DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 13, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 and 13-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al (U.S. Patent Pub. No. 2016/0126956; already of record) and in view of Kashihara et al (U.S. Patent Pub. No. 2019/0260363; already of record).
Regarding claim 1, Ryu discloses a negative level shifter (10B’), (fig. 10, [0153]), comprising:
a first level shifter (11B’) including an input circuit (MP21, MP22, MP23 and MP24), a shielding circuit (MN25 and MN26) and a load circuit (11B’-2), (fig. 10, [0155]); and
a second level shifter (12B’) configured to generate a level (i.e. second level shifter 12B’ may output a signal have a low voltage of about -5.5V and a high voltage which is level shifted to about 0V) different from a level of the first level shifter (i.e. first level shifter 11B’ may output a signal having a low voltage of about -5.5V to about -5.0V and a high voltage which is shifted to about -1.0V to about -2.5V), (fig. 10, [0126]),
wherein the shielding circuit (MN25 and MN26) includes an NMOS transistor (MN25 and MN26) having a drain terminal (ND3 and ND4) directly coupled to an output (ND3 and ND4) of the input circuit (MP21, MP22, MP23 and MP24), a source terminal (ND5 and ND6) and a gate terminal connected to a ground (i.e. the voltage GND of about 0V may be applied to a gate terminal of the NMOS transistor MN25 and MN26), (fig. 10, [0161-0162]), and
wherein the gate terminal of the shielding circuit (MN25 and MN26) is directly connected with a gate terminal of the input circuit (MP21, MP22, MP23 and MP24), (i.e. gate terminals of MN25 and MN26 are directly connected to gate terminals of MP23 and MP24 as shown in fig. 10), [0156].
However, Ryu does not mention wherein the shielding circuit includes an NMOS transistor having a source terminal coupled to a body region to shift voltage from the input circuit downward.
In a similar field of endeavor, Kashihara teaches wherein the shielding circuit includes an NMOS transistor (MNE1P and MNE1N) having a drain terminal directly coupled to an output (output node 153 and 154) of the input circuit (i.e. MPINN, MPINP, MPE1P and MPE1N), a source terminal coupled to a body region (i.e. each of the back gates is coupled to the respective sources) to shift voltage from the input circuit (MPINN, MPINP, MPE1P and MPE1N) downward and a gate terminal connected to a ground (i.e. gate terminal of MNE1P and MNE1N are coupled to ground voltage VSS when the negative high-voltage power supply is active), (fig. 8, [0106, 0110-0118 and 0121]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Ryu, by specifically providing the NMOS transistor, as taught by Kashihara, for the purpose of having a stable operation, [0015].
Regarding claim 2, Ryu discloses wherein the input circuit (MP21, MP22, MP23 and MP24) comprises:
a first PMOS transistor (MP22) configured to receive an inverting input signal (INb); and
a second PMOS transistor (MP21) configured to receive an input signal (IN),
wherein body regions of the first PMOS transistor and the second PMOS transistor are connected to each other, (fig. 10, [0155-0156]).
Regarding claim 3, Ryu discloses wherein the NMOS transistor (MN25 and MN26) comprises:
a first NMOS transistor (MN26) connected to the first PMOS transistor (MP22) through a first node (ND4) and MP24; and
a second NMOS transistor (MN25) connected to the second PMOS transistor (MP21) through a second node (ND3) and MP23, (fig. 10, [0155 and 0162]).
Regarding claim 4, Ryu discloses wherein the first PMOS transistor (MP22) and the second PMOS transistor (MP21) are high voltage elements (i.e. receives high voltage DVDD), and
wherein the first NMOS transistor (MN26) and the second NMOS transistor (MN25) are medium voltage elements (i.e. receiving ground GND voltage) having an operating voltage lower than the high voltage elements, (fig. 10, [0156 and 0169]).
Regarding claim 5, Ryu discloses wherein a first voltage (DVDD) is applied to the body regions of the first PMOS transistor (MP22) and the second PMOS transistor (MP21), and
wherein the first PMOS transistor (MP22) and the second PMOS transistor (MP21) are formed in a same well region (i.e. the body of MP22 and MP21 are connected to each other), (fig. 10, [0161 and 0164]).
Regarding claim 6, Ryu discloses wherein a drain terminal of the first NMOS transistor (MN26) is connected to a first node (ND4), a gate terminal connected to ground (GND), and a source terminal connected to a third node (ND6), and
wherein a drain terminal of the second NMOS transistor (MN25) is connected to a second node (ND3), a gate terminal connected to the ground (GND), and a source terminal connected to a fourth node (ND5), (fig. 10, [0162]).
Regarding claim 7, Ryu discloses wherein the load circuit (11B’-2) comprises:
a third NMOS transistor (MN24) including a drain terminal and a gate terminal connected to the third node (ND6) and a source terminal connected to a fifth node (ND8);
a fourth NMOS transistor (MN23) including a drain terminal and a gate terminal connected to the fourth node (ND5) and a source terminal connected to a sixth node (ND7);
a fifth NMOS transistor (MN22) including a drain terminal connected to the fifth node (ND8), a gate terminal connected to the fourth node (ND5), and a source terminal to which a negative voltage (AVDDN) is applied; and
a sixth NMOS transistor (MN21) including a drain terminal connected to the sixth node (ND7), a gate terminal connected to the third node (ND6), and a source terminal to which the negative voltage VENG (AVDDN) is applied, and
wherein the negative voltage VENG (AVDDN) is applied to body regions of the third NMOS transistor to sixth NMOS transistor (MN24, MN23, MN22 and MN21, respectively), (fig. 10, [0163-0164]).
Regarding claim 8, Ryu discloses wherein the second level shifter (12B’), when an inverting input signal (INb) of 0 V (low state 0V) and a first voltage (high state 1.8V) as an input signal are inputted to the first level shifter (11B’), outputs a negative voltage (-5.5V) through an inverting output terminal (OUTb) and output a ground voltage (0V) through an output terminal (OUT), (fig. 10, [0170 and 0176]).
Regarding claim 9, Ryu discloses wherein the second level shifter (12B’) comprises:
a first PMOS transistor (MP25) including a source terminal connected to the ground (0 V) (GND), a gate terminal connected to an eighth node (ND10), and a drain terminal connected to a seventh node (ND9);
a second PMOS transistor (MP26) including a source terminal connected to the ground (0 V) (GND), a gate terminal connected to a seventh node (ND9), and a drain terminal connected to the eighth node (ND10);
a seventh NMOS transistor (MN27) including a drain terminal connected to a seventh node (ND9), a gate terminal connected to a sixth node (ND8) of the first level shifter (11b’), and a source terminal to which a negative voltage VNEG (AVDDN) is applied; and
an eighth NMOS transistor (MN28) including a drain terminal connected to the eighth node (ND10), a gate terminal connected to a fifth node (ND7) of the first level shifter (11b’), and a source terminal to which a negative voltage VNEG (AVDDN) is applied, (fig. 10, [0157-0158 and 0167-0168]).
Regarding claim 10, Ryu discloses wherein the first PMOS transistor (MP25), the second PMOS transistor (MP26), the seventh NMOS transistor (MN27), and the eighth NMOS transistor (MN28) are medium voltage elements (i.e. level shifters of the two stages may be embodied by using medium-voltage-standard transistors), (fig. 10, [0061]).
Regarding claim 13, Ryu discloses a display device (100), (fig. 1), comprising:
a display panel (110) with a plurality of gate lines (G1-Gm) and a plurality of source lines (S1-Sn), (fig. 1, [0056-0057]); and
a panel control circuit (120 and 130) for driving the gate line (G1-Gm) and the source line (S1-Sn), (fig. 1, [0059 and 0063]);
wherein the panel control circuit (120 and 130) includes: a first level shifter (11B’) including an input circuit (MP21, MP22, MP23 and MP24), a shielding circuit (MN25 and MN26), and a load circuit (11B’-2) and a second level shifter (12B’) connected to the load circuit (11B’-2) (fig. 10, [0155-0157]),
wherein the shielding circuit NMOS transistors (MN25 and MN26) having a drain terminals (ND3 and ND4) directly coupled to an output (ND3 and ND4) of the input circuit (MP21, MP22, MP23 and MP24), and source terminals (ND5 and ND6), and gate terminals connected to a ground (i.e. the voltage GND of about 0V may be applied to a gate terminals of the NMOS transistors MN25 and MN26), (fig. 10, [0161-0162]), and
wherein the gate terminal of the shielding circuit (MN25 and MN26) is directly connected with a gate terminal of the input circuit (MP21, MP22, MP23 and MP24), (i.e. gate terminals of MN25 and MN26 are directly connected to gate terminals of MP23 and MP24 as shown in fig. 10), [0156].
However, Ryu does not mention wherein the shielding circuit NMOS transistors source terminals coupled to a body region to shift voltage from the input circuit downward.
In a similar field of endeavor, Kashihara teaches wherein the shielding circuit NMOS transistors (MNE1P and MNE1N) having drain terminals directly coupled to an output (i.e. output node 153 and 154) of the input circuit (i.e. MPINN, MPINP, MPE1P and MPE1N) and source terminals coupled to a body region (i.e. each of the back gates is coupled to the respective sources) to shift voltage from the input circuit (MPINN, MPINP, MPE1P and MPE1N) downward, and gate terminals connected to a ground (i.e. gate terminal of MNE1P and MNE1N are coupled to ground voltage VSS when the negative high-voltage power supply is active), (fig. 8, [0106, 0110-0118 and 0121]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Ryu, by specifically providing the NMOS transistor, as taught by Kashihara, for the purpose of having a stable operation, [0015].
Regarding claim 14, please refer to claim 2 for details.
Regarding claim 15, Ryu discloses wherein the shielding circuit (MN25 and MN26) comprises:
a first NMOS transistor (MN26) connected to the first PMOS transistor (MP22) through a first node (ND4) and MP24; and
a second NMOS transistor (MN25) connected to the second PMOS transistor (MP21) through a second node (ND3) and MP23, (fig. 10, [0155 and 0162]).
However, Ryu does not mention wherein a source terminal and a body region of the first NMOS transistor are connected to each other.
In a similar field of endeavor, Kashihara teaches wherein a source terminal and a body region (back gate) of the first NMOS transistor (MNE1P) are connected to each other, and a source terminal and a body region (back gate) of the second NMOS transistor (MNE1N) are connected to each other (i.e. To the gates of the breakdown-voltage relaxing PMOS transistors MPE1P and MPE1N, the ground voltage VSS is supplied. Each of the back gates is coupled to the respective sources), (fig. 8, [0112]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Ryu, by specifically providing the source terminal and the body region of the NMOS transistor to be connected to each other, as taught by Kashihara, for the purpose of having a different circuit connection.
Regarding claim 16, Ryu discloses wherein the shielding circuit (MN25 and MN26) operates within a medium voltage operating region (i.e. level shifters of the two stages may be embodied by using medium-voltage-standard transistors), (fig. 10, [0060-0061]).
Regarding claim 17, Ryu discloses wherein the first PMOS transistor (MP22) and the second PMOS transistor (MP21) are high voltage elements (i.e. receives high voltage DVDD), and
wherein the first NMOS transistor (MN26) and the second NMOS transistor (MN25) are medium voltage elements (i.e. receiving ground GND voltage) having a lower operating voltage than the high voltage element, (fig. 10, [0156 and 0169]).
Regarding claim 18, Ryu discloses wherein the second level shifter (12b’), when an inverting input signal (INb) of 0 V (low state 0V) and a first voltage (high state 1.8V) as an input signal are inputted to the first level shifter (11b’), outputs a negative voltage (-5.5V) and outputs a ground voltage (0V) through an output terminal (i.e. output terminals OUTb and OUT), (fig. 10, [0170 and 0176]).
Allowable Subject Matter
Claims 11-12 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments, see page 9, filed January 13, 2026, with respect to the rejection(s) of claim(s) 1 and 13 under U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different interpretation of the reference of Kashihara, embodiment of figure 8.
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG D PHAM whose telephone number is (571)270-5573. The examiner can normally be reached Monday - Friday: 9am-5pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh D Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LONG D PHAM/Primary Examiner, Art Unit 2623