Technology areas: Communications • Semiconductors, Circuits & Optics • Medical Devices & Mechanical Engineering
5 pending office actions • 5 art units • 5 examiners • 0 of 5 (0%) have an AI response strategy ready • 9 patents granted in the last 365 days
MagnaChip Semiconductor Ltd. is currently managing 6 pending office actions within the Semiconductors, Circuits & Optics technology area. These actions are distributed across distinct examiners and a matching number of distinct art units, showing a broad prosecution front. FIGUEROA-GIBSON, GLORYVID is the busiest examiner for the portfolio, currently handling 1 pending office action.
The distribution of 6 pending office actions across the various art units indicates that the company's technical filings are being evaluated by a wide range of specialized groups. This variety requires a flexible legal approach, as each of the distinct examiners may have different interpretations of the prior art. The fact that the busiest examiner, FIGUEROA-GIBSON, GLORYVID, only holds 1 pending action suggests that no single individual dominates the current workload.
With the pending office actions in the Semiconductors, Circuits & Optics sector, the company must maintain oversight across multiple examination tracks. The use of multiple distinct art units suggests that the underlying technologies are varied enough to trigger different classification standards. Practitioners should prepare for unique sets of examiner feedback, as the portfolio is currently spread across the patent office's organizational structure.
Based on the USPTO statutory response window for each pending office action. 2 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 3 (60%) |
| Multi-statute (no §101) | 2 (40%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| FIGUEROA-GIBSON, GLORYVID | 1 | 66.1% | +9.9% |
| MICHAUD, NICHOLAS BRIAN | 1 | 75.0% | +30.0% |
| BRAWNER, CHARLES RILEY | 1 | 75.9% | +11.2% |
| KIELIN, ERIK J | 1 | 67.6% | +5.1% |
| BEARDSLEY, JONAS TYLER | 1 | 60.9% | +28.5% |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18411252 | SUPER JUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | MICHAUD, NICHOLAS BRIAN | — |
| 18457240 | WAFER ANNEALING APPARATUS AND METHOD | BRAWNER, CHARLES RILEY | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18411252 | SUPER JUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | MICHAUD, NICHOLAS BRIAN | — |
| 18457240 | WAFER ANNEALING APPARATUS AND METHOD | BRAWNER, CHARLES RILEY | — |
| 18110015 | POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | BEARDSLEY, JONAS TYLER | — |
| Art Unit | Apps |
|---|---|
| 2628 | 1 |
| 2818 | 1 |
| 3762 | 1 |
| 2814 | 1 |
| 2811 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18644926 | DISPLAY PANEL DRIVING DEVICE AND METHOD | FIGUEROA-GIBSON, GLORYVID | 2628 | §103 | Final Rejection | 13d | Pending | Apr 24, 2024 |
| 18411252 | SUPER JUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | MICHAUD, NICHOLAS BRIAN | 2818 | §102§103§112 | Non-Final OA | — | Pending | Jan 12, 2024 |
| 18457240 | WAFER ANNEALING APPARATUS AND METHOD | BRAWNER, CHARLES RILEY | 3762 | §103§112 | Non-Final OA | — | Pending | Aug 28, 2023 |
| 18449373 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR | KIELIN, ERIK J | 2814 | §103 | Non-Final OA | 22d overdue | Pending | Aug 14, 2023 |
| 18110015 | POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | BEARDSLEY, JONAS TYLER | 2811 | §103 | Non-Final OA | — | Pending | Feb 15, 2023 |
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