DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/13/26 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 8-10, 12, 13 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nomura (US 10,199,085) in view of Villemin (US 2018/0276914) and Pasala (US 11,621,049).
Regarding claim 1, Nomura discloses a storage device to identify a die with a defective temperature sensor (intended use), the storage device comprises: (see Figure 3, slices) a memory device including multiple dies, wherein each die includes a temperature sensor; and a controller to execute a defective temperature sensor scheme to obtain a temperature for a first die in the memory device, compare the first die temperature against a benchmark (see Figure 8 for example).
Nomura fails to teach determining that the first die includes a defective temperature sensor if there is a temperature variance in the firs die temperature and the benchmark and if the temperature variance is greater than a die temperature variation threshold and excluding the first die temperature from thermal calculations wherein the defective temperature sensor scheme includes one of comparing the first temperature die against temperature of other dies and determining that the temperature variance of the first die temperature from a second die temperature is outside the die temperature variation threshold and excluding the first die temperature from thermal calculations
However, it was known at the time of filing to perform such a comparison to test temperature sensors for defects by comparing the variance between the temperature output of the sensor and a local device temperature and determining a defect with the sensor when the variance is greater than a threshold (see Villemin paragraphs 0018-0033) wherein a defective temperature sensor scheme includes comparing the first temperature die against temperature of other dies (Tcell’s compared) and determining that the temperature variance of the first die temperature from a second die temperature is outside the die temperature variation threshold (see paragraph 0020 for example).
Further, Pasala teaches a sensor testing configuration wherein when a faulty sensor is detected, it is excluded from thermal calculations (see Figure 3, 350) such as a shutdown (see column 2, lines 12+).
Therefore, it would have been obvious to one having ordinary skill at the time of filing to provide such a sensor defect determination with the device of Nomura in order to remove faulty temperature readings which would incorrectly affect the temperature based operations.
Regarding claim 2, Nomura discloses the storage device of claim 1, wherein the controller executes the defective temperature sensor scheme during initialization of the storage device (see Villemin, paragraph 0040).
Regarding claim 3, Nomura discloses the storage device of claim 1, but fails to specifically teach the die temperature variation threshold is a configurable value based on at least one hardware value. However, it would have been obvious to one having ordinary skill at the time of filing to configure the variation threshold based on a hardware variable (e.g. distance to sensitive components) in order to protect the sensitive components and/or the calculations for their optimal performance.
Regarding claim 4, Nomura as modified above discloses the storage device of claim 1, but fails to teach excluding from thermal calculations wherein the thermal calculations include thermal shut down calculations (see Pasala, Figure 3, 350).
Regarding claim 8, Nomura discloses the storage device of claim 1, wherein the defective temperature sensor scheme includes a third defective temperature sensor scheme wherein the controller: determines that temperatures of dies in the memory device are within the die temperature variation threshold, compares a temperature of each die against a temperature of an internal temperature sensor, determines that there is a temperature variance between a die temperature and the temperature of an internal temperature sensor, and that the temperature variance is greater than the die temperature variation threshold; and determines that a die with a temperature variance that is greater than the die temperature variation threshold includes the defective temperature sensor (in view of the modification above, Nomura includes multiple sensors and it would have been obvious to expand the testing to all the sensors of Nomura in order to prevent faulty sensor readings).
Regarding claim 9, Nomura discloses the storage device of claim 8, wherein the controller determines that no single die on the memory device has a temperature variance outside the die temperature variation threshold when compared to die temperature of another die on the memory device (see Figures 1, 2 of Villemen—Output diagnostic).
Regarding claim 10, Nomura discloses the storage device of claim 8, wherein the internal temperature sensor is set to provide an ambient temperature of the storage device (see Villemen, paragraph 0027).
Regarding claim 12, the claim recites substantially the same features as claim 1 above and is rejected on the same basis.
Regarding claim 13, Nomura discloses the method of claim 12, further comprising executing the defective temperature sensor scheme one of before performing thermal calculations, during initialization of the storage device, and at other predefined times (see rejection of claim 2 above).
Regarding claim 16, Nomura discloses the method of claim 12, further comprising executing a third defective temperature sensor scheme wherein: the comparing comprises determining that temperatures of dies in the memory device are within the die temperature variation threshold and comparing a temperature of each die against a temperature of an internal temperature sensor, and the determining comprises determining that there is a temperature variance between a die temperature and the temperature of an internal temperature sensor, that the temperature variance is greater than the die temperature variation threshold, and that a die with a temperature variance that is greater than the die temperature variation threshold includes the defective temperature sensor (see rejection of claim 8 above).
Regarding claim 18, the claim is directed to subject matter found in rejected claim 1 above and is rejected on the same basis.
Claim(s) 11 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nomura (US 10,199,085), Villemin (US 2018/0276914), Pasala and further in view of Oden (US 6,223,817).
Regarding claim 11 and 17, Nomura discloses the storage device of claim 1, but fails to teach the defective temperature sensor scheme includes a fourth defective temperature sensor scheme wherein the controller checks a firmware to determine if the first die includes the defective temperature sensor.
However, as Oden teaches, it was known at the time of filing to store in memory a flag indicating that a sensor is faulty as a signal for other circuitry to know of the fault (see column 6, lines 30+). Therefore, it would have been obvious to one having ordinary skill at the time of filing provide for the storing of a fault information in a memory area and for the controller to check for the flag in order to avoid using a faulty thermal sensor.
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nomura (US 10,199,085), in view of Pasala and Oden (US 6,223,817).
Regarding claim 18, Nomura discloses a storage device to identify a die with a defective temperature sensor, the storage device comprises: a memory device including multiple dies (see Figure 3, slices), wherein each die includes a temperature sensor; and a controller (1) to execute a defective temperature sensor scheme (see Figure 8 for example).
But Nomura fails to teach wherein in executing the defective temperature scheme, the controller obtains information from a firmware to determine if a first die includes the defective temperature sensor and excludes the first die temperature from thermal calculations.
However, as Oden teaches, it was known at the time of filing to store in memory a flag indicating that a sensor is faulty as a signal for other circuitry to know of the fault (see column 6, lines 30+).
Further, Pasala teaches a sensor testing configuration wherein when a faulty sensor is detected, it is excluded from thermal calculations (see Figure 3, 350) such as a shutdown (see column 2, lines 12+).
Therefore, it would have been obvious to one having ordinary skill at the time of filing provide for the storing of a fault information in a memory area and for the controller to check for the flag in order to avoid using a faulty thermal sensor and to exclude said sensor temperature from calculations in order to prevent erroneous calculations.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nomura (US 10,199,085), Villemin in view of Pasala and Oden (US 6,223,817).
Claims 19 and 20 recite additional features not taught by the combination of Nomura, Villemin and Psala. However, as noted in the rejection of claim 18 above these features and reasons for combination are taught by Oden and claims 19 and 20 are rejected on the same basis.
Response to Arguments
Applicant's arguments have been fully considered but are not persuasive. Applicant seems to argue principally that the combinations fail to each the claimed “ASIC” limitations (see page 14). However, the limitation is not present in all independent claims and where it is present it is an alternative and not required.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS KING whose telephone number is (571)272-2311. The examiner can normally be reached M-F: 9:00AM-5:30PM.
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/DOUGLAS KING/Primary Examiner, Art Unit 2824
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