DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 16, 17 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sriram et al. (US 2019/0333767).
Regarding claim 1, Sriram discloses a transistor comprising:
a group III-Nitride channel layer (104, fig. 5 and paragraph 0072);
a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III- Nitride channel layer (106, fig. 5 and paragraph 0072);
a low resistance contact layer on the group III-Nitride barrier layer (150, fig. 5 and paragraph 0075) and/or on the group III-Nitride channel layer (250, fig. 6 and paragraph 0081);
a source electrically coupled to the group III-Nitride barrier layer (110, fig. 5 and paragraph 0073);
a drain electrically coupled to the group III-Nitride barrier layer (114, fig. 5 and paragraph 0073); and
a gate on the group III-Nitride barrier layer (112, fig. 5 and paragraph 0074),
wherein at least one of the drain and the source are arranged on the low resistance contact layer (110 on 150, fig. 5 and paragraph 0076).
Regarding claim 2, Sriram further discloses wherein the low resistance contact layer comprises GaN doped with silicon and/or germanium (250, fig. 6 and paragraphs 0076-0078, 0081-0082).
Regarding claim 3, Sriram further discloses wherein the low resistance contact layer comprises n-type GaN (250, fig. 6 and paragraphs 0081-0082).
Regarding claim 4, Sriram further discloses wherein the low resistance contact layer (150, fig. 5) comprises a sputtered layer, a physical vapor deposited layer, a doped GaN film layer, and/or a n-type sputtered GaN layer (paragraph 0076).
Regarding claim 6, Sriram further discloses wherein the low resistance contact layer (150, fig. 5) comprises a sputtered layer, a layer formed by sputtering, a physical vapor deposited layer, a layer formed by physical vapor deposition, a doped GaN film layer, a n-type sputtered GaN layer, and/or a layer formed by sputtering n-type GaN (paragraphs 0072-0076).
Regarding claim 16, Sriram further discloses wherein the low resistance contact layer is configured to improve a performance of the transistor (paragraph 0067).
Regarding claim 17, Sriram further discloses wherein the low resistance contact layer is configured to improve a radiofrequency performance of the transistor by reducing on-resistance (paragraph 0075).
Regarding claim 21, Sriram further discloses comprising a field plate, wherein the field plate is arranged on a spacer layer and electrically isolated from the gate by the spacer layer (paragraph 0130).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Sriram et al. (US 2019/0333767).
Regarding claim 5, Sriram discloses the transistor of claim 1, as mentioned above. Sriram further discloses wherein the low resistance contact layer comprises an n-type GaN layer (250, fig. 6 and paragraphs 0078-0081), and wherein the n-type GaN layer is configured to lower an electrostatic barrier for electron injection into the group III-Nitride channel (paragraph 0081). Sriram does not explicitly disclose wherein the low resistance GaN contact layer is a sputtered GaN layer. Sriram discloses layer 150 formed from an implantation process (paragraphs 0075-0077). However, a n-type sputtered GaN layer would be deemed as a known functional equivalent in the art of semiconductor manufacturing and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing.
Regarding claims 9 and 11, Sriram discloses the transistor of claim 1, as mentioned above. Sriram further discloses wherein the drain and/or source is arranged on the low resistance contact layer (paragraph 0077) and wherein the ohmic structure can include depositing a metallic material (paragraph 0077). Sriram does not explicitly disclose wherein there is one or more intervening layers therebetween or wherein the low resistance contact layer is arranged on the group III-Nitride channel layer with one or more intervening layers therebetween. However, the use of an intervening layer would be deemed obvious to one of ordinary skill in the art at the time of filing since such was widely practiced at the time and the Examiner take official notice of such practice.
Response to Arguments
Applicant's arguments filed 8/7/26 have been fully considered but they are not persuasive.
First, all arguments pertaining to the deposition method of the low resistance contact layer are moot in regards to independent claim 1, since the claim contains no such language. Applicant further argues that Sriram does not teach a low resistance contact layer on the group III-Nitride barrier layer and/or on the group III-Nitride channel because “Sriram expressly teaches that source ohmic structure 150 includes silicon and/or germanium implanted into barrier layer 106 and is formed as an implanted region that controls current flow through the barrier layer as the barrier layer becomes increasingly forward biased.” Examiner disagrees. As mentioned in the above rejection, Sriram’s ohmic structure (150, fig. 5) is a low resistance contact layer on the group III-Nitride barrier layer and Sriram’s ohmic structure (250, fig. 6) is a low resistance contact layer on the group III-Nitride channel. Sriram’s ohmic structures 150, 250 have an n+ conductivity and the channel layer has an n- conductivity (paragraphs 0076, 0082). This is achieved by implanting silicon and/or germanium into the barrier layer, which reduces the resistance relative to the n- conductivity of the channel because the relative electron concentration of the n+ doping is very high which lowers the resistivity. Thus Sriram absolutely discloses the limitation “a low resistance contact layer on the group III-Nitride barrier layer and/or the group III-Nitride channel layer”. Furthermore, it is noted that Applicant’s dependent claim 2 states, “…wherein the low resistance contact layer comprises GaN doped with silicon and/or germanium”, which is what Applicant clearly states that Sriram expressly teaches.
Applicant has amended claims 9 and 11 to further include one or more intervening layers between the low resistance contact layer and the group III-Nitride channel layer, and argues that the Official Notice would not apply to the newly amended dual-spatial relationship. Examiner disagrees. As mentioned in the above rejection, Sriram ohmic structure may also be formed by etching into one or more of the device layers and depositing a metallic material. As such, whenever a metallic material is deposited in a semiconductor device it would be deemed obvious to one of ordinary skill in the art to include an intervening layer such as a barrier layer to prevent migration. Therefore, Examiner stands by the Official Notice. Applicant is advised to amend the independent claim to more precisely define Applicant’s invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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/DOUGLAS M MENZ/ Primary Examiner, Art Unit 2897 10/7/26
