DETAILED ACTION
This action is in response to an amendment to application 18/384023, filed on 7/28/2026. Claims 1-3, 6-12, 15-18, and 21-23 are pending; claims 4-5, 13-14, 19-20 are cancelled and claims 21-23 are new. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 6-12, 15-18, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over USPGPUB 2021/0103433, hereinafter “Kerr,” and WIPO publication WO2023195658A1, hereinafter “Kim.” A machine translation of Kim is cited in these rejections and a copy of that machine translation is attached to this action.
Regarding claim 1, Kerr discloses “A method, comprising:
receiving artificial intelligence (AI) model code containing a specialized function for a first one or more types of hardware platforms; (see, e.g., Kerr, fig. 4 & associated text; para. 53; “a programmer has written an implementation of a basic convolution with hooks in place, as represented by static kernels 402 to be compiled by a language-appropriate compiler 404.”; fig. 5 sec. 502; “Receive . . . one or more function objects”)
training a transformer model defined in the Al model code using only the first one or more types of hardware platforms; (see, e.g., Kerr, fig. 6B & associated text; para. 64; “inference and/or training logic 615 illustrated in FIG. 6B may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware or other hardware, such as field programmable gate arrays (FPGAs).”)
converting, by a compiler, the specialized function into executable code for a second type of hardware platform; and (see, e.g., Kerr, fig. 4 & associated text; para. 53; “a transformation and optimization module 412 can be used as discussed herein, along with an code generator module 414 to generate the final complied binary or lowered machine code for execution.”; fig. 5 sec. 508-510; “an in-lining pass is performed 508 in order to insert compiled function(s) at one or more call locations corresponding to hooks in the partially compiled kernel. In at least one embodiment, one or more optimizations are performed.”)
performing inference only on the second type of hardware platform using the trained transformer model and the executable code.” (see, e.g., Kerr, fig. 6B & associated text; para. 64; “inference and/or training logic 615 illustrated in FIG. 6B may be used in conjunction with an application-specific integrated circuit (ASIC), such as Tensorflow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp.”).
Kerr arguably does not disclose the further limitation “wherein the second type of hardware platform comprises a model-specific chipset optimized to execute only transformer models.” More specifically, Kerr does disclose optimized chipsets (see, e.g., Kerr, para. 63; “an application-specific integrated circuit (“ASIC”), such as Tensorflow® Processing Unit from Google1 . . . or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp.”)2 but arguably does not disclose chipsets optimized to execute “only transformer models” as claimed. However, Kim discloses a chipset specifically optimized to execute only transformer models. For example, at para. 40, Kim discloses that “[t]he present disclosure provides a low-cost multi-FPGA acceleration system (hereinafter referred to as the 'multi FPGA acceleration system') that executes end-to-end transformer model inference with high throughput and low latency in both the summarization and generation stages. Multi-FPGA acceleration systems can use model parallelism with lightweight routers to distribute the same workload across devices through fast P2P (peer-to-peer) communication.”
Ker and Kim are directed toward machine learning and therefore are analogous art. On or before the effective filing date of the instant application, one of ordinary skill in the art would have deemed it obvious to try to combine the specialized compilation method of Kerr with the model-specific hardware acceleration of Kim, thereby obtaining the invention of the instant claim. A clear and predictable benefit of so combining would have been “that “Multi-FPGA acceleration systems achieve 3.78 times faster speed and 3.99 times greater energy efficiency compared to using four of the latest GPUs for the latest GPT language models, while maintaining acceptable accuracy for transformer-based language services.” (Kim, para. 40). Accordingly, the instant claim is unpatentable over the combination of Kerr and Kim.
Regarding claim 2, the combination of Kerr and Kim renders obvious “The method of claim 1, wherein the first one or more types of hardware platforms are capable of executing different types of Al models, (see, e.g., Kerr, para. 63; “may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware”) and the second type of hardware platform is optimized for only one type of Al model.” (see, e.g., Kim, para. 40).
Regarding claim 3, the combination of Kerr and Kim renders obvious “The method of claim 2, wherein the first one or more types of hardware platforms comprise at least one of a central processing unit (CPU) or a graphics processing unit (GPU).” (see, e.g., Kerr, para. 63; “may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware”).
Regarding claim 6, the combination of Kerr and Kim renders obvious “The method of claim 1, wherein the specialized function, when compiled, results in a fused kernel in the first and second type of hardware platforms.” (see, e.g., Kerr, para. 42-43, 46-47; fig. 4 sec. 408, 416; para. 53; “a procedural code generator 408 or other application interface can compile user-supplied functionality to be fused with the kernels. In at least one embodiment, a compilation manager 416 can assist with the compilation, which may include various instances of compiled code 406 to be fused.”; para. 54; “one or more application-supplied functions can be fused with a coded implementation of one or more compute-limited workloads”).
Regarding claim 7, the combination of Kerr and Kim renders obvious “The method of claim 6, wherein the specialized function comprises a plurality of lower-level functions defined by a machine learning (ML) or Al framework that are executed sequentially by the fused kernel.” (see, e.g., Kerr, para. 47, 53-54; “one or more application-supplied functions can be fused with a coded implementation of one or more compute-limited workloads . . . such fusion can provide for a performance and energy improvement with respect to separate execution . . . an architecture can take advantage of specialized compiler behavior that would not be feasible to disclose to compile an entire application . . . such architecture can enable a hardware vendor to combine sensitive IP, or proprietary functionality, with user-supplied functionality without disclosing the proprietary functionality . . . such fusion can also reduce overall code size for the functionality.”).
Regarding claim 8, the combination of Kerr and Kim renders obvious “The method of claim 7, wherein converting the specialized function into the executable code further comprises: translating, by the compiler, the specialized function into an intermediate representation (IR); (see, e.g., Kerr, fig. 4 & associated text; para. 53; fig. 5 sec. 505-506; “each function object is compiled 504 to obtain an intermediate representation. In at least one embodiment, an intermediate, or partially-compiled, representation of a compute-limited operation, such as a convolution kernel, is obtained 506.”) and
converting the IR into the executable code, wherein the IR comprises values of arguments that configure the second type of hardware platform to perform the plurality of lower-level functions defined in the specialized function.” (see, e.g., Kerr, fig. 4 & associated text; para. 53-54; “an architecture can take advantage of specialized compiler behavior that would not be feasible to disclose to compile an entire application . . . such architecture can enable a hardware vendor to combine sensitive IP, or proprietary functionality, with user-supplied functionality without disclosing the proprietary functionality.”; fig. 5 sec. 508-510; “an in-lining pass is performed 508 in order to insert compiled function(s) at one or more call locations corresponding to hooks in the partially compiled kernel. In at least one embodiment, one or more optimizations are performed.”).
Regarding claim 9, the combination of Kerr and Kim renders obvious “The method of claim 1, wherein converting the specialized function into the executable code further comprises: translating, by the compiler, the specialized function into an intermediate representation (IR); (see, e.g., Kerr, fig. 4 & associated text; para. 53; fig. 5 sec. 505-506; “each function object is compiled 504 to obtain an intermediate representation. In at least one embodiment, an intermediate, or partially-compiled, representation of a compute-limited operation, such as a convolution kernel, is obtained 506.”) and
converting the IR into the executable code, wherein the IR comprises values of arguments for performing at least one of matrix multiplication or attention operations on the second type of hardware platform.” (see, e.g., Kerr, fig. 4 & associated text; para. 52-54; “a matrix multiply”; “an architecture can take advantage of specialized compiler behavior that would not be feasible to disclose to compile an entire application . . . such architecture can enable a hardware vendor to combine sensitive IP, or proprietary functionality, with user-supplied functionality without disclosing the proprietary functionality.”; fig. 5 sec. 508-510; “an in-lining pass is performed 508 in order to insert compiled function(s) at one or more call locations corresponding to hooks in the partially compiled kernel. In at least one embodiment, one or more optimizations are performed.”).
Regarding claim 10, the combination of Kerr and Kim renders obvious “The method of claim 1, wherein the compiler supports a plurality of specialized functions for the first one or more types of hardware platforms but supports only a limited number of lower-level functions of an ML or Al framework.” (see, e.g., Kerr, fig. 4 & associated text; para. 53-54; “an architecture can take advantage of specialized compiler behavior that would not be feasible to disclose to compile an entire application . . . such architecture can enable a hardware vendor to combine sensitive IP, or proprietary functionality, with user-supplied functionality without disclosing the proprietary functionality.”; fig. 5 sec. 508-510; “an in-lining pass is performed 508 in order to insert compiled function(s) at one or more call locations corresponding to hooks in the partially compiled kernel. In at least one embodiment, one or more optimizations are performed.”).
Regarding claim 11, Kerr discloses “A non-transitory computer readable medium having program instructions embodied therewith, the program instructions executable by a processor to perform an operation, the operation comprising:
receiving an artificial intelligence (Al) model code containing a specialized function for a first one or more types of hardware platforms; (see, e.g., Kerr, fig. 4 & associated text; para. 53; “a programmer has written an implementation of a basic convolution with hooks in place, as represented by static kernels 402 to be compiled by a language-appropriate compiler 404.”; fig. 5 sec. 502; “Receive . . . one or more function objects”)
translating, by a compiler, the specialized function into an intermediate representation (IR); (see, e.g., Kerr, fig. 4 & associated text; para. 53; fig. 5 sec. 505-506; “each function object is compiled 504 to obtain an intermediate representation. In at least one embodiment, an intermediate, or partially-compiled, representation of a compute-limited operation, such as a convolution kernel, is obtained 506.”) and
converting, by the compiler, the IR into executable code for a second type of hardware platform, (see, e.g., Kerr, fig. 4 & associated text; para. 53-54; “an architecture can take advantage of specialized compiler behavior that would not be feasible to disclose to compile an entire application . . . such architecture can enable a hardware vendor to combine sensitive IP, or proprietary functionality, with user-supplied functionality without disclosing the proprietary functionality.”; fig. 5 sec. 508-510; “an in-lining pass is performed 508 in order to insert compiled function(s) at one or more call locations corresponding to hooks in the partially compiled kernel. In at least one embodiment, one or more optimizations are performed.”)
wherein the first one or more types of hardware platforms are used only for training a transformer model defined in the AI model code (see, e.g., Kerr, para. 63; “an application-specific integrated circuit (“ASIC”), such as Tensorflow®3 Processing Unit from Google . . . or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp.”)4 and the second type of hardware platform is used only for performing inference using the trained transformer model and the executable code.” (see, e.g., Kerr, para. 63; “an application-specific integrated circuit (“ASIC”), such as . . . an inference processing unit (IPU) from Graphcore™).5
Kerr arguably does not disclose the further limitation “and wherein the second type of hardware platform comprises a model-specific chipset optimized to execute only transformer models.” More specifically, Kerr does disclose optimized chipsets (see, e.g., Kerr, para. 63; “an application-specific integrated circuit (“ASIC”), such as Tensorflow® Processing Unit from Google6 . . . or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp.”)7 but arguably does not disclose chipsets optimized to execute “only transformer models” as claimed. However, Kim discloses a chipset specifically optimized to execute only transformer models. For example, at para. 40, Kim discloses that “[t]he present disclosure provides a low-cost multi-FPGA acceleration system (hereinafter referred to as the 'multi FPGA acceleration system') that executes end-to-end transformer model inference with high throughput and low latency in both the summarization and generation stages. Multi-FPGA acceleration systems can use model parallelism with lightweight routers to distribute the same workload across devices through fast P2P (peer-to-peer) communication.”
Ker and Kim are directed toward machine learning and therefore are analogous art. On or before the effective filing date of the instant application, one of ordinary skill in the art would have deemed it obvious to try to combine the specialized compilation method of Kerr with the model-specific hardware acceleration of Kim, thereby obtaining the invention of the instant claim. A clear and predictable benefit of so combining would have been “that “Multi-FPGA acceleration systems achieve 3.78 times faster speed and 3.99 times greater energy efficiency compared to using four of the latest GPUs for the latest GPT language models, while maintaining acceptable accuracy for transformer-based language services.” (Kim, para. 40). Accordingly, the instant claim is unpatentable over the combination of Kerr and Kim.
Regarding claim 12, the combination of Kerr and Kim renders obvious “The non-transitory computer readable medium of claim 11, wherein the first one or more types of hardware platforms are capable of executing different types of Al models, (see, e.g., Kerr, para. 63; “may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware”) and the second type of hardware platform is optimized for only one type of Al model, (see, e.g., Kim, para. 40) wherein the first one or more types of hardware platforms comprise at least one of a central processing unit (CPU) or a graphics processing unit (GPU).” (see, e.g., Kerr, para. 63; “may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware”).
Regarding claim 15, the combination of Kerr and Kim renders obvious “The non-transitory computer readable medium of claim 11, wherein the specialized function, when compiled, results in a fused kernel in the first and second type of hardware platforms, (see, e.g., Kerr, para. 42-43, 46-47; fig. 4 sec. 408, 416; para. 53; “a procedural code generator 408 or other application interface can compile user-supplied functionality to be fused with the kernels. In at least one embodiment, a compilation manager 416 can assist with the compilation, which may include various instances of compiled code 406 to be fused.”; para. 54; “one or more application-supplied functions can be fused with a coded implementation of one or more compute-limited workloads”) wherein the specialized function comprises a plurality of lower-level functions defined by a machine learning (ML) or Al framework that are executed sequentially by the fused kernel.” (see, e.g., Kerr, para. 47, para. 54; “one or more application-supplied functions can be fused with a coded implementation of one or more compute-limited workloads . . . such fusion can provide for a performance and energy improvement with respect to separate execution . . . an architecture can take advantage of specialized compiler behavior that would not be feasible to disclose to compile an entire application . . . such architecture can enable a hardware vendor to combine sensitive IP, or proprietary functionality, with user-supplied functionality without disclosing the proprietary functionality . . . such fusion can also reduce overall code size for the functionality.”).
Regarding claim 16, the combination of Kerr and Kim renders obvious “The non-transitory computer readable medium of claim 15, wherein the IR comprises values of arguments that configure the second type of hardware platform to perform the plurality of lower-level functions defined in the specialized function.” (see, e.g., Kerr, fig. 4 & associated text; para. 53-54; “an architecture can take advantage of specialized compiler behavior that would not be feasible to disclose to compile an entire application . . . such architecture can enable a hardware vendor to combine sensitive IP, or proprietary functionality, with user-supplied functionality without disclosing the proprietary functionality.”; fig. 5 sec. 508-510; “an in-lining pass is performed 508 in order to insert compiled function(s) at one or more call locations corresponding to hooks in the partially compiled kernel. In at least one embodiment, one or more optimizations are performed.”).
Regarding claim 17, Kerr discloses “A system, comprising: one or more processors; and memory storing a compiler (see, e.g., Kerr, fig. 4 sec. 410) which, when executed by the one or more processors, performs an operation comprising:
receiving artificial intelligence (Al) model code containing a specialized function for a first one or more types of hardware platforms; (see, e.g., Kerr, fig. 4 & associated text; para. 53; “a programmer has written an implementation of a basic convolution with hooks in place, as represented by static kernels 402 to be compiled by a language-appropriate compiler 404.”; fig. 5 sec. 502; “Receive . . . one or more function objects”)
translating the specialized function into an intermediate representation (IR); (see, e.g., Kerr, fig. 4 & associated text; para. 53; fig. 5 sec. 505-506; “each function object is compiled 504 to obtain an intermediate representation. In at least one embodiment, an intermediate, or partially-compiled, representation of a compute-limited operation, such as a convolution kernel, is obtained 506.”) and
converting the IR into executable code for a second type of hardware platform, (see, e.g., Kerr, fig. 4 & associated text; para. 53-54; “an architecture can take advantage of specialized compiler behavior that would not be feasible to disclose to compile an entire application . . . such architecture can enable a hardware vendor to combine sensitive IP, or proprietary functionality, with user-supplied functionality without disclosing the proprietary functionality.”; fig. 5 sec. 508-510; “an in-lining pass is performed 508 in order to insert compiled function(s) at one or more call locations corresponding to hooks in the partially compiled kernel. In at least one embodiment, one or more optimizations are performed.”)
wherein the memory further stores a transformer model defined in the AI model code that is trained using only the first one or more types of hardware platforms (see, e.g., Kerr, para. 63; “an application-specific integrated circuit (“ASIC”), such as Tensorflow®8 Processing Unit from Google . . . or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp.”)9 and the trained transformer model and the executable code are used to perform inference only on the second type of hardware platform.” (see, e.g., Kerr, para. 63; “an application-specific integrated circuit (“ASIC”), such as . . . an inference processing unit (IPU) from Graphcore™).10
Kerr arguably does not disclose the further limitation “and wherein the second type of hardware platform comprises a model-specific chipset optimized to execute only transformer models.” More specifically, Kerr does disclose optimized chipsets (see, e.g., Kerr, para. 63; “an application-specific integrated circuit (“ASIC”), such as Tensorflow® Processing Unit from Google11 . . . or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp.”)12 but arguably does not disclose chipsets optimized to execute “only transformer models” as claimed. However, Kim discloses a chipset specifically optimized to execute only transformer models. For example, at para. 40, Kim discloses that “[t]he present disclosure provides a low-cost multi-FPGA acceleration system (hereinafter referred to as the 'multi FPGA acceleration system') that executes end-to-end transformer model inference with high throughput and low latency in both the summarization and generation stages. Multi-FPGA acceleration systems can use model parallelism with lightweight routers to distribute the same workload across devices through fast P2P (peer-to-peer) communication.”
Ker and Kim are directed toward machine learning and therefore are analogous art. On or before the effective filing date of the instant application, one of ordinary skill in the art would have deemed it obvious to try to combine the specialized compilation method of Kerr with the model-specific hardware acceleration of Kim, thereby obtaining the invention of the instant claim. A clear and predictable benefit of so combining would have been “that “Multi-FPGA acceleration systems achieve 3.78 times faster speed and 3.99 times greater energy efficiency compared to using four of the latest GPUs for the latest GPT language models, while maintaining acceptable accuracy for transformer-based language services.” (Kim, para. 40). Accordingly, the instant claim is unpatentable over the combination of Kerr and Kim.
Regarding claim 18, the combination of Kerr and Kim renders obvious “The system of claim 17, wherein the first one or more types of hardware platforms are capable of executing different types of Al models, (see, e.g., Kerr, para. 63; “may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware”) and the second type of hardware platform is optimized for only one type of Al model, (see, e.g., Kim, para. 40) wherein the first one or more types of hardware platforms comprise at least one of a central processing unit (CPU) or a graphics processing unit (GPU).” (see, e.g., Kerr, para. 63; “may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware”).
Regarding claim 21, the combination of Kerr and Kim renders obvious “The method of claim 9, wherein the values of arguments in the IR indicate whether an activation function, a Rotary Positional Embedding (RoPE), or a Gated Linear Unit (GLU) variant is to be applied following a matrix multiplication operation on the second type of hardware platform.” (see, e.g., Kim, fig. 4 & associated text; para. 88, “the first special function unit (414) can perform operations after the matrix vector product required by the matrix instruction. For example, the first special function unit (414) may be configured to handle activation operations such as GELU (Gaussian Error Linear Unit).”).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Kerr, Kim, and “DLVM: A Modern Compiler Infrastructure for Deep Learning Systems,” hereinafter “Wei.”
Regarding claim 22, the combination of Kerr and Kim renders obvious “The method of claim 9,” but does not appear to disclose the further limitations “wherein translating the specialized function into the IR comprises: generating a graph representing functions in the AI model code and data flow between the functions; identifying a post-processing argument for the specialized function based on one or more operations that occur after the specialized function in the graph; and updating the IR based on the identified post-processing argument.” However, Wei discloses “Deep Learning Virtual Machine (DLVM) is a compiler infrastructure designed for modern deep learning systems.” (pg. 3, sec. 3). Wei further discloses that specialized AI functions are represented in graphs (at pg. 4, sec. 3.1.1) and “The front-end can choose to differentiate a function with respect to selected arguments, to keep some of the outputs of the original function, to apply differentiation to a specific output when there are multiple return values, or to enable the function to accept back propagated gradients (seeds) through function composition, all by gradient declarations.” (pg. 6, sec. 3.1.3).
Kerr, Kim, and Wei are directed toward machine learning and therefore are analogous art. On or before the effective filing date of the instant application, one of ordinary skill in the art would have deemed it obvious to try to combine Kerr and Kim with Wei, thereby obtaining the invention of the instant claim. A clear and predictable benefit of so combining would have appeared as the ability to optimize machine learning performance. Accordingly, the instant claim is unpatentable over the combination of Kerr, Kim, and Wei.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Kerr, Kim, USPAT 11,803,736, hereinafter “Meyer.”
Regarding claim 23, the combination of Kerr and Kim renders obvious “The method of claim 1 wherein the model-specific chipset comprises a self-attention circuit, the self-attention circuit configured to perform attention operations using data computed from previous tokens.” (see, e.g., Kim, para. 51-53). The combination does not disclose the underlined portion of the limitation “wherein the model-specific chipset comprises a systolic array and a self-attention circuit.” However, Meyer discloses an integrated circuit comprising a systolic array (Meyer, 2:17-27). Kerr, Kim, and Meyer are directed toward machine learning and therefore are analogous art. On or before the effective filing date of the instant application, one of ordinary skill in the art would have deemed it obvious to try to combine Kerr and Kim with Meyer, thereby obtaining the invention of the instant claim. A clear and predictable benefit of so combining would have been that “a systolic array can provide much faster performance than off-the-shelf processors” (Meyer 2:35-36). Accordingly, the instant claim is unpatentable over the combination of Kerr, Kim, and Meyer.
Response to Arguments
Applicant’s amendments necessitated new grounds of rejection, set forth above. Applicant’s remarks in traversal of the previous anticipation rejections therefore are moot in view of the foregoing new obviousness rejections. Mootness notwithstanding, Applicant’s remarks in traversal again address the Kerr reference, and those remarks repeat certain assertions regarding the Kerr reference, assertions which were addressed in the Advisory Action mailed 7/28/2026. Examiner maintains the interpretations of the Kerr reference set forth in that Advisory Action and does not acquiesce to Applicant’s assertions regarding the Kerr reference for at least the reasons set forth in the Advisory Action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN D COYER whose telephone number is 571-270-5306. The examiner can normally be reached Monday-Friday 12pm-10pm Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wei Mui, can be reached at 571-272-3708. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Ryan D. Coyer/Primary Examiner, Art Unit 2191
1 https://en.wikipedia.org/wiki/Tensor_Processing_Unit
2 https://simplecore.intel.com/ai/wp-content/uploads/sites/69/16433-1_NNP-announce_NNP-T_brief_v43.pdf, Nov. 2019; (“The Intel® Nervana™ Neural Network Processor for Training (Intel® Nervana™ NNP-T) enables advanced AI systems for large-scale deep learning training.”).
3 https://en.wikipedia.org/wiki/Tensor_Processing_Unit
4 See footnote 2; (“The Intel® Nervana™ Neural Network Processor for Training (Intel® Nervana™ NNP-T) enables advanced AI systems for large-scale deep learning training.”).
5 https://www.graphcore.ai/products/ipu; https://en.wikipedia.org/wiki/Graphcore
6 https://en.wikipedia.org/wiki/Tensor_Processing_Unit
7 https://simplecore.intel.com/ai/wp-content/uploads/sites/69/16433-1_NNP-announce_NNP-T_brief_v43.pdf, Nov. 2019; (“The Intel® Nervana™ Neural Network Processor for Training (Intel® Nervana™ NNP-T) enables advanced AI systems for large-scale deep learning training.”).
8 https://en.wikipedia.org/wiki/Tensor_Processing_Unit
9 See footnote 2; (“The Intel® Nervana™ Neural Network Processor for Training (Intel® Nervana™ NNP-T) enables advanced AI systems for large-scale deep learning training.”).
10 https://www.graphcore.ai/products/ipu; https://en.wikipedia.org/wiki/Graphcore
11 https://en.wikipedia.org/wiki/Tensor_Processing_Unit
12 https://simplecore.intel.com/ai/wp-content/uploads/sites/69/16433-1_NNP-announce_NNP-T_brief_v43.pdf, Nov. 2019; (“The Intel® Nervana™ Neural Network Processor for Training (Intel® Nervana™ NNP-T) enables advanced AI systems for large-scale deep learning training.”).
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