DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 8 and 10-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu et al. (2021/0057309).
Regarding claims 1, 16 and 20, Hu (Fig. 3D) discloses an integrated circuit (IC) device, comprising: a first active semiconductor layer that includes first active semiconductor device regions 112 ([0013]); a first back end of line (BEOL) 120 positioned on the first active semiconductor layer 112 ([0014]); a first conductive structure 122 is integrated into the first BEOL 120 and connects to at least one of the first active semiconductor components 112 ([0015-0016]); a second active semiconductor layer that includes second active semiconductor components 212 ([0027]); a second BEOL 220 positioned on the second active semiconductor layer ([0032]), wherein a second conductive structure 122 is integrated into the second BEOL 220 and connects to at least one of the second active semiconductor components 212, wherein the second conductive structure 122 is electrically connected to the first conductive structure 122;a first redistribution layer 252a positioned over the second active semiconductor layer 212 ([0041]), the first redistribution layer 252a is electrically connected to the second conductive structure 122 (Fig. 3D); and a passivation layer 254a positioned on the first redistribution layer 252a ([0041]); a second redistribution layer 252b positioned over the passivation layer 254a ([0041]), wherein the second redistribution layer 252b is electrically connected to the first redistribution layer 252a (see Fig. 3D).
Regarding claims 2 and 17, Hu (Fig. 3D) discloses further comprising a hybrid bonding layer with a third conductive structure (230, BE) integrated into the hybrid bonding layer ([0036-0038]), wherein: the first BEOL 120 is positioned under the hybrid bonding layer; the second BEOL 220 is positioned on the hybrid bonding layer; the third conductive structure (230, BE) electrically connects the first conductive structure to the second conductive structure 122.
Regarding claim 8, Hu (Fig. 3D) discloses further comprising: a solder bump 260 positioned on the second redistribution layer 252b ([0043]).
Regarding claims 10-11, Hu (Fig. 3D) discloses further comprising one or more first/second gate electrodes positioned over the first/second active semiconductor device regions 112/212 such that the one or more first/second gate electrodes and the first/second active semiconductor device regions form one or more first/second field effect transistors (FETs) ([0013 and 0023]).
Regarding claim 12, Hu (Fig. 3D) discloses wherein the one or more first FETS 112 and the one or more second FETs 212 are connected by the first conductive structure 122 and the second conductive structure 222 to provide a stack of FETs coupled in series (Figs. 1C and 2C, [0015 and 0027]).
Regarding claim 13, Hu (Fig. 3D) discloses further comprising a conductive via 230 that connects the first redistribution layer 252a to the second conductive structure 220.
Regarding claims 14 and 18, Hu (Fig. 3D) discloses wherein the first redistribution layer 252a (AP1/AP2/AP3) comprises aluminum ([0017]).
Regarding claims 15 and 19, Hu (Fig. 3D) discloses wherein the second redistribution layer 252b (AP1/AP2/AP3) comprises copper ([0017]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (2021/0057309) in view of Liu et al. (2024/0234401).
Regarding claim 9, Hu all the claimed limitations of the invention except for the solder bump which is at least partially aligned over the first active semiconductor layer and the second active semiconductor layer.
However, Liu (Fig. 10) discloses the solder bump 346 is at least partially aligned over the first active semiconductor layer 312 and the second active semiconductor layer 318 ([0050]) in order to provide the devices designed for an intended purpose. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device of Hu as taught by Liu by forming the solder bump which is at least partially aligned over the first active semiconductor layer and the second active semiconductor layer in order to provide the devices designed for an intended purpose (Figs. 10, [0050]).
Allowable Subject Matter
Claims 3-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record fails to disclose all the limitations recited in the claim 3. Specifically, the prior art of record fails to disclose further comprising a first buried oxide layer, a trap rich layer, and a handle layer, the first active semiconductor layer is positioned on the first buried oxide layer, the trap rich layer is positioned on the first buried box layer, and the first handle layer is positioned on the first trap layer (claim 3).
The dependent claims being further limiting and definite are also allowable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THERESA T DOAN whose telephone number is (571)272-1704. The examiner can normally be reached on Monday, Tuesday, Wednesday and Thursday from 7:00AM - 3:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THERESA T DOAN/ Primary Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814