DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election of Species III (claims 1-20) in the reply filed on 05/22/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-10, and 12-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liu et al. (U.S 2024/0071887 A1).
As to claim 1, Liu et al. disclose in Fig. 20 a semiconductor package comprising: a semiconductor chip (“die” 200)/(comprising 200a-200e) (see annotated Fig. 20 below, para. [0019]); a connection structure (“redistribution layer structure” 110) below the semiconductor chip (“die” 200) and electrically connected to the semiconductor chip (“die” 200) (see annotated Fig. 20 below, para. [0023]-[0024]); and an external connection terminal (“conductive elements or bumps” B2) below the connection structure (“redistribution layer structure” 110) (see annotated Fig. 20 below, para. [0031]),
wherein the connection structure (“redistribution layer structure” 110) comprises: a first via array (see “first via array” V3b as annotated in Fig. 20 below) comprising a plurality of first vias (see a plurality of vias V3b, annotated Fig. 20 below) in a first direction (horizontal direction) (Fig. 20, para. [0029], [0035]); a second via array (see “second via array” V1a/V1b as annotated in Fig. 20 below) above the first via array (see “first via array” V3b as annotated in Fig. 20 below) and comprising a plurality of second vias (plurality of vias V1a/V1b, Fig. 20) in the first direction (horizontal direction) (Fig. 20, para. [0029], [0035]); and a first pad (see “first pad” L2b as annotated in Fig. 20 below) between the first via array (see “first via array” V3b as annotated in Fig. 20 below) and the second via array (see “second via array” V1a/V1b as annotated in Fig. 20 below) and on upper surfaces (top surface) of the plurality of the first vias (see a plurality of vias V3b, annotated Fig. 20) (Fig. 20, para. [0025], [0035]), wherein the second via array (see “second via array” V1a/V1b as annotated in Fig. 20 below) is offset from the first via array (see “first via array” V3b as annotated in Fig. 20 below) in the first direction (horizontal direction) and does not overlap the first via array (see “first via array” V3b as annotated in Fig. 20 below) in a vertical direction (see annotated Fig. 20 below).
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As to claim 2, as applied to claim 1 above, Liu et al. disclose in Fig. 20 all claimed limitations including the limitation: wherein the first via array (see “first via array” V3b as annotated in Fig. 20 above) is integrally formed with the first pad (see “first pad” L2b as annotated in Fig. 20 above).
As to claim 3, as applied to claim 1 above, Liu et al. disclose in Fig. 20 all claimed limitations including the limitation: wherein a distance between first vias (see a plurality of vias V3b, annotated Fig. 20 above) adjacent to each other among the plurality of first vias (a plurality of vias V3b) is greater than a distance by which the second via array (see “second via array” V3b as annotated in Fig. 20 above) is offset from the first via array (see “first via array” V3b as annotated in Fig. 20 above) in the first direction (horizontal direction) (see annotated Fig. 20 above).
As to claim 5, as applied to claim 1 above, Liu et al. disclose in Fig. 20 all claimed limitations including the limitation: wherein the connection structure (“redistribution layer structure” 110) further comprises a second pad (see “second pad” as annotated in Fig. 20 below) between the first via array (see “first via array” V3b as annotated in Fig. 20 below) and the second via array (see “second via array” V1a/V1b as annotated in Fig. 20 below) and on lower surfaces (bottom surface) of the plurality of the second vias (vias of “second via array”), wherein the first pad (see “first pad” L2b as annotated in Fig. 20 below) is on the upper surfaces (top surface) of the plurality of first vias (vias V3b of “first via array”), and wherein the second pad (see “second pad” as annotated in Fig. 20 below) is on the lower surfaces (bottom surface) of the plurality of second vias (vias of “second via array”) (see annotated Fig. 20 below).
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As to claim 6, as applied to claim 1 above, Liu et al. disclose in Fig. 20 all claimed limitations including the semiconductor package further comprising a lower pad (as indicated at L3b, in annotated Fig. 20) below the first via array (see “first via array” V3b as annotated in Fig. 20 above) and electrically connected to the external connection terminal (“conductive elements or bumps” B2), wherein the lower pad (as indicated at L3b, in annotated Fig. 20 above) is in contact with the first via array (see “first via array” V3b as annotated in Fig. 20 above) (see annotated Fig. 20 above, para. [0027], [0031]).
As to claim 7, as applied to claim 1 above, Liu et al. disclose in Fig. 20 all claimed limitations including the limitation: wherein the connection structure (“redistribution layer structure” 110) further comprises: a third via array (see “third via array” as annotated in Fig. 20 below) above the second via array (see “second via array” V1a/V1b as annotated in Fig. 20 below) and comprising a plurality of third vias in the first direction (horizontal direction) (see annotated Fig. 20 below); and a third pad (see “third pad” as annotated in Fig. 20 below) between the second via array (see “second via array” V1a/V1b as annotated in Fig. 20 below) and the third via array (see “third via array” as annotated in Fig. 20 below) and on upper surfaces of the plurality of the second vias (V1a/V1b), wherein the third via array (see “third via array” as annotated in Fig. 20 below) is offset from the second via array (see “second via array” V1a/V1b as annotated in Fig. 20 below) in the first direction (horizontal direction) and does not overlap the second via array (see “second via array” V1a/V1b as annotated in Fig. 20 below) in the vertical direction (see annotated Fig. 20 below).
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As to claim 8, as applied to claims 1 and 7 above, Liu et al. disclose in Fig. 20 all claimed limitations including the semiconductor package further comprising: an upper pad (200b) on the third via array (see “third via array” as annotated in Fig. 20 above) and electrically connected to the semiconductor chip (“die” 200)/(comprising 200a-200e), wherein the upper pad (200b) is on upper surfaces of the plurality of third vias (vias of “third via array”) (see annotated Fig. 20 above, para. [0019], [0045]).
As to claim 9, as applied to claims 1 and 7 above, Liu et al. disclose in Fig. 20 all claimed limitations including the limitation: wherein a distance between second vias (plurality of vias V1a/V1b, annotated Fig. 20) adjacent to each other among the plurality of second vias (plurality of vias V1a/V1b, annotated Fig. 20) is greater than a distance by which the third via array (see “third via array” as annotated in Fig. 20 above) is offset from the second via array (see “second via array” V1a/V1b as annotated in Fig. 20 above) in the first direction (horizontal direction) (see annotated Fig. 20 above).
As to claim 10, as applied to claims 1 and 7 above, Liu et al. disclose in Fig. 20 all claimed limitations including the limitation: wherein the third via array (see “third via array” as annotated in Fig. 20 above) overlaps at least a portion of the first via array (see “first via array” V3b as annotated in Fig. 20 above) in the vertical direction (see annotated Fig. 20 above).
As to claim 12, Liu et al. disclose in Fig. 20 a semiconductor package comprising: a semiconductor chip (“die” 200)/(comprising 200a-200e) (see annotated Fig. 20 below, para. [0019]); and a connection structure (“redistribution layer structure” 110) below the semiconductor chip (“die” 200)/(comprising 200a-200e) and electrically connected to the semiconductor chip (“die” 200)/(comprising 200a-200e) (see annotated Fig. 20 below, para. [0023]-[0024]),
wherein the connection structure (“redistribution layer structure” 110) comprises: a plurality of first vias (see “plurality of first vias” V3b as annotated in Fig. 20 below) in a first direction (horizontal direction) (see annotated Fig. 20, para. [0023]-[0024], [0027], [0043]); a plurality of second vias (see “plurality of second vias” V1a/V1b as annotated in Fig. 20 below) in the first direction (horizontal direction) above the plurality of first vias (see annotated Fig. 20 below, para. [0035]-[0036]); a first pad (see “first pad” L2b as annotated in Fig. 20 below) between the plurality of first vias (see “plurality of first vias” V3b as annotated in Fig. 20 below) and the plurality of second vias (see “plurality of second vias” V1a/V1b as annotated in Fig. 20 below) and on upper surfaces of the plurality of first vias (see “plurality of first vias” V3b as annotated in Fig. 20 below) (see annotated Fig. 20 below); a second pad (see “second pad” as annotated in Fig. 20 below) in the first direction (horizontal direction) above the plurality of first vias (see “plurality of first vias” V3b as annotated in Fig. 20 below) between the plurality of first vias (see “plurality of first vias” V3b as annotated in Fig. 20 below) and the plurality of second vias (see “plurality of second vias” V1a/V1b as annotated in Fig. 20 below) and on lower surfaces of the plurality of second vias (see “plurality of second vias” V1a/V1b as annotated in Fig. 20 below) (see annotated Fig. 20 below, para. [0026], [0039]); and a redistribution pattern (see “redistribution pattern” as annotated in Fig. 20 below) between the first pad (see “first pad” L2b as annotated in Fig. 20 below) and the second pad (see “second pad” as annotated in Fig. 20 below) in the first direction (horizontal direction) (see annotated Fig. 20 below, para. [0026], [0039]), wherein the plurality of second vias (see “plurality of second vias” V1a/V1b as annotated in Fig. 20 below) are offset from the plurality of first vias (see “plurality of first vias” V3b as annotated in Fig. 20 below) in the first direction (horizontal direction) and does not overlap the plurality of first vias (see “plurality of first vias” V3b as annotated in Fig. 20 below) in a vertical direction (see annotated Fig. 20 below).
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As to claim 13, as applied to claim 12 above, Liu et al. disclose in Fig. 20 all claimed limitations including the limitation: wherein the redistribution pattern (see “redistribution pattern” as annotated in Fig. 20 above) is integrally formed with the first pad (as annotated in Fig. 20 above) and the second pad (as annotated in Fig. 20 above).
As to claim 14, as applied to claim 12 above, Liu et al. disclose in Fig. 20 all claimed limitations including the limitation: wherein a material of the redistribution pattern (see “redistribution pattern” as annotated in Fig. 20 above) is same as a material of the first pad (see “first pad” L2b as annotated in Fig. 20 above) and a material of the second pad (see “second pad” as annotated in Fig. 20 above) (see annotated Fig. 20 above).
As to claim 15, as applied to claim 12 above, Liu et al. disclose in Fig. 20 all claimed limitations including the limitation: wherein a width of the redistribution pattern (see “redistribution pattern” as annotated in Fig. 20 above) in the first direction (horizontal direction) is greater than a width of the redistribution pattern (see “redistribution pattern” as annotated in Fig. 20 above) in a second direction (vertical direction) perpendicular to the first direction (horizontal direction) (see annotated Fig. 20 above).
As to claim 16, as applied to claim 12 above, Liu et al. disclose in Fig. 20 all claimed limitations including the limitation: wherein the first pad (see “first pad” L2b as annotated in Fig. 20 above) is on the upper surfaces (top surface) of the plurality of first vias (see “plurality of first vias” V3b as annotated in Fig. 20 above), and wherein the second pad (see “second pad” as annotated in Fig. 20 above) is on the lower surfaces of the plurality of second vias (see “plurality of second vias” V1a/V1b as annotated in Fig. 20 above) (see annotated Fig. 20 above).
As to claim 17, as applied to claim 12 above, Liu et al. disclose in Fig. 20 all claimed limitations including the limitation: wherein a width of the redistribution pattern (see “redistribution pattern” as annotated in Fig. 20 above) in the first direction (horizontal direction) is less than a distance between first vias (see “plurality of first vias” V3b as annotated in Fig. 20 above) adjacent to each other among the plurality of first vias (see “plurality of first vias” V3b as annotated in Fig. 20 above) and is less than a width of the first pad (see “first pad” L2b as annotated in Fig. 20 above) in the first direction (horizontal direction) (see annotated Fig. 20 above).
As to claim 18, Liu et al. disclose in Fig. 20 a semiconductor package comprising: a semiconductor chip (“die” 200)/(comprising 200a-200e) (see annotated Fig. 20 below, para. [0019]); a connection structure (“redistribution layer structure” 110) below the semiconductor chip (“die” 200)/(comprising 200a-200e) and electrically connected to the semiconductor chip (“die” 200)/(comprising 200a-200e) (see annotated Fig. 20 below, para. [0023]-[0024]); a solder ball (“conductive elements or bumps” B2) below the connection structure (“redistribution layer structure” 110) (see annotated Fig. 20 below, para. [0031]); a pad (200b) below the semiconductor chip (“die” 200)/(comprising 200a-200e) and electrically connected to the semiconductor chip (“die” 200)/(comprising 200a-200e) (see annotated Fig. 20 below, para. [0019]); a conductive post (“through dielectric vias (TIVs)” 106) adjacent to the semiconductor chip (“die” 200)/(comprising 200a-200e) (Fig. 20, para. [0015]); and an encapsulation layer (“dielectric encapsulation layer” 108) on the semiconductor chip (200) and the conductive post (106) (see annotated Fig. 20 below, para. [0022]),
wherein the connection structure (“redistribution layer structure” 110) comprises: a first via array (see “first via array” V3b as annotated in Fig. 20 below) comprising a pair of first vias (see a plurality of vias V3b, annotated Fig. 20 below) in a first direction (horizontal direction) (Fig. 20, para. [0029], [0035]); a second via array (see “second via array” V1a/V1b as annotated in Fig. 20 below) above the first via array (see “first via array” V3b as annotated in Fig. 20 below) and comprising a pair of second vias (plurality of vias V1a/V1b, Fig. 20) in the first direction (horizontal direction) (Fig. 20, para. [0029], [0035]); a first pad (see “first pad” L2b as annotated in Fig. 20 below) between the first via array (see “first via array” V3b as annotated in Fig. 20 below) and the second via array (see “second via array” V1a/V1b as annotated in Fig. 20 below), integrally formed with upper surfaces the pair of first vias (see a plurality of vias V3b, annotated Fig. 20), and extending in the first direction (horizontal direction) (Fig. 20, para. [0025], [0035]); a second pad (see “second pad” as annotated in Fig. 20 below) between the first via array (see “first via array” V3b as annotated in Fig. 20 below) and the second via array (see “second via array” V1a/V1b as annotated in Fig. 20 below) and in contact with lower surfaces of the pair of second vias (see “plurality of second vias” V1a/V1b as annotated in Fig. 20 below) (see annotated Fig. 20 below, para. [0026], [0039]); and a redistribution insulating layer (comprising layers PM2 & PM3) in which the first via array (see “first via array” V3b as annotated in Fig. 20 below), the second via array (see “second via array” V1a/V1b as annotated in Fig. 20 below), the first pad (see “first pad” L2b as annotated in Fig. 20 below), and the second pad (see “second pad” as annotated in Fig. 20 below) are buried (see annotated Fig. 20 below, para.[0026]), wherein the second via array (see “second via array” V1a/V1b as annotated in Fig. 20 below) is offset from the first via array (see “first via array” V3b as annotated in Fig. 20 below) in the first direction (horizontal direction) and does not overlap the first via array (see “first via array” V3b as annotated in Fig. 20 below) in a vertical direction (see annotated Fig. 20 below), wherein the upper surface (top surface) of the first pad (see “first pad” L2b as annotated in Fig. 20 below) and the upper surface (top surface) of the second pad (see “second pad” as annotated in Fig. 20 below) are at the same vertical level (see annotated Fig. 20 below), and wherein a distance between the pair of first vias (see a plurality of vias V3b, annotated Fig. 20 below) is greater than a distance by which the second via array (see “second via array” V1a/V1b as annotated in Fig. 20 below) is offset from the first via array (see “first via array” V3b as annotated in Fig. 20 below) in the first direction (horizontal direction) (see annotated Fig. 20 below).
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As to claim 19, as applied to claim 18 above, Liu et al. disclose in Fig. 20 all claimed limitations including the limitation: wherein the connection structure (“redistribution layer structure” 110) further comprises a redistribution pattern (see “redistribution pattern” as annotated in Fig. 20 above) between the first pad (see “first pad” L2b as annotated in Fig. 20 above) and the second pad (see “second pad” as annotated in Fig. 20 above) in the first direction (horizontal direction) (see annotated Fig. 20 above), wherein the redistribution pattern (see “redistribution pattern” as annotated in Fig. 20 above) is integrally formed with the first pad (see “first pad” L2b as annotated in Fig. 20 above) and the second pad (see “second pad” as annotated in Fig. 20 above) and a material of the redistribution pattern (see “redistribution pattern” as annotated in Fig. 20 above) is same as a material of the first pad (see “first pad” L2b as annotated in Fig. 20 above) and a material of the second pad see “second pad” as annotated in Fig. 20 above), and wherein a width of the redistribution pattern (see “redistribution pattern” as annotated in Fig. 20 above) in the first direction (horizontal direction) is greater than a width of the redistribution pattern (see “redistribution pattern” as annotated in Fig. 20 above) in a second direction (vertical direction) perpendicular to the first direction (horizontal direction) (see annotated Fig. 20 above).
As to claim 20, as applied to claim 18 above, Liu et al. disclose in Fig. 20 all claimed limitations including the limitation: wherein the connection structure (“redistribution layer structure” 110) further comprises: a third via array (see “third via array” as annotated in Fig. 20 above) above the second via array (see “second via array” V1a/V1b as annotated in Fig. 20 above) and comprising a plurality of third vias in the first direction (horizontal direction) (see annotated Fig. 20 above); and a third pad (see “third pad” as annotated in Fig. 20 above) between the second via array (see “second via array” V1a/V1b as annotated in Fig. 20 above) and the third via array (see “third via array” as annotated in Fig. 20 above) and on upper surfaces of the plurality of the second vias (V1a/V1b), wherein the third via array (see “third via array” as annotated in Fig. 20 above) is offset from the second via array (see “second via array” V1a/V1b as annotated in Fig. 20 above) in the first direction (horizontal direction) and does not overlap the second via array (see “second via array” V1a/V1b as annotated in Fig. 20 above) in the vertical direction (see annotated Fig. 20 above), wherein the third via array (see “third via array” as annotated in Fig. 20 above) is configured to provide a movement path of a power signal to operate the semiconductor chip (200) or a movement path of a signal of the semiconductor chip (200) (see annotated Fig. 20 above, para. [0028]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (U.S 2024/0071887 A1).
As to claim 11, as applied to claim 1 above, Liu et al. disclose in Fig. 20 all claimed limitations including the limitation: wherein a distance by which the second via array (see “second via array” V1a/V1b as annotated in Fig. 20 above) is offset from the first via array (see “first via array” V3b as annotated in Fig. 20 above) in the first direction (horizontal direction) (see annotated Fig. 20 above).
Liu et al. do not disclose a distance by which the second via array is offset from the first via array in the first direction is 10 micrometers to 20 millimeters. However, it would have been obvious to one of ordinary skill in the art to use the teaching of Liu et al. in the range (10 micrometers to 20 millimeters for a distance by which the second via array is offset from the first via array in the first direction) as claimed, in order to maximize electrical isolation and minimize parasitic capacitance between the first and second via arrays, thereby enhancing signal integrity across high-frequency channels, because it has been held that where the general conditions of the claims are disclosed in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955); Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. Denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); MPEP 2144.05. There is no evidence indicating a range of an offset distance is critical. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (U.S 2024/0071887 A1) in view of MAEDA et al. (U.S 2012/0024582 A1).
As to claim 4, as applied to claim 1 above, Liu et al. disclose in Fig. 20 all claimed limitations except for the limitation: wherein a diameter of each of the plurality of first vias and a diameter of each of the plurality of second vias decreases towards the external connection terminal.
MAEDA et al. disclose in Fig. 1 a semiconductor package comprising: a first via array (see “first via array” 34 as annotated in Fig. 1 below) including the plurality of first vias (34) and a second via array (see “second via array” 34 as annotated in Fig. 1 below) including the plurality of second vias (34), wherein a diameter of each of the plurality of first vias (34) and a diameter of each of the plurality of second vias (34) decreases towards the external connection terminal (“main-face-side solder bumps” 46) (see annotated Fig. 1 below, para. [0047]-[0048]).
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Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify reference of Liu by having the diameter of each of the plurality of first vias and the diameter of each of the plurality of second vias decreases towards the external connection terminal as taught by MAEDA et al., in order to reduce parasitic capacitance between adjacent vias, improve signal integrity and structural reliability of the via connections.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: YU et al. (U.S 2024/0074053 A1) disclose in Fig. 3 a semiconductor package comprising: a semiconductor chip (231); and a connection structure (201) having a first via array (included in “multi-layer via” 350) and a second via array (included in “multi-layer via” 350).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 August 6, 2026
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