CTNF 18/384,259 CTNF 77450 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-2, 7-9, 12, 14-15 and 17-18 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Liu et al. (CN 113206098 A) . Regarding claim 1, Liu discloses a chip-package structure, comprising: a first chip (602 or 402) comprising at least a peripheral circuit comprising a first transistor (611 or 411) [Fig. 2-4 and page 14, first two paragraphs, in Machine English Translation]; a second chip (604, 606 or 404) comprising at least a column decoder comprising a second transistor (631) [Fig. 4 and page 14, second paragraph, in Machine English Translation]; and a third chip (606, 30 or 302) comprising at least a control circuit comprising a third transistor (661) [Fig. 4; and page 13, paragraph starting with “In some embodiments, the 3D NAND channel structure 318….,” and page 14, second paragraph, in Machine English Translation]; wherein the first chip (602 or 402), the second chip (604, 606 or 404), and the third chip (606, 30 or 302) form a stacked structure [Figs. 4-5], and wherein a first channel length of the first transistor (611 or 411), a second channel length of the second transistor (631, 661 or 431), and a third channel length of the third transistor (661 or 318) are different [Figs. 3-5, and page 14, second paragraph, in Machine English Translation]. Regarding claim 2, Liu discloses wherein: the peripheral circuit comprises at least a word line driver and a page buffer each comprising the first transistor (611), the second chip (604) further comprises a power management circuit comprising the second transistor (631), and the third chip (606) further comprises an input/output (I/O) interface circuit comprising the third transistor (661) Figs. 4-5, and page 14, fourth paragraph, in Machine English Translation]. Regarding claim 7, Liu discloses wherein: one chip (404 or 606) of two adjacent chips in the stacked structure comprises a first dielectric layer (490) on one of its surfaces and a first conductive pattern (491) penetrating the first dielectric layer [Figs. 2-3], another chip (302 or 30) of the two adjacent chips in the stacked structure comprises a second dielectric layer (360) on one of its surfaces and a second conductive pattern (362) penetrating the second dielectric layer [Fig. 3], the first conductive pattern (491) is bonded (hybrid bonded) with the second conductive pattern (362) [Fig. 3, and page 11, last paragraph, in Machine English Translation], and the first dielectric layer (490) is bonded (hybrid bonding) with the second dielectric layer (360) [Figs. 3 and 5, and page 11, last paragraph, in Machine English Translation]. Regarding claim 8, Liu discloses wherein: one chip (604) of two adjacent chips in the stack structure comprises a first dielectric layer (ILD layer 630 embedding device/wiring) on one of its surfaces and a first conductive pattern (642) penetrating the first dielectric layer (630) [Fig. 4 and pages 8-9 and 18 in Machine English Translation], another chip (606) of the two adjacent chips in the stack structure comprises a second dielectric layer (660) on one of its surfaces and a second conductive pattern (672) penetrating the second dielectric layer (660) [Fig. 4 and pages 8-9 and 18 in Machine English Translation], and the chip-package structure further comprises a connection structure (641/655/671) through which the first conductive pattern (642) is electrically connected with the second conductive pattern (672) [Fig. 4 and page 18 in Machine English Translation]. Regarding claim 9, Liu discloses wherein the connection structure comprises any one of a solder ball, a solder bump, or a copper (Cu) pillar (655) [Fig. 4 and page 18 in Machine English Translation]. Regarding claim 12, Liu discloses a fifth chip (604) comprising a three-dimensional memory array, wherein the fifth chip (604) is stacked with the first chip (602), the second chip (606) and the third chip (30), and wherein the fifth chip (604) is disposed adjacent to the first chip (602) [Fig. 5]. Regarding claim 14, Liu discloses a method of fabricating a chip-package structure comprising: forming a first chip (602) comprising at least a peripheral circuit comprising a first transistor (611) [Fig. 4 and page 14, first two paragraphs, in Machine English Translation]; forming a second chip (604) comprising at least a column decoder comprising a second transistor (631) [Fig. 4 and page 14, second paragraph, in Machine English Translation]; forming a third chip (606) comprising at least a control circuit comprising a third transistor (661) [Fig. 4 and page 14, second paragraph, in Machine English Translation]; and stacking the first chip, the second chip, and the third chip to form a stack structure (60/30) [Fig. 5], wherein a first channel length of the first transistor, a second channel length of the second transistor, and a third channel length of the third transistor are different [Fig. 4, and page 14, second paragraph, in Machine English Translation]. Regarding claim 15, Liu discloses wherein: the first chip, the second chip, and the third chip each comprise a plurality of circuits (410/430 or 610/630/660), and the method further comprises: forming the plurality of circuits on a same chip using the same process, or forming the plurality of circuits on different chips with different process parameters [page 16, last two paragraphs, and page 17, last two paragraphs, in Machine English Translation]. Regarding claim 17, Liu discloses wherein surfaces of two adjacent chips (30/606) in the stack structure are connected using a bonding process (“hybrid bonding”, 360/690) [Figs. 3 and 5, and page 11, last paragraph, in Machine English Translation]. Regarding claim 18, Liu discloses wherein two adjacent chips of the stack structure (30/690) are connected using a connection structure (491/691 and 362) [Figs. 2-5] . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 5-6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (CN 113206098 A) in view of Baik (US 2020/0013767) . Regarding claims 5-6, Liu does not disclose a volatile memory. In regards to claims 5 and 16 , Baik teaches a fourth chip (500) comprising a volatile memory (DRAM), wherein the fourth chip (500) is stacked with the first chip (210), the second chip (210), and the third chip (210) [Fig. 4 and paragraphs 0036-0037]. In regards to claim 6, Baik teaches a fourth chip (400a) comprising a volatile memory (DRAM), wherein the first chip (210), the second chip (210), and the third chip (210) are stacked in a first direction (vertical), and wherein the fourth chip (400a) is placed adjacent to the stack structure (200) in a second direction perpendicular to the first direction (horizontal) [Fig. 2 and paragraph 0029]. Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Liu by including a volatile memory as taught by Baik because it helps to increase the capacity, functionality and performance of the semiconductive package [paragraph 0003] . 07-21-aia AIA Claim s 20 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (CN 113206098 A) in view of Takenaka et al. (US 12183401) . Regarding claim 20, Liu discloses a memory system comprising: a chip-package structure comprising: a first chip (602) comprising at least a peripheral circuit comprising a first transistor (611) [Fig. 2-4 and page 14, first two paragraphs, in Machine English Translation]; a second chip (604) comprising at least a column decoder comprising a second transistor (631) [Fig. 4 and page 14, second paragraph, in Machine English Translation]; and a third chip (606) comprising at least a control circuit comprising a third transistor (661) [Fig. 4; and page 13, paragraph starting with “In some embodiments, the 3D NAND channel structure 318….,” and page 14, second paragraph, in Machine English Translation], wherein the first chip (602), the second chip (604), and the third chip (606) form a stacked structure [Fig. 4], and wherein a first channel length of the first transistor (611), a second channel length of the second transistor (604), and a third channel length of the third transistor (606) are different [Fig. 4, and page 14, second paragraph, in Machine English Translation]; and However, Liu does not disclose a circuit board. Takenaka teaches that it is well known in the art to electrically connect a circuit board (MSB) with the chip-package structure (MD) [Figs. 1-2]. Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Liu by including a circuit board as taught by Takenaka because it helps to provide support and electrical connectivity for various components . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 3-4, 10-11, 13 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent- center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Jose R Diaz/Primary Examiner, Art Unit 2815 Application/Control Number: 18/384,259 Page 2 Art Unit: 2815 Application/Control Number: 18/384,259 Page 3 Art Unit: 2815 Application/Control Number: 18/384,259 Page 4 Art Unit: 2815 Application/Control Number: 18/384,259 Page 5 Art Unit: 2815 Application/Control Number: 18/384,259 Page 6 Art Unit: 2815 Application/Control Number: 18/384,259 Page 7 Art Unit: 2815 Application/Control Number: 18/384,259 Page 8 Art Unit: 2815 Application/Control Number: 18/384,259 Page 9 Art Unit: 2815