Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 20 is objected to because of the following informalities:
Recitation of the limitation “the PCB comprising a the PCB comprising…” in lines 3-4.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the warpage" in line 4. There is insufficient antecedent basis for this limitation in the claim. For the same reason, all dependent claims 2-12 thereof are rejected as well by virtue of their dependencies.
Claim 8 is rejected as it recites the limitation “a substantially same thickness” in lines 1-2. The limitation “substantially” renders the scope of the claim unclear because it is ambiguous, failing to provide an objective standard for determining the boundaries of the claimed subject matter.
Claim 9 recites the limitation "the second PCB" in line 6. There is insufficient antecedent basis for this limitation in the claim. Furthermore, claim 9 is rejected as it recites the limitation “the PCB” in line 8 renders the scope of the claim unclear because it is ambiguous to whether it refers to
the first PCB (recited in claim 9, line 4); or
the second PCB (recited in claim 9, line 6)
As such, it is not clear how the claimed limitation is intended to be interpreted. For the purpose of this office action, the claim has been examined, as best understood, to encompass any of the two potential reasonable interpretations noted above. For the same reason, dependent claim 10 thereof are rejected as well by virtue of their dependencies.
Claim 10 is rejected as it recites the limitation “a same set of technical specifications” in line 2. The limitation renders the scope of the claim unclear because it is ambiguous, failing to provide an objective standard for determining the boundaries of the claimed subject matter.
Claim 20 is rejected as it recites the limitation "chip package" in line 3 which renders the claim ambiguous to whether it refers to
the first chip package (recited in claim 17, line 2); or
the second chip package (recited in claim 20, line 2)
As such, it is not clear how the claimed limitation is intended to be interpreted. For the purpose of this office action, the claim has been examined, as best understood, to encompass any of the two potential reasonable interpretations noted above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 13 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chng et al (U.S. Patent Application Publication 20220375053 A1) hereinafter Chng, and further in view of Kuo et al (U.S. Patent 9536865 B1) hereinafter Kuo.
Regarding claim 13, Chng discloses a method (Title: Apparatus, System and Method for Determining a Match Condition for a Printed Circuit Board to a Stencil) of attaching a chip package (electronic components, ¶92) to a printed circuit board ("PCB") (assembled PCB 30, ¶50), comprising:
measuring a warpage parameter (upper and lower limits of tolerance, ¶60, “The condition determination module 121 is configured to allow for upper and lower limits of tolerance during the comparison between the datasets to account for the thermal expansion of the FR-4 substrate of the bare PCB 10”);
selecting a first stencil (stencil data file 21, ¶60) from a plurality of stencils, the first stencil configured to compensate for warpage (thermal expansion, ¶60) corresponding to the measured warpage parameter, the first stencil including a plurality of first apertures (aperture layout 23, ¶60) (¶60, “Having both the PCB surface data file 11 and the stencil data file 21, the condition determination module 121 shall conduct a matching process by comparing the datasets available in both data files [i.e. the dimension data and coordinate data] to determine if the aperture layout 23 can align to the pad layout 13”);
positioning the first stencil above the PCB (¶61, “A match-successful condition occurs when all sets of data available in both data files, after comparison, fall within the configured limits of tolerance. This will indicate that the aperture layout 23 of the stencil specification image 22 is fairly aligned to the pad layout 13 of the surface profile image 12”; FIG. 4 depicts stencil properly lined up while FIG. 5 depicts stencil misalignment);
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applying solder paste (solder paste, ¶92) on the PCB via the plurality of first apertures of the first stencil (¶88, “The apparatus may also be a member of a system for performing solder printing and forming an assembled PCB 30”);
moving the PCB away from the first stencil (¶92, “After that, the stencil printed bare PCB 10 is passed into a pick and place machine 804”; it would be understood to a POSITA that the PCB 10 is passed into the machine 804 without the stencil as it would interfere with electronic component mounting); and
positioning the chip package (electronic components, ¶92) on the solder paste on the PCB, thereby attaching the chip package to the PCB (¶92, “After that, the stencil printed bare PCB 10 is passed into a pick and place machine 804 for electronic components to be mounted thereon. The electronic components may be, but not limited, to surface-mount components and through-hole components. Due to the tacky nature of the solder paste, the electronic components would be held in place on the pads”).
However, Chng fails to disclose measuring a warpage parameter of the chip package, namely the electronic components.
Kuo discloses (Title: Interconnection Joints Having Variable Volumes in Package Structures and Methods of Formation Thereof) a method step of measuring a warpage parameter of the chip package, namely the electronic components (col. 4, ll. 62-64, “The warpage characteristics of each package component are then analyzed prior to bonding”).
Though Chng fails to directly disclose such a method, Chng does however teach a similar method, measuring instead the warpage parameter of the substrate. Both the chip package and substrate of the PCB are mating components whose relative locations affects alignment, bonding quality, solder joint reliability, and overall assembly. Similarly, Kuo discloses of a method for analyzing the warpage characteristic of a package component instead to then be mounted upon a printed circuit board via deposition of a stenciled/solder material. Thus, a person of ordinary skill in the art before the effective filing date would have recognized that the same measurement technique used to characterize the warpage of one element is equally applicable to another element due to both elements being subject to warpage disadvantages. In this case, measuring the warpage of Chng’s substrate versus measuring the warpage of Kuo’s package component.
Furthermore, making such a modification would have yielded no more than predictable use of routine optimization, providing operators the flexibility of measuring a more physically/visibly available element for measurement to be mounted upon. Also, a POSITA would have known that measuring the warpage of components of the electronic device would provide obvious advantages, such as decreased production time and cost due to avoiding costly rework or replacement of packages which are unacceptably warped.
Regarding claim 17, Chng discloses (Title: Apparatus, System and Method for Determining a Match Condition for a Printed Circuit Board to a Stencil) an electronic device comprising:
a first chip package (electronic components, ¶92); and
a printed circuit board (PCB) (assembled PCB 30, ¶50) electrically and mechanically connected to the first chip package (¶92, “Then the PCB with the components enters the solder reflow machine 805. The solder reflow machine 805 applies heat gradually for the solder paste to melt so that a secure solder joint can be formed between the contacts of the electronic components and the pads of the bare PCB 10”), the PCB comprising a first stenciled material (solder paste, ¶92) disposed.
However, Chng fails to disclose the warpage characteristic is based on the warpage of the first chip package. Chng also fails to disclose that the first stenciled material is deposited such that it is patterned based on the first predetermined warpage characteristic of the first chip package.
Kuo discloses (Title: Interconnection Joints Having Variable Volumes in Package Structures and Methods of Formation Thereof) a method step of measuring a warpage parameter of the chip package, namely the electronic components (col. 4, ll. 62-64, “The warpage characteristics of each package component are then analyzed prior to bonding”).
(Regarding to why Chng, in view of Kuo, teaches such a method, namely measuring instead the warpage parameter of the substrate to which the electronic components are mounted upon, refer to the rejection of claim 13, supra, as it is applicable to the rejection of claim 17 in the manner of measuring a more accessible element for measuring warpage as well as how elements are directly affected to one another through manufacturing process disadvantages concerning warpage).
Claims 1-9 and 11-12, 14-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chng, in view of Kuo, and further in view of Zu (U.S. Patent Application Publication 20100143656 A1).
Regarding claim 1, Chng discloses a method (Title: Apparatus, System and Method for Determining a Match Condition for a Printed Circuit Board to a Stencil) of attaching a chip package (electronic components, ¶92) to a printed circuit board ("PCB") (assembled PCB 30, ¶50), comprising:
measuring a warpage parameter (upper and lower limits of tolerance, ¶60, “The condition determination module 121 is configured to allow for upper and lower limits of tolerance during the comparison between the datasets to account for the thermal expansion of the FR-4 substrate of the bare PCB 10”);
selecting a stencil (stencil data file 21, ¶60) configured to compensate for the warpage (thermal expansion, ¶60) corresponding to the measured warpage parameter, the stencil including a plurality of apertures (aperture layout 23, ¶60) (¶60, “Having both the PCB surface data file 11 and the stencil data file 21, the condition determination module 121 shall conduct a matching process by comparing the datasets available in both data files [i.e. the dimension data and coordinate data] to determine if the aperture layout 23 can align to the pad layout 13”);
positioning the stencil above the PCB (¶61, “A match-successful condition occurs when all sets of data available in both data files, after comparison, fall within the configured limits of tolerance. This will indicate that the aperture layout 23 of the stencil specification image 22 is fairly aligned to the pad layout 13 of the surface profile image 12”; FIG. 4 depicts stencil properly lined up while FIG. 5 depicts stencil misalignment);
applying solder paste (solder paste, ¶92) on the PCB via the plurality of apertures of the stencil (¶88, “The apparatus may also be a member of a system for performing solder printing and forming an assembled PCB 30”);
moving the PCB away from the stencil (¶92, “After that, the stencil printed bare PCB 10 is passed into a pick and place machine 804”; it would be understood to a POSITA that the PCB 10 is passed into the machine 804 without the stencil as it would interfere with electronic component mounting); and
positioning a chip package (electronic components, ¶92) on the solder paste on the PCB, thereby attaching the second chip package to the PCB (¶92, “After that, the stencil printed bare PCB 10 is passed into a pick and place machine 804 for electronic components to be mounted thereon. The electronic components may be, but not limited, to surface-mount components and through-hole components. Due to the tacky nature of the solder paste, the electronic components would be held in place on the pads”).
However, Chng fails to disclose measuring a warpage parameter of the chip package, namely the electronic components.
Kuo discloses (Title: Interconnection Joints Having Variable Volumes in Package Structures and Methods of Formation Thereof) a method step of measuring a warpage parameter of the chip package, namely the electronic components (col. 4, ll. 62-64, “The warpage characteristics of each package component are then analyzed prior to bonding”).
Though Chng fails to directly disclose such a method, Chng does however teach a similar method, measuring instead the warpage parameter of the substrate. Both the chip package and substrate of the PCB are mating components whose relative locations affects alignment, bonding quality, solder joint reliability, and overall assembly. Similarly, Kuo discloses of a method for analyzing the warpage characteristic of a package component instead to then be mounted upon a printed circuit board via deposition of a stenciled/solder material. Thus, a person of ordinary skill in the art before the effective filing date would have recognized that the same measurement technique used to characterize the warpage of one element is equally applicable to another element due to both elements being subject to warpage disadvantages. In this case, measuring the warpage of Chng’s substrate versus measuring the warpage of Kuo’s package component.
Furthermore, making such a modification would have yielded no more than predictable use of routine optimization, providing operators the flexibility of measuring a more physically/visibly available element for measurement to be mounted upon. Also, a POSITA would have known that measuring the warpage of components of the electronic device would provide obvious advantages, such as decreased production time and cost due to avoiding costly rework or replacement of packages which are unacceptably warped.
Furthermore, Chng and Kuo fail to disclose that the positioned chip package on the solder paste on the PCB is of a second, separate chip package such that the second chip package uses the stencil corresponding the warpage parameter of the first chip package.
Zu discloses a method (Title: Method and Structure for Adapting Solder Column to Warped Substrate) of attaching a chip package (warped board, ¶36; and/or modules, ¶36/37) to a printed circuit board (“PCB”) (PCB, ¶36) comprising:
Positioning a second chip package on the solder paste (solder pads, ¶36) on the PCB such that the second chip package uses the stencil corresponding the warpage parameter of the first chip package (¶36, “Small apertures 504 correspond to locations on the PCB that have no un-desired gap between the module and the solder pads of the PCB substrate. In other words, small apertures 504 may be at an optimum location on the board and be a target column height and radius and therefore do not need to be adapted for warpage. In addition, medium apertures 506 correspond to locations on the PCB that have a midsize gap between the module and the solder pads of the PCB substrate”; ¶37, “The size and shape of the apertures may be customized for each gap distance and location on the PCB. Further, groups of like modules may be sorted according to warpage and alternate stencils may be adapted for the solder printing process for each group”).
Chng discloses a method of attaching a chip package to a printed circuit board comprising of the steps such as measuring a warpage parameter, selecting the proper stencil to compensate for said warpage, and positioning the stencil such that the solder paste may be provided. Kuo discloses of a method for measuring the warpage characteristics of a package component. Zu discloses a method to which the plurality of chip packages, namely the modules, are arranged in groups according to their respective warpage along with alternative stencils adapted for each group (a group consists of the first and second chip package, as claimed, displaying similar forms of warpage). Thus, it would have been obvious to take Zu’s method of rearranging the chip packages into groups corresponding to warpage characteristics and providing a stencil to compensate for the warpage, and apply it to the method steps of measuring and positioning the stencil of Chng and Kuo to achieve the claimed step of measuring “chip packages of the same type”, as described in the instant application’s specifications (¶24), allowing for insight measurement to be done for the second chip package. Such a method of grouping would allow for greater efficiency in PCB production, reducing overall inspection time of each and every single chip package, decrease stencil changeover frequency, and reduce equipment/operator idle time.
Regarding claim 2, Chng, in view of Kuo and Zu, teaches the method of claim 1, as detailed above, and Chng further discloses wherein the warpage parameter is a thickness of the first chip package (¶70, “the first diagonal length tolerance for the bare PCB 10”).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 2 in the manner of grouping warped chip packages to allow for a predetermined measured warpage parameter during manufacturing).
Regarding claim 3, Chng, in view of Kuo and Zu, teaches the method of claim 1, as detailed above, and Chng further discloses wherein the stencil is a first stencil selected from a plurality of stencils disposed in a stencil storage (¶90, “The solder printed machine 802 is configured to have three different physical stencils, namely the A.sub.N stencil 20a, the A+ stencil 20b, and the A− stencil 20c”).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 3 in the manner of grouping warped chip packages to allow for a predetermined measured warpage parameter during manufacturing).
Regarding claim 4, Chng, in view of Kuo and Zu, teaches the method of claim 3, as detailed above, and Zu further discloses wherein the first stencil includes a first aperture having a size that is different than a second aperture of a second stencil.
(¶36-37, Zu discloses that the size of the apertures 504, 506, & 508 are corresponding to the gap between the PCB and module, due to warpage of the module. Zu also discloses that the plurality of stencils comprising of said apertures are varied, corresponding to the module groups, grouped by their respective featured warpage. Thus, each stencil must have unique aperture sizes compared to another stencil)
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(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 4 in the manner of grouping warped chip packages to allow for a predetermined measured warpage parameter during manufacturing).
Regarding claim 5, Chng, in view of Kuo and Zu, teaches the method of claim 4, as detailed above, and Zu further discloses wherein the first aperture and the second aperture are in the same location on their respective stencils (¶37, “The size and shape of the apertures may be customized for each gap distance and location on the PCB”).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 5 in the manner of grouping warped chip packages to allow for a predetermined measured warpage parameter during manufacturing).
Regarding claim 6, Chng, in view of Kuo and Zu, teaches the method of claim 4, as detailed above, and Chng further discloses wherein each of the plurality of stencils includes the same number of apertures (FIGS. 4 & 5 depict two different stencils with varying dimensions; ¶90, “three different physical stencils, namely the A.sub.N stencil 20a, the A+ stencil 20b, and the A− stencil 20c”).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 6 in the manner of grouping warped chip packages to allow for a predetermined measured warpage parameter during manufacturing).
Regarding claim 7, Chng, in view of Kuo and Zu, teaches the method of claim 4, as detailed above, and Zu further discloses wherein the first stencil includes a third aperture having a size that is different than the first aperture (FIG. 5 depicts a stencil with varying aperture sizes, namely small aperture 504, medium aperture 506, and large aperture 508).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 7 in the manner of grouping warped chip packages to allow for a predetermined measured warpage parameter during manufacturing).
Regarding claim 8, Chng, in view of Kuo and Zu, teaches the method of claim 3, as detailed above, and Zu further discloses wherein the plurality of stencils have a substantially same thickness (¶36, “The stencil is of uniform thickness and may be about 5 mils thick, or for example, 4 mils, 6 mils, or 10 mils. An adapted stencil of any thickness is within the scope of these embodiments”).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 8 in the manner of grouping warped chip packages to allow for a predetermined measured warpage parameter during manufacturing).
Regarding claim 9, Chng, in view of Kuo and Zu, teaches the method of claim 1, as detailed above, and Chng further discloses the method further comprising:
positioning the second stencil above the PCB (¶61, “A match-successful condition occurs when all sets of data available in both data files, after comparison, fall within the configured limits of tolerance. This will indicate that the aperture layout 23 of the stencil specification image 22 is fairly aligned to the pad layout 13 of the surface profile image 12”; ¶90 discloses that there are three stencils to choose from; FIG. 4 depicts stencil properly lined up while FIG. 5 depicts stencil misalignment);
applying solder paste on the PCB through the second stencil (¶88, “The apparatus may also be a member of a system for performing solder printing and forming an assembled PCB 30”);
moving the PCB away from the second stencil (¶92, “After that, the stencil printed bare PCB 10 is passed into a pick and place machine 804”; it would be understood to a POSITA that the PCB 10 is passed into the machine 804 without the stencil as it would interfere with electronic component mounting); and
positioning the second chip package on the solder paste on the PCB, thereby attaching the second chip package to the PCB (¶36, “Small apertures 504 correspond to locations on the PCB that have no un-desired gap between the module and the solder pads of the PCB substrate. In other words, small apertures 504 may be at an optimum location on the board and be a target column height and radius and therefore do not need to be adapted for warpage. In addition, medium apertures 506 correspond to locations on the PCB that have a midsize gap between the module and the solder pads of the PCB substrate”; ¶37, “The size and shape of the apertures may be customized for each gap distance and location on the PCB. Further, groups of like modules may be sorted according to warpage and alternate stencils may be adapted for the solder printing process for each group”).
However, Chng and Kuo fail to disclose the method comprising selecting a second stencil based on a warpage parameter of a third chip package. Chng also fails to disclose that the PCB moving away from the second stencil is of a second PCB.
Zu discloses method comprising selecting a second stencil (stencil of a second group) based on a warpage parameter of a third chip package (in ¶36-37 that there are multiple groups of chip packages/modules, each group comprising of modules having similar warpage parameters such that a singular adaptive stencil may be used for one group. The second group is mapped such that it comprises of the second stencil and a third chip package corresponding to a warpage different from the first and second chip package).
Moving the second PCB away from the second stencil (Chng teaches the step of moving a PCB away from a stencil. In combination of Chng and Zu, it would have been obvious to a POSITA that the same process may occur for repeated steps, such that a second PCB is manufactured, requiring a second PCB to also be moved away from a second stencil).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 9 in the manner of grouping warped chip packages to allow for a predetermined measured warpage parameter during manufacturing).
Regarding claim 11, Chng, in view of Kuo and Zu, teaches the method of claim 1, as detailed above, and Chng further discloses the method further comprising performing a reflow process after positioning the chip package on the PCB (¶92, “Then the PCB with the components enters the solder reflow machine 805. The solder reflow machine 805 applies heat gradually for the solder paste to melt so that a secure solder joint can be formed between the contacts of the electronic components and the pads of the bare PCB 10”).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 11 in the manner of grouping warped chip packages to allow for a predetermined measured warpage parameter during manufacturing).
Regarding claim 12, Chng, in view of Kuo and Zu, teaches the method of claim 1, as detailed above, and Chng further discloses wherein the plurality of apertures of the stencil correspond to a plurality of pads of the PCB for connection with the first chip package (¶60, “the aperture layout 23 can align to the pad layout 13”).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 12 in the manner of grouping warped chip packages to allow for a predetermined measured warpage parameter during manufacturing).
Regarding claim 14, Chng and Kuo discloses the method of claim 13, as detailed above, and Chng further discloses wherein the plurality of stencils includes a second stencils having a plurality of second apertures (¶90, “three different physical stencils, namely the A.sub.N stencil 20a, the A+ stencil 20b, and the A− stencil 20c”).
However, Chng and Kuo fail to discloses wherein the second stencil including a plurality of second apertures having a different size than the plurality of first apertures.
Zu discloses a method (Title: Method and Structure for Adapting Solder Column to Warped Substrate) of attaching a chip package (warped board, ¶36; and/or modules, ¶36/37) to a printed circuit board (“PCB”) (PCB, ¶36) comprising:
A second stencil including a plurality of second apertures having a different size than the plurality of the first apertures (As detailed in ¶36-37, Zu discloses groups of chip packages/modules that features similar warpage. Each group is paired with an adaptive stencil with various apertures such as "small aperture 504, medium aperture 506, and large aperture 508”. Thus, different groups and their respective stencil features various size changes of apertures).
(Regarding the reason to combine references, refer to the rejection of claim 1 and 13, supra, as it is applicable to the rejection of claim 14 in the manner of grouping warped chip packages to allow for a predetermined measured warpage parameter during manufacturing as well as how groups of stencil packages/modules have their own respective unique stencil compensating for the group’s uniquely measured warpage parameter).
Regarding claim 15, Chng, in view of Kuo and Zu, teaches the method of claim 14, as detailed above, and Zu further discloses wherein the second stencil is configured to compensate for warpage corresponding to a second measured warpage parameter (As detailed in ¶36-37, Zu discloses groups and their corresponding stencil regarding the group’s warpage. Thus, it would have been obvious to a POSITA that a second stencil corresponding a second measured warpage parameter, mapped as another group, or similarly a second group and its respective stencil, would read onto the immediately claimed language).
(Regarding the reason to combine references, refer to the rejection of claim 1, 13, and 14, supra, as it is applicable to the rejection of claim 15 in the manner of grouping warped chip packages to allow for a predetermined measured warpage parameter during manufacturing as well as how groups of stencil packages/modules have their own respective unique stencil compensating for the group’s uniquely measured warpage parameter).
Regarding claim 16, Chng, in view of Kuo and Zu, teaches the method of claim 13, as detailed above, and Zu further discloses wherein the number of apertures and a thickness of each of the plurality of stencils is about the same (¶36, “The stencil is of uniform thickness and may be about 5 mils thick, or for example, 4 mils, 6 mils, or 10 mils. An adapted stencil of any thickness is within the scope of these embodiments”; FIG. 5 depicts a set number of apertures, only varying in size regarding warpage).
(Regarding the reason to combine references, refer to the rejection of claim 1 and 13, supra, as it is applicable to the rejection of claim 16 in the manner of grouping warped chip packages to allow for a predetermined measured warpage parameter during manufacturing as well as how groups of stencil packages/modules have their own respective unique stencil compensating for the group’s uniquely measured warpage parameter).
Regarding claim 18, Chng and Kuo disclose the device of claim 17, as detailed above.
However, Chng and Kuo fail to disclose wherein the first predetermined warpage characteristic is determined using a second chip package.
Zu discloses a method (Title: Method and Structure for Adapting Solder Column to Warped Substrate) of attaching a chip package (warped board, ¶36; and/or modules, ¶36/37) to a printed circuit board (“PCB”) (PCB, ¶36) comprising:
A first predetermined warpage characteristic determined from a second chip package (As detailed in ¶36-37, Zu discloses groups and their corresponding stencil regarding the group’s warpage. Thus, it would have been obvious to a POSITA that a first and second chip package, organized into one group according to similar warpage, would further have both of their warpage characteristics measured, resulting in both warpages measured).
(Regarding the reason to combine references, refer to the rejection of claim 1 and 13, supra, as it is applicable to the rejection of claim 18 in the manner of grouping warped chip packages to allow for a predetermined measured warpage parameter during manufacturing as well as how groups of stencil packages/modules have their own respective unique stencil compensating for the group’s uniquely measured warpage parameter).
Regarding claim 19, Chng, in view of Kuo and Zu, teaches the device of claim 18, as detailed above, and Zu further discloses wherein the first predetermined warpage characteristic is at least one of stress or warpage analysis of the second chip package (¶36, “Apertures such as small aperture 504, medium aperture 506, and large aperture 508 are formed in adaptive stencil 500 and placed on the stencil in locations corresponding to the locations of gap distances of a warped board”).
(Regarding the reason to combine references, refer to the rejection of claim 1, 17, and 18, supra, as it is applicable to the rejection of claim 19 in the manner of grouping warped chip packages to allow for a predetermined measured warpage parameter during manufacturing as well as how groups of stencil packages/modules have their own respective unique stencil compensating for the group’s uniquely measured warpage parameter).
Regarding claim 20, Chng, in view of Kuo and Zu, teaches the device of claim 17, as detailed above, and Zu further discloses the electronic device of claim 17 further comprising:
a second chip package having a second predetermined warpage characteristic (As detailed in ¶36-37, Zu discloses groups and their corresponding stencil regarding the group’s warpage. Thus, it would have been obvious to a POSITA that the first chip package is of a first group and the second chip package is of a separate and different organized group according to a different warpages) electrically and mechanically connected to the chip package,
the PCB comprising a second stenciled material (solder paste, ¶35) disposed thereon that is patterned based on the second predetermined warpage characteristic of the second chip package, wherein first and second predetermined warpage characteristics are different (¶35-37, “A measured amount of solder paste is applied to the top of the stencil and the squeegee forces solder paste through the apertures and onto the PCB, printing the solder paste onto the PCB.”; a POSITA would have recognized that the first and second chip packages feature distinct warpage parameters, allowing them to be categorized into two separate groups. Thus, the second chip package requires a pattern based on its own warpage and not the warpage of the first chip package).
(Regarding the reason to combine references, refer to the rejection of claim 1 and 17, supra, as it is applicable to the rejection of claim 20 in the manner of grouping warped chip packages to allow for a predetermined measured warpage parameter during manufacturing as well as how groups of stencil packages/modules have their own respective unique stencil compensating for the group’s uniquely measured warpage parameter).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE REY D LEGASPI whose telephone number is (571)272-2956. The examiner can normally be reached Monday-Friday 8-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hong can be reached at (571) 272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/E.D.L./Examiner, Art Unit 3729 /THOMAS J HONG/Supervisory Patent Examiner, Art Unit 3729
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