DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, i.e., claims 1-19, in the reply filed on May 20, 2026 is acknowledged.
Claim 20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on May 20, 2026.
Claim Objections
Claims 1-5, 8 and 15-17. objected to because of the following informalities:
Claim 1 recites the limitation “A semiconductor package comprising: at least one first substrate and second substrate each comprising a specific metal pattern formed thereon to enable electrical connection; at least one semiconductor chip each bonded to one side surface of the first substrate, the second substrate, or the first and second substrates; at least one three-dimensional clip structure comprising one side surface bonded to one side surface of the at least one semiconductor chip and the other side surface bonded to each of the metal patterns of the first substrate, the second substrate, or the first and second substrates; at least one terminal lead each bonded to the first substrate, the second substrate, or the first and second substrates; and a package housing molded to cover the semiconductor chips, wherein one side surface of the three-dimensional clip structure bonded to the one side surface of the semiconductor chip is extended in an X-axis direction and the other side surface of the three-dimensional clip structure bonded to each of the metal patterns of the first substrate, the second substrate, or the first and second substrates is extended in a Y-axis direction which is perpendicular to the X-axis direction” in lines 1-17.
However, there is a lack of antecedent basis for “the semiconductor chips” and “the three-dimensional clip structure” in the claim. Changing “the semiconductor chips” and “the three-dimensional clip structure” to -- the at lease one semiconductor chip-- and --the at least one three-dimensional clip structure-- throughout the claim provides proper antecedent basis.
Similar changes should be made in claims 2-5, 8 15, 16 and 17.
Claim 1 recites the limitation “at least one semiconductor chip each bonded to one side surface of the first substrate” in lines 4. The limitation “at least one semiconductor chip” recites singular chip, whereas “each bonded” indicates plurality of chips. Therefore, the claim lacks clarity. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the first and second substrates” in lines 5 and thought the claim. However, the is lack of antecedent basis inf the claims for “the first and second substrates”. Therefore, the claim lacks clarity in the scope.
Claims 2-19 are also rejected as being directly or indirectly dependent of the rejected independent base claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 7-10 and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHOI et al. (US 2018/0240731).
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Re Claim 1, CHOI et al. disclose a semiconductor package comprising: at least one first substrate (200) and second substrate (500) each comprising a specific metal pattern (210) formed thereon to enable electrical connection (see fig. 2 Paragraph [0027]); at least one semiconductor chip (300) each bonded to one side surface of the first substrate (300) or the second substrate at least one three-dimensional clip structure (600, Paragraph [0033]) comprising one side surface bonded to one side surface of the at least one semiconductor chip (300) and the other side surface bonded to each of the metal patterns of the first substrate, the second substrate, or the first and second substrates; at least one terminal lead (400) each bonded to the first substrate (300 and a package housing molded (100) to cover the semiconductor chip (300), wherein one side surface of the three-dimensional clip structure (600) bonded to the one side surface of the semiconductor chip (300) is extended in an X-axis direction and the other side surface of the three-dimensional clip structure bonded to each of the metal patterns of the first substrate is extended in a Y-axis direction which is perpendicular to the X-axis direction (see Fig. 2 and related text in Paragraphs [0025] – [0034]).
Re Claim 2, as applied to claim 1 above, CHOI et al. disclose all the claimed limitations including wherein one side surface of the three-dimensional clip structure comprises a first surface which forms a first bonded contact point with the semiconductor chip, the other side surface of the three-dimensional clip structure comprises a second surface which forms a second bonded contact point with the first substrate or the metal pattern of the second substrate and a third surface which forms two separate third bonded contact points with the second substrate or the metal pattern of the first substrate, and the first surface and the second surface are bent to form a level difference (see Fig. 2 and related text in Paragraphs [0025] – [0034]).
Re Claim 4, as applied to claim 2 above, CHOI et al. disclose all the claimed limitations including wherein the three-dimensional clip structure comprises an upper surface and a lower surface facing the upper surface, and the first surface, the second surface, or the third surface is formed on any one same surface from among the upper surface and the lower surface.
6. (Original) The semiconductor package of claim 1, wherein the terminal lead has a stacked structure comprising at least two layers of each different metal.
Re Claim 7, as applied to claim 1 above, CHOI et al. disclose all the claimed limitations including wherein the first substrate or the second substrate comprises at least one insulating layer, or a single metal layer, or a mixed metal layer in an alloy form, or a plated form or a stacked structure comprising at least one lower metal layer, at least one upper metal layer, and at least one insulating layer interposed between the lower metal layer and the upper metal layer (see Paragraph [0027]).
Re Claim 8 as applied to claim 2 above, CHOI et al. disclose all the claimed limitations including wherein one side surface of the three-dimensional clip structure has a lower structure joining the one side surface of the semiconductor chip and the other side surface of the three-dimensional clip structure has an upper structure joining the first substrate or the metal pattern of the second substrate so that a three-dimensional structure is formed.
Re Claim 9, as applied to claim 1 above, CHOI et al. disclose all the claimed limitations including wherein the terminal lead is bonded to the first substrate, the second substrate, or the first and second substrates by using soldering, sintering, or ultrasonic welding (Paragraph [0030]).
Re Claim 10, as applied to claim 1 above, CHOI et al. disclose all the claimed limitations including wherein the other side of the first substrate or the second substrate is partially or entirely exposed to one side surface or the other side surface of the package housing.
Re Claim 13, as applied to claim 1 above, CHOI et al. disclose all the claimed limitations including wherein the other side surface of the first substrate or the second substrate comprises a heat sink bonded thereto by using a heat transfer material (Paragraph [0026]).
Allowable Subject Matter
Claims 3, 5, 6, 11, 12 and 14-19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 3, 5, 11, 12 and 14-19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure CHOI (US 2022/0359452) and CHOI (US 2022/0399300) disclose semiconductor package that includes first and second substrates a meal bridge between the first and second substrate and a semiconductor chip bonded to form semiconductor package.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BROOK KEBEDE whose telephone number is 571-272-1862. The examiner can normally be reached Monday Friday 8:00 AM 5:00 PM.
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/BROOK KEBEDE/
Primary Examiner, Art Unit 2894
/BK/
June 26, 2026
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