Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the first insulating layer" in lines 16-17 (last limitation of claim 1). There is insufficient antecedent basis for this limitation in the claim.
Claim 2 recites the limitation "the first insulating layer" in lines 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the first insulating layer" in lines 3 and 5. There is insufficient antecedent basis for this limitation in the claim.
Claim 5 recites the limitation "the first insulating layer" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim.
Claims 3 and 6-10 are rejected due to their dependency on claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11 and 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tseng et al. (US 11088202).
Regarding claim 11, Tseng discloses a magnetoresistive random access memory device, comprising:
a substrate (102) a substrate (102) [Figs. 3-4 and 21];
a lower electrode contact (112) on the substrate [Figs. 3-4 and 21];
a lower electrode (116) contacting an upper surface of the lower electrode contact (112) [Figs. 3-4 and 21]; and
a memory structure (206/120) contacting an entire upper surface of the lower electrode (116), the memory structure including a stacked MTJ structure (206) and upper electrode (120) [Figs. 3-4 and 21];
wherein the lower electrode (116) has a rounded sidewall (rounded sidewall ) and a width of the lower electrode (116) increases from a lower portion to an upper portion [Figure 3, annotated below].
Regarding claim 15, Tseng discloses wherein:
the memory structure (206/120) has a sidewall profile such that a width of the memory structure increases from an upper portion to a lower portion [Figs. 3-4 and 21], and a sidewall (edges having angle α) of the memory structure (206/120) has a constant slope portion [Fig. 3 and col. 6, lines 16-43].
Regarding claim 16, Tseng discloses wherein:
an upper surface of the lower electrode (116) and a lower surface (208) of the MTJ structure (206/120) have the same area [Figs. 3-4 and 21], and
the upper surface of the lower electrode (116) and the lower surface of the MTJ structure (206/120) are aligned to each other [Figs. 3-4 and 21].
Regarding claim 17, Tseng discloses:
the lower electrode (116) includes a first portion (P1) and a second portion (P2) on the first portion [Fig. 3, annotated below],
the first portion (P1) of the lower electrode (116) has a lower sidewall profile having a rounded sidewall profile (rounded sidewall) such that a width of the first portion increases from a lower portion toward an upper portion [Fig. 3, annotated below], and
the second portion (P2) has an upper sidewall profile (116s) such that a width of the second portion decreases from a lower portion toward an upper portion [Fig. 3, annotated below, and col. 6, lines 16-43].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-10, and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Tseng et al. (US 11088202) in view of Hashemi et al. (US 2021/0043827).
Regarding claims 1 and 12, Tseng discloses a magnetoresistive random access memory device, comprising:
a substrate (102) [Figs. 3-4 and 21];
conductive patterns (112) on the substrate [Figs. 3-4, 6 and 21];
an insulating interlayer (106) covering the conductive patterns [Figs. 3-4 and 21];
a lower electrode contact (conductive vias) [col. 4, lines 35-41];
a lower electrode (116) on the lower electrode contact, the lower electrode including a rounded sidewall [Figs. 3-4, 9-11, and 21]; and
a memory structure (206/120) on the lower electrode, the memory structure including a stacked MTJ structure (206) and upper electrode (120) [Figs. 3-4 and 21],
wherein:
a width of the lower electrode (116) increases from a lower portion to an upper portion [consider the T-shape 116 in Figs. 3-4, 9-11, and 21],
the memory structure (206/120) has a sidewall slope such that a width of the memory structure increases from an upper portion to a lower portion [Figs. 3-4 and 21], and at least a portion of a sidewall of the lower electrode (116) is covered by the first insulating interlayer (106) [Figs. 3-4 and 21].
However, Tseng does not show a lower electrode contact passing through the insulating interlayer, the lower electrode contact contacting the conductive patterns.
Hashemi teaches a lower electrode contact (16L) passing through the insulating interlayer (14), the lower electrode contact (16L) contacting the conductive patterns (12) [Fig. 12].
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Tseng by a lower electrode contact as taught by Hashemi because helps to improve the electrical characteristics of the device.
Regarding claim 3, Tseng discloses: an upper surface of the lower electrode (116) and a lower surface (208) of the MTJ structure (206) have the same area, and
the upper surface of the lower electrode (116) and the lower surface (208) of the MTJ structure (206) are aligned to each other [Figs. 3-4 and 21].
Regarding claim 4, Tseng discloses: the first insulating interlayer (202) between the memory structures (206) has a recessed shape [Fig. 11], and an upper surface of the first insulating interlayer (202) between the memory structures (206) is lower than an upper surface of the lower electrode (116) [Figs. 3-4, 6 and 21].
Regarding claim 5, Tseng discloses: a protective layer (122/124) covering an upper surface of the first insulating interlayer (202) and a surface of the memory structure (206) [Figs. 3-4 and 21].
Regarding claim 6, Tseng discloses the protective layer (122/124) contacts a portion of the sidewall of the lower electrode (202), or does not contact the sidewall of the lower electrode (202) [Figs. 3-4 and 21].
Regarding claim 7, Tseng discloses wherein the lower electrode (116) includes tungsten, titanium, tantalum, tungsten nitride, titanium nitride, or tantalum nitride [col. 4, lines 61-67].
[AltContent: textbox (recessed shape between memory structures (206))][AltContent: arrow][AltContent: textbox (P1 )][AltContent: textbox (P2)][AltContent: connector][AltContent: textbox (Rounded Sidewall )][AltContent: arrow][AltContent: textbox (Figure 3 (annotated) )]
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Regarding claim 8, Tseng discloses an insulation spacer (122) on the sidewall of the lower electrode (116) [Figs. 3-4 and 21].
Regarding claim 9, Hashemi teaches wherein a bottom surface of the lower electrode (22S/19L) has an area the same as or less than an area of an upper surface of the lower electrode contact (16L) [Fig. 12].
Regarding claim 10, Tseng discloses:
the lower electrode (116) includes a first portion (P1) and a second portion (P2) on the first portion [Fig. 3, annotated above],
the first portion (P1) of the lower electrode (116) has a lower sidewall profile having a rounded sidewall profile (rounded sidewall) such that a width of the first portion increases from a lower portion toward an upper portion [[Fig. 3, annotated above], and
the second portion (P2) has an upper sidewall profile (116s) such that a width of the second portion decreases from a lower portion toward an upper portion [Fig. 3, annotated above, and col. 6, lines 16-43].
Regarding claim 13, Tseng discloses wherein a bottom surface of the lower electrode (116) is lower than an uppermost surface of the first insulating interlayer (202/107c) [Figs. 3, 4 and 21].
Regarding claim 14, Tseng discloses: a protective layer (122/124) covering an upper surface of the first insulating interlayer (202) and a surface of the memory structure (206) [Figs. 3-4 and 21].
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tseng et al. (US 11088202) in view of Park et al. (US 9722172), cited by applicant.
Regarding claim 18, Tseng discloses a magnetoresistive random access memory device, comprising:
a substrate (102) [Figs. 3-4 and 21];
a lower structure (112) on the substrate [Figs. 3-4, 6 and 21];
an insulating interlayer (106) covering the lower structure [Figs. 3-4 and 21];
a lower electrode (116), the lower electrode having a width increasing from a lower portion to an upper portion, and the lower electrode (116) including a rounded sidewall [Fig. 3, annotated above]; and
a memory structure (206/120) in which an MTJ structure (206) and an upper electrode (120) are stacked on the lower electrode [Figs. 3-4 and 21],
However, Tseng does not show a lower electrode contact passing through the insulating interlayer, the lower electrode contact contacting the conductive patterns.
Park teaches a lower electrode contact (110) passing through the insulating interlayer (105), the lower electrode contact (110) contacting the lower structure (terminal) [Fig. 1A and col. 5, lines 17-22], the lower electrode contact (110) having an upper surface lower than an uppermost surface of the insulating interlayer (105) [Fig. 1A]; a lower electrode (120) on the lower electrode contact (110) [Fig. 1A], wherein a bottom surface of the lower electrode (120) has an area that is the same as or less than an area of an upper surface of the lower electrode contact (110) [Fig. 1A].
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Tseng by including a lower electrode contact as taught by Park because it helps to improve the characteristics of the device [col. 5, lines 5-6].
Regarding claim 19, Tseng discloses an insulation spacer (122) on a sidewall of the lower electrode (116) [Figs. 3-4 and 21].
Regarding claim 20, Tseng discloses wherein:
the lower electrode contact (116/902) includes a first electrode contact conductive material deposited before planarization) and a second electrode contact (additional conductive material deposited after planarization) stacked on the first electrode contact [Fig. 9, col. 9, lines 55-67 and col. 10, lines 1-4],
the first electrode contact includes a first metal [e.g. titanium], and
the second electrode contact includes a second metal [e.g. tantalum] having a resistance lower than a resistance of the first metal [Please note that tantalum (131 nΩ∙m) has a lower resistivity than titanium (180 nΩ∙m). Hence, the resistance (R=ρ∙(L/A)) of tantalum can also be assumed to be lower than titanium, when the length and area of both first and second electrode contacts are about the same. See Fig. 9, col. 9, lines 55-67 and col. 10, lines 1-4. In addition, the court has held that it is within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960); Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945)].
7. Claims 1-10 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Tseng et al. (US 11088202) in view of Hashemi et al. (US 2020/0295256).
Regarding claims 1 and 12, Tseng discloses a magnetoresistive random access memory device, comprising:
a substrate (102) [Figs. 3-4 and 21];
conductive patterns (112) on the substrate [Figs. 3-4, 6 and 21];
an insulating interlayer (106) covering the conductive patterns [Figs. 3-4 and 21];
a lower electrode contact (conductive vias) [col. 4, lines 35-41];
a lower electrode (116) on the lower electrode contact, the lower electrode including a rounded sidewall [Figs. 3-4, 9-11, and 21]; and
a memory structure (206/120) on the lower electrode, the memory structure including a stacked MTJ structure (206) and upper electrode (120) [Figs. 3-4 and 21],
wherein:
a width of the lower electrode (116) increases from a lower portion to an upper portion [consider the T-shape 116 in Figs. 3-4, 9-11, and 21],
the memory structure (206/120) has a sidewall slope such that a width of the memory structure increases from an upper portion to a lower portion [Figs. 3-4 and 21], and at least a portion of a sidewall of the lower electrode (116) is covered by the first insulating interlayer (106) [Figs. 3-4 and 21].
However, Tseng does not show a lower electrode contact passing through the insulating interlayer, the lower electrode contact contacting the conductive patterns.
Hashemi teaches a lower electrode contact (14) passing through the insulating interlayer (12) [Fig. 10A].
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Tseng by a lower electrode contact as taught by Hashemi because helps to improve the electrical characteristics of the device.
Regarding claim 2, Hashemi teaches wherein an uppermost surface of the first insulating interlayer (16) and an upper surface of the lower electrode (40) are coplanar with each other [Fig. 10A, annotated below].
[AltContent: textbox (Coplanar surfaces)][AltContent: arrow][AltContent: arrow]
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Regarding claim 3, Tseng discloses: an upper surface of the lower electrode (116) and a lower surface (208) of the MTJ structure (206) have the same area, and
the upper surface of the lower electrode (116) and the lower surface (208) of the MTJ structure (206) are aligned to each other [Figs. 3-4 and 21].
Regarding claim 4, Tseng discloses: the first insulating interlayer (202) between the memory structures (206) has a recessed shape [Fig. 11], and an upper surface of the first insulating interlayer (202) between the memory structures (206) is lower than an upper surface of the lower electrode (116) [Figs. 3-4, 6 and 21].
Regarding claim 5, Tseng discloses: a protective layer (122/124) covering an upper surface of the first insulating interlayer (202) and a surface of the memory structure (206) [Figs. 3-4 and 21].
Regarding claim 6, Tseng discloses the protective layer (122/124) contacts a portion of the sidewall of the lower electrode (202), or does not contact the sidewall of the lower electrode (202) [Figs. 3-4 and 21].
Regarding claim 7, Tseng discloses wherein the lower electrode (116) includes tungsten, titanium, tantalum, tungsten nitride, titanium nitride, or tantalum nitride [col. 4, lines 61-67].
Regarding claim 8, Tseng discloses an insulation spacer (122) on the sidewall of the lower electrode (116) [Figs. 3-4 and 21].
Regarding claim 9, Hashemi teaches wherein a bottom surface of the lower electrode (40) has an area
Regarding claim 10, Tseng discloses:
the lower electrode (116) includes a first portion (P1) and a second portion (P2) on the first portion [Fig. 3, annotated above],
the first portion (P1) of the lower electrode (116) has a lower sidewall profile having a rounded sidewall profile (rounded sidewall) such that a width of the first portion increases from a lower portion toward an upper portion [[Fig. 3, annotated above], and
the second portion (P2) has an upper sidewall profile (116s) such that a width of the second portion decreases from a lower portion toward an upper portion [Fig. 3, annotated above, and col. 6, lines 16-43].
Regarding claim 13, Tseng discloses wherein a bottom surface of the lower electrode (116) is lower than an uppermost surface of the first insulating interlayer (202/107c) [Figs. 3, 4 and 21].
Regarding claim 14, Tseng discloses: a protective layer (122/124) covering an upper surface of the first insulating interlayer (202) and a surface of the memory structure (206) [Figs. 3-4 and 21].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
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/Jose R Diaz/Primary Examiner, Art Unit 2815
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