DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I (Claims 1-6) in the reply filed on 3/12/26 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3- 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen US 2019/0131273.
Pertaining to claim 1, Chen teaches a three-dimensional integrated circuit structure, comprising:
a first semiconductor die 100; and
a second semiconductor die 300 disposed on the first semiconductor die 100,
wherein the first semiconductor die includes:
a plurality of through-silicon vias (TSV TSV1); and
a plurality of integrated stack capacitor (ISC) chips CA1, wherein each of the plurality of ISC chips is disposed between adjacent through-silicon vias among the plurality of through-silicon vias See Figures 13 and 16 below and [0041[.
PNG
media_image1.png
480
798
media_image1.png
Greyscale
PNG
media_image2.png
358
428
media_image2.png
Greyscale
Pertaining to claim 3, Chen teaches the three-dimensional integrated circuit structure of claim 1, wherein the plurality of through-silicon vias is alternately arranged with the plurality of integrated stacked capacitor chips. See Figure 16 marked up above
Pertaining to claim 4, Chen teaches the three-dimensional integrated circuit structure of claim 1, wherein a distance between a through-silicon via of the plurality of through-silicon vias and an integrated stack capacitor chip, of the plurality of integrated stack capacitor chip, adjacent to the through-silicon via is smaller than a width of each through-silicon via of the plurality of through-silicon vias in a horizontal direction. See Figure 16 marked up below
PNG
media_image3.png
364
478
media_image3.png
Greyscale
Pertaining to claim 5, Chen teaches the three-dimensional integrated circuit structure of claim 1, wherein the second semiconductor die includes a system on chip (SOC). [0027]
Pertaining to claim 6, Chen teaches the three-dimensional integrated circuit structure of claim 1, further comprising a molding material E2 disposed on the second semiconductor die and on the first semiconductor die. See Figure 13
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, and further in view of US 2021/0384073.
Pertaining to claim 2, Chen teaches the three-dimensional integrated circuit structure of claim 1, but fails to teach wherein the integrated stack capacitor chip includes:
a lower plate layer;
an insulating layer disposed on the lower plate layer and including a plurality of through-holes;
a lower electrode continuously and conformally extending along an inside of the plurality of through-holes and along the insulating layer;
a dielectric film disposed on the lower electrode;
an upper electrode disposed on the dielectric film;
a conductive interconnection member disposed on the upper electrode; and
an upper plate layer disposed on the conductive interconnection member.
Lv teaches an integrated stack capacitor chip including:
a lower plate layer 101/111;
an insulating layer 102 disposed on the lower plate layer and including a plurality of through-holes 115;
a lower electrode 113 continuously and conformally extending along an inside of the plurality of through-holes and along the insulating layer 102;
a dielectric film 114 disposed on the lower electrode;
an upper electrode 115 disposed on the dielectric film;
a conductive interconnection member 103 disposed on the upper electrode; and
an upper plate layer 116 disposed on the conductive interconnection member 103.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to substitute the capacitor as taught by Chen with the capacitor taught by Lv because such a modification represents simple substitution of one known element for another with predictable results (they are capacitors and capacitors are known in the art as energy storage elements). See MPEP 2143(B). When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co v. Teleflex Inc.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
Prosecution Insights