DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group (II), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6 February 2026.
Applicant’s election without traverse of Group I in the reply filed on 6 February 2026 is acknowledged.
Applicant’s election without traverse of Species A and Species C2 in the telephone interview conducted on 6 May 2026 with Applicant’s Representative, Tyler P. Del Rosario, is acknowledged.
The Applicant’s Representative has indicated that claims 12-13 and 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group (II) and Species (B and C1), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6 May 2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 30 October 2023 has been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-6 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chien-Yuan Huang et al. (US 2023/0025094 A1; hereinafter “Huang”).
Regarding Claim 1, Huang teaches a semiconductor structure comprising:
an interconnect structure (106, Fig. 45, para [0015] describes an interconnect structure 106) on a substrate (102, Fig. 45, para [0015] describes a semiconductor substrate 102 upon which the interconnect structure 106 is disposed);
an interlayer dielectric layer on the interconnect structure (120 and 124, Fig. 45, para [0020] describes a passivation layer 120 that may be comprised of silicon nitride and para [0025] describes a dielectric layer 124 that may be comprised of silicon nitride wherein the dielectric layers 120 and 124 comprised of a same material form an interlayer dielectric layer);
at least one first conductive pad within the interlayer dielectric layer and electrically coupled with the interconnect structure (118b, Fig. 37, para [0019] describes die pad 118b within the interlayer dielectric layer 120 and 124 and electrically connected to the interconnect structure 106);
at least one second conductive pad within the interlayer dielectric layer and electrically decoupled from the interconnect structure (118c, Fig. 45, para [0076] describes a dummy die pads 118c within the interlayer dielectric layer 120 and 124 and electrically insulated from the interconnect structure 106);
at least one first via plug within the interlayer dielectric layer (V11, Fig. 45, para [0076] describes a conductive via V11 within the interlayer dielectric layer 120 and 124); and
a bonding structure on the interlayer dielectric layer (125 and BP11-BP14, Fig. 45, para [0027] describes a bonding structure) and comprising at least one first bonding pad (BP11, Fig. 45, para [0028] describes an active bonding pad BP11), a plurality of second bonding pads (BP12, BP13 and BP14, Fig. 45, para [0028] describes dummy bonding pads BP12, BP13 and BP14), and a bonding dielectric layer (125, Fig. 45, para [0027] describes a bonding dielectric layer 125),
wherein the at least one first bonding pad is electrically coupled to the at least one first via plug (BP11, Fig. 45, para [0057] describes wherein active bonding pad BP11 is electrically connected to the at least one first via V11),
wherein some of the plurality of second bonding pads are spaced apart from the at least one first conductive pad in a vertical direction (BP12 and BP13, Fig. 45, para [0028] describes the dummy bonding pads BP12 and BP13 which can be seen spaced apart from the first conductive pad 118b in a vertical direction in Fig. 45), and
wherein others of the plurality of second bonding pads are spaced apart from the at least one second conductive pad in the vertical direction (BP14, Fig. 45, para [0028] describes the dummy bonding pad BP14 which can be seen spaced apart from the second conductive pad 118c in a vertical direction in Fig. 45).
Regarding Claim 3, Huang teaches the semiconductor structure of claim 1, wherein the at least one first conductive pad comprises a probe mark (118b, Fig. 45, para [0019] describes wherein first conductive pad 118b may have probe marks on the top surface thereof).
Regarding Claim 4, Huang teaches the semiconductor structure of claim 1, wherein the at least one second conductive pad comprises a dummy conductive pad (118c, Fig. 45, para [0076] describes wherein the second conductive pad 118c is a dummy die pad).
Regarding Claim 5, Huang teaches the semiconductor structure of claim 1, wherein the at least one second conductive pad is on a same level as a level of the at least one first conductive pad (118c and 118b, Fig. 45 depicts wherein the at least one second conductive pad 118c is on a same level as a level of the at least one first conductive pad 118b).
Regarding Claim 6, Huang teaches the semiconductor structure of claim 1, wherein each of the plurality of second bonding pads comprises a dummy bonding pad (BP12, BP13 and BP14, Fig. 45, para [0028] describes wherein each of the plurality of second bonding pads BP12, BP13 and BP14 are dummy bonding pads).
Regarding Claim 10, Huang teaches the semiconductor structure of claim 1, further comprising a third conductive pad between the first via plug and the interconnect structure (118a, Fig. 45, para [0024] describes a conductive die pad 118a which is between the first via plug V11 and the interconnect structure 106).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chien-Yuan Huang et al. (US 2023/0025094 A1; hereinafter “Huang”) in view of Heungkyu Kwon et al. (US 2016/0133585 A1; hereinafter “Kwon”).
Regarding Claim 2, Huang discloses all the limitations of claim 1.
Huang discloses wherein the at least one first conductive pad comprises a test pad (118b, Fig. 45, para [0019] describes wherein the at least one first conductive pad 118b may have a probe mark wherein a probe mark would be the result of the pad 118b being involved in a testing process).
Huang fails to explicitly disclose the semiconductor structure of claim 1, wherein the at least one first conductive pad comprises an electrical die sorting (EDS) test pad.
However, Kwon teaches a similar semiconductor device, wherein the at least one first conductive pad comprises an electric die sorting test (EDS) test pad (153, Fig. 2, para [0049] describes an EDS conductive pad 143 connected to a redistribution structure of a semiconductor chip 100).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Huang with Kwon to further disclose a semiconductor device wherein a first conductive pad may comprise an electric die sorting test pad in order to provide the advantage of enabling for an electrostatic test to be performed when forming a wafer to reduce the number of defective wafers produced in a manufacturing process therefore reducing manufacturing costs (Kwon, para [0055]).
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Chien-Yuan Huang et al. (US 2023/0025094 A1; hereinafter “Huang”) in view of Szu-Ying Chen et al. (2015/0279888 A1; hereinafter “Chen”).
Regarding Claim 7, Huang discloses all the limitations of claim 1.
Huang fails to explicitly disclose the semiconductor structure of claim 1, wherein the at least one second conductive pad is a plurality of second conductive pads, and wherein each of the others of the plurality of second bonding pads is connected to a respective one among the plurality of second conductive pads.
However, Chen teaches a similar semiconductor device , wherein the at least one second conductive pad is a plurality of second conductive pads (224B, Fig. 9, para [0033] describes dummy pads 224B wherein a plurality of dummy pads 224B would comprise a plurality of second conductive pads) and
wherein each of the others of the plurality of second bonding pads is connected to a respective one among the plurality of second conductive pads (124B, Fig. 9, para [0038] describes dummy metal pads 124B bonded to second dummy conductive pads 234B wherein para [0038] describes second conductive pads 224B and second bonding pads 124B are bonded with a one-to-one correspondence resulting in each of the others of plurality of second bonding pads 124B being connected to a respective one among the plurality of second conductive pads 224B).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Huang with Chen to further disclose a semiconductor device wherein a second conductive pad comprises a plurality of conductive pads that are connected to a respective second bonding pad in order to provide the advantage of reducing the pattern-loading effect and dishing effect in a CMP process reducing defects such as air bubbles in the bonding process (Chen, para [0045]).
Regarding Claim 8, the combination of Huang and Chen discloses the semiconductor structure of claim 7, wherein each of the others of the plurality of second bonding pads is spaced apart from the plurality of second conductive pads (Huang, BP14, Fig. 45, para [0028] wherein upon combining Huang with Chen, each of the others of the plurality of second bonding pads BP14 of Huang and 124B of Chen, would be spaced apart from the plurality of second conductive pads due to the presence of a portion of the interlayer dielectric layer 124 and thermal vias V12 separating bonding pads BP12-BP14 from second conductive pads 118c of Huang).
Regarding Claim 9, the combination of Huang and Chen discloses the semiconductor structure of claim 7, further comprising a second via plug between one of the plurality of second conductive pads and one of the plurality of second bonding pads (Huang, V12, Fig. 45, para [0079] describes bonding vias V12 between second conductive pad 118c and each of the one of the plurality of second bonding pad BP14 wherein upon combining Huang with Chen, each of the others of the plurality of second bonding pads 124B and second conductive pads 224B of Chen would be separated from each other by the bonding vias V12 of Huang).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chien-Yuan Huang et al. (US 2023/0025094 A1; hereinafter “Huang”) in view of Hsien-Wei Chen et al. (US 2020/0381379 A1; hereinafter “Chen II”).
Regarding Claim 11, Huang teaches a semiconductor chip stacking structure comprising:
a first semiconductor chip die (200, Fig. 45, para [0029] describes a semiconductor die 200); and
a second semiconductor chip die bonded to the first semiconductor chip die (100, Fig. 45, para [0029] describes a second semiconductor die 100 bonded to the first semiconductor die 200),
wherein each of the first semiconductor chip die (200) and the second semiconductor chip die (100) comprises:
an interconnect structure on a substrate (106 and 206, Fig. 45, para [0015] describes an interconnect structure 106 for the second die 100 and para [0030] describes a similar interconnect structure 206 for the first semiconductor die 200);
an interlayer dielectric layer on the interconnect structure (120, 124, 220 and 224, Fig. 45, para [0020] describes a passivation layer 120 that may be comprised of silicon nitride and para [0025] describes a dielectric layer 124 that may be comprised of silicon nitride wherein the dielectric layers 120 and 124 comprised of a same material form an interlayer dielectric layer and para [0030] and para [0038] describe a similar interlayer dielectric layer 220 and 224 for the first semiconductor die 200);
at least one first conductive pad within the interlayer dielectric layer and electrically coupled with the interconnect structure (118b and 218b, Fig. 37, para [0019] describes die pad 118b within the interlayer dielectric layer 120 and 124 and electrically connected to the interconnect structure 106 and para [0030] describes a similar conductive pad 218b for the first semiconductor die 200);
at least one second conductive pad within the interlayer dielectric layer and electrically decoupled from the interconnect structure (118c and 218c, Fig. 45, para [0076] describes a dummy die pads 118c within the interlayer dielectric layer 120 and 124 and electrically insulated from the interconnect structure 106 and para [0076] describes a similar second conductive pad 218c for the first semiconductor die 200);
at least one first via plug within the interlayer dielectric layer and electrically coupled with the interconnect structure (V11 and V21, Fig. 45, para [0076] describes a conductive via V11 within the interlayer dielectric layer 120 and 124 and para [0076] describes a similar via plug V21 for the first semiconductor die 200); and
a first bonding structure on the interlayer dielectric layer (125, BP11-BP14, Fig. 45, para [0027] describes a bonding structure for the second semiconductor die 100 and para [0041] describes a similar bonding structure for the first semiconductor die 200), the first bonding structure comprises:
a first dielectric layer (125 and 225, Fig. 45, para [0027] describes a bonding dielectric layer 125 and para [0040] describes a similar bonding dielectric layer for the first semiconductor die 200);
at least one first bonding pad passing through the first dielectric layer (BP11 and BP21, Fig. 45, para [0028] describes an active bonding pad BP11 passing through the first dielectric layer 125 and para [0040] describes a similar first bonding pad V21 passing through the first dielectric layer 225 for the first semiconductor die 200) and the second dielectric layer; and
a plurality of second bonding pads passing through the first dielectric layer (BP12, BP13, BP14, BP22, BP23 and BP24, Fig. 45, para [0028] describes dummy bonding pads BP12, BP13 and BP14 passing through the first dielectric layer 125 and para [0041] describes similar dummy bonding pads BP22, BP23 and BP24 passing through the first dielectric 225 of the first semiconductor die 200) and the second dielectric layer,
wherein the at least one first bonding pad is electrically coupled with the at least one first via plug (BP11 and BP21, Fig. 45, para [0057] describes wherein active bonding pad BP11 is electrically connected to the at least one first via V11 and para [0074] describes a similar active bonding pad BP21 electrically connected to the at least one first via V21 of the first semiconductor die 200),
wherein some of the plurality of second bonding pads are spaced apart from the at least one first conductive pad in a vertical direction (BP12, BP13, BP22 and BP23, Fig. 45, para [0028] describes the dummy bonding pads BP12 and BP13 which can be seen spaced apart from the first conductive pad 118b in a vertical direction in Fig. 45 and para [0074] describes similar dummy bonding pads BP22 and BP23 which can be seen spaced apart from the first conductive pad 218b of the first semiconductor die 200 in a vertical direction in Fig. 45), and
wherein others of the plurality of second bonding pads are spaced apart from the at least one second conductive pad in the vertical direction (BP14 and BP24, Fig. 45, para [0028] describes the dummy bonding pad BP14 which can be seen spaced apart from the second conductive pad 118c in a vertical direction in Fig. 45 and para [0074] describes a similar dummy bonding pad BP24 which can be seen spaced apart from the second conductive pad 218c of the first semiconductor die 200 in a vertical direction in Fig. 45).
Huang fails to explicitly disclose a second dielectric layer on the first dielectric layer; at least one first bonding pad passing through the first dielectric layer and the second dielectric layer; and a plurality of second bonding pads passing through the first dielectric layer and the second dielectric layer.
However, Chen II teaches a similar semiconductor chip stacking structure, comprising:
a second dielectric layer (130b, Fig. 3D, para [0030] describes a blocking layer 130b comprised of a dielectric material) on the first dielectric layer (130c, Fig. 3D, para [0030] describes a bonding dielectric material 130c wherein second dielectric layer 130b is on a bottom surface of the first dielectric layer 130c);
at least one first bonding pad passing through the first dielectric layer and the second dielectric layer (136, Fig. 3D, para [0033] describes a first metal feature 136 of a bonding metal layer 132 which passes through first dielectric layer 130c and second dielectric layer 130b); and
a plurality of second bonding pads passing through the first dielectric layer and the second dielectric layer (138, Fig. 3D, para [0033] describes a dummy metal feature 138 in the bonding material layers 130 which passes through first dielectric layer 130c and second dielectric layer 130b wherein upon combining Huang with Chen II, the dummy metal feature 138 of Chen II would be comprised in the plurality of second bonding pads BP12, BP13, BP22 and BP23 of Huang).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Huang with Chen II to further disclose a semiconductor chip stacking structure comprising a second dielectric layer on a first dielectric layer in order to provide the advantage of providing a blocking layer which may act as an etch stopping layer for the overlying bonding dielectric layer to prevent over etching in underlying layers of the semiconductor device (Chen II, para [0040]).
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Chien-Yuan Huang et al. (US 2023/0025094 A1; hereinafter “Huang”) in view of Hsien-Wei Chen et al. (US 2020/0381379 A1; hereinafter “Chen II”) and in further view of Min-Feng Kao et al. (US 2021/0391302 A1; hereinafter “Kao”).
Regarding Claim 14, the combination of Huang and Chen II discloses all the limitations of claim 11.
Huang and Chen II fail to explicitly disclose the semiconductor chip stacking structure of claim 11, wherein the first semiconductor chip die further comprises: a second bonding structure on a bottom surface of the substrate of the first semiconductor chip die and comprising at least one third bonding pad, a plurality of fourth bonding pads, and a third dielectric layer; and at least one through-silicon via (TSV) in the substrate of the first semiconductor chip die and in contact with the at least one third bonding pad.
However, Kao teaches a similar semiconductor chip stacking structure, wherein the first semiconductor chip die (104, Fig. 1, para [0014] describes an IC die 104) further comprises:
a second bonding structure on a bottom surface of the substrate of the first semiconductor chip die (126, Fig. 1, para [0014] describes an additional bonding structure 126) and comprising at least one third bonding pad (TP, annotated Fig. 1, para [0014] describes bonding wire layers 122 wherein second bonding structure 126 comprises third bonding pads TP comprised of bonding wire layers 122), a plurality of fourth bonding pads (FP, annotated Fig. 1, para [0014] describes bonding wire layers 122 wherein second bonding structure 126 comprises fourth bonding pads FP comprised of bonding wire layers 122), and a third dielectric layer (TDL, annotated Fig. 1, para [0014] describes a bonding dielectric layer 124 wherein second bonding structure 126 comprises a third dielectric layer TDL comprised of a bonding dielectric structure 124); and
at least one through-silicon via (TSV) in the substrate of the first semiconductor chip die and in contact with the at least one third bonding pad (132, annotated Fig. 1, para [0015] describes a TSV in the substrate 108b of the first semiconductor chip die 104 which is in contact with third bonding pad TP through a bonding via 123).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Huang and Chen II with Kao to further disclose a semiconductor chip stacking structure comprising a second bonding structure on a bottom surface of the substrate of the first semiconductor chip die and comprising at least one third bonding pad, a plurality of fourth bonding pads, and a third dielectric layer, and a through-silicon via in order to provide the advantage of enabling an additional bonding layer to be used to help dissipate heat built up in a plurality of semiconductor dies wherein heat buildup may cause the negative effects of deterioration in physical and electrical characteristics of a device (Kao, para [0017]) and to further provide the well-known advantage of enabling a semiconductor die stack to be able to bond additional semiconductor dies on either surface of a device increasing device integration possibilities.
Regarding Claim 15, the combination of Huang, Chen II and Kao discloses the semiconductor chip stacking structure of claim 14, wherein the at least one third bonding pad (Kao, TP, annotated Fig. 1, para [0014] describes bonding wire layers 122 wherein second bonding structure 126 comprises third bonding pads TP comprised of bonding wire layers 122) is directly bonded to the at least one first bonding pad of the second semiconductor chip die (Kao, FBP, annotated Fig. 1, para [0014] describes bonding wire layers 122 wherein a first bonding structure 120a of a second semiconductor die 102 comprises a first bonding pad FBP connected to a conductive pad of interconnect layers 112a wherein the first bonding pad FBP is directly bonded to the third bonding pad TP), and the plurality of fourth bonding pads is directly bonded to the plurality of second bonding pads of the second semiconductor chip die (Kao, SBP and 102, annotated Fig. 1, para [0014] describes bonding wire layers 122 wherein the first bonding structure 120a of the second semiconductor die 102 comprises second bonding pads SBP disconnected from interconnect layers 112a wherein the second bonding pads SBP are directly bonded to the fourth bonding pads FP).
Regarding Claim 16, the combination of Huang, Chen II and Kao discloses the semiconductor chip stacking structure of claim 14, wherein the third dielectric layer is directly bonded to the second dielectric layer of the second semiconductor chip die (Kao, 120A and 124, annotated Fig. 1A, para [0014] describes a bonding dielectric layer 124 wherein first bonding structure 120a comprises a second dielectric layer comprised of a bonding dielectric structure 124 and the second dielectric layer of 120a and the third dielectric layer TDL of 126 are directly bonded).
Conclusion
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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