Prosecution Insights
Last updated: April 19, 2026
Application No. 18/385,296

Superconductor-Based Transistor

Non-Final OA §101§102§112§DP
Filed
Oct 30, 2023
Examiner
LIU, BENJAMIN T
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Psiquantum Corp.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
3y 1m
To Grant
87%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allow Rate
511 granted / 687 resolved
+6.4% vs TC avg
Moderate +13% lift
Without
With
+12.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
48 currently pending
Career history
735
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
56.9%
+16.9% vs TC avg
§102
32.8%
-7.2% vs TC avg
§112
9.2%
-30.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 687 resolved cases

Office Action

§101 §102 §112 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957). A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101. Claims 15-17 are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 15-17 of prior U.S. Patent No. 11805709. This is a statutory double patenting rejection. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 2-14 and 18-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In claim 2 ll. 8, it is indefinite as to whether the limitation “first region of to the semiconductor wire” refers to first region of the semiconductor wire or something else. For purposes of examination the first interpretation will be used. Claims 3-14 and 18-23 do not clear up the deficiencies of claim 2. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 2-4, 7, 9, 11, 14, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morrow et al. (US 2020/0152750) (“Morrow”). With regard to claim 2, fig. 10A-10C of Morrow discloses a transistor 150, comprising: a superconducting wire (“gate electrode 142 may include a superconducting material”, par [0045]) on a first layer 142 of the transistor 150; a semiconducting wire (102, 122) on a second layer 102 of the transistor 150, the semiconducting wire (102, 122) comprising a first region (102 under 142) adjacent to the superconducting wire 142 and secondary regions 122 neighboring the first region 102, the first region 102 being narrower than the secondary regions 122; a source (left 122 in fig. 10B) coupled to one of the secondary regions 122 of the semiconducting wire (102, 122); and a drain (right 122 in fig. 10B) coupled to another of the secondary regions 122 of the semiconducting wire (102, 122), the semiconducting wire (102, 122) configured to transfer current from the source (left 122, fig. 10B) through the first region 102 of to the semiconducting wire (102, 122) and to the drain (122, fig. 10B). With regard to claim 3, figs. 10A-10C of Morrow discloses that the superconducting wire 142 comprises a gate (“gate electrode 142”, par [0043]) of the transistor 150 and the semiconducting wire (102, 122) comprises the source (left 122, fig. 10B) and drain (right 122, fig. 10B) of the transistor 150. With regard to claim 4, figs. 10A-10C of Morrow discloses that a superconducting threshold temperature of the superconducting wire 142 is adjacent to a semiconducting threshold temperature of the semiconducting wire (102, 122).\ With regard to claim 7, figs. 10A-10C of Morrow discloses that the semiconducting wire includes Germanium (“germanium”, par [0031]). With regard to claim 9, figs. 10A-10C of Morrow discloses that the superconducting wire 142 is perpendicular to the semiconducting wire (102, 122). With regard to claim 11, figs. 10A-10C of Morrow discloses that an electrically-insulating layer 140 is arranged between the superconducting wire 142 and the semiconducting wire (102, 122). With regard to claim 14, figs. 10A-10C of Morrow discloses that the superconducting wire (102, 122) has a temperature that is above a temperature threshold of the superconducting wire (102, 122) when the transistor 150 is in an on state. With regard to claim 18, figs. 10A-10C of Morrow discloses comprising: providing a first wire (102, 122); depositing an electrically-insulating layer 140 over the first wire (102, 122); and forming a second wire 142 on the electrically-insulating layer 140, wherein one of the first wire and the second wire 142 includes a superconducting component (“gate electrode 142 may include a superconducting material”, par [0045]) and another (102, 122) of the first wire and the second wire includes a semiconducting component (“semiconductor body 102”, par [0043]). With regard to claim 20, figs. 10A-10C of Morrow discloses that the first wire (102, 133) includes the semiconducting component (“semiconductor body 102”, par [0043]); and the second wire 142 includes the superconducting component (“gate electrode 142 may include a superconducting material”, par [0045]). Allowable Subject Matter Claims 5-6, 8, 10, 12-13, 19, and 21-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at 571 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Oct 30, 2023
Application Filed
Aug 27, 2024
Response after Non-Final Action
Jan 10, 2026
Non-Final Rejection — §101, §102, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
87%
With Interview (+12.6%)
3y 1m
Median Time to Grant
Low
PTA Risk
Based on 687 resolved cases by this examiner. Grant probability derived from career allow rate.

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