Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawing objections for not showing every feature specified in the claims are withdrawn in view of the amendments to claims 9 and 19 in the response filed on April 14, 2026. The drawing objection for using reference character 420Sw3 to designate both the third sidewall of the second chip stack pad and the third sidewall of the third chip stack pad is withdrawn in view of the corrections to the drawings in the response filed on April 14, 2026.
Specification
The corrections to the specification in the response filed on April 14, 2026 are accepted by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Mehta et al. (US 7,723,833) in view of Zhang (CN 211017055 U). The examiner notes that the citations to paragraphs of Zhang refer to paragraphs of the attached English language translation.
Regarding Claim 1:
Mehta discloses a semiconductor package, comprising:
a substrate (substrate, See fig. 3, ref. no. 202 and col. 5 lines 41-60);
a plurality of substrate pads (bond fingers to the right of the semiconductor chips, See fig. 3, 4B(ii), 4C, ref. no. 203, 208, 209, col. 5 lines 41-60 and col. 6 lines 8-40. The examiner notes that in the cross sectional view of figure 3 two bond fingers are shown to the right of the semiconductor chips.) on an upper surface (top surface of substrate, See fig. 3, ref. no. 202a and col. 5 lines 41-6) of the substrate;
a first semiconductor chip (first semiconductor chip, See fig. 3, ref. no. 208) and a second semiconductor chip (third semiconductor chip, See fig. 3, ref. no. 216) stacked on the substrate in a first direction (the first semiconductor chip and the third semiconductor chip are stacked on the substrate in the vertical direction, See fig. 3, ref.no. 202, 208, 216, and col. 6 lines 16-19), wherein the first semiconductor chip has a first sidewall (the right sidewall of the first semiconductor chip shown in the cross-section view of figure 3, See fig. 3, ref. no. 208) and the second semiconductor chip has a second sidewall (the right sidewall of the third semiconductor chip shown in the cross-section view of figure 3, See fig. 3, ref. no. 216);
a first chip stack pad (a pad is represented in figure 3 by a rectangular block located on an active top surface of the first semiconductor chip and electrically connected to a bond wire, See fig. 3, ref. nos. 208a, 214, and col. 6 line 7-11) on an upper surface (top active surface of the first semiconductor chip, See fig. 3, ref. no. 208a and col. 5 lines 61-65) of the first semiconductor chip;
a second chip stack pad (a pad is represented in figure 3 by a rectangular block located on an active top surface of the third semiconductor chip and electrically connected to a bond wire, See fig. 3, ref. nos. 216a, 214, and col. 6 lines 19-27) on an upper surface (top active surface of the third semiconductor chip, See fig. 3, ref. no. 216a and col. 6 lines 19-27) of the second semiconductor chip, a first center of an upper surface of the first chip stack pad and a second center of an upper surface of the second chip stack pad being misaligned in the first direction (the center of the top line of the pad represented by a rectangular block on the first semiconductor chip and the center of the top line of the pad represented by a rectangular block on the third semiconductor chip cannot be intersected by a straight line in the vertical direction, See fig. 3, ref. nos. 208 and 216) and;
a first wire (bond wire, See fig. 3, ref. no. 214 and col. 6 lines 7-11) connecting the first chip stack pad with a corresponding one (right bond finger located closest to the first semiconductor chip, See fig. 3, ref. no. 208) of the plurality of the substrate pads; and
a second wire (bond wire, See fig. 3, ref. no. 214 and col. 6 lines 19-27) connecting the second chip stack pad with a corresponding one (right bond finger located furthest from the third semiconductor chip, See fig. 3, ref. no. 216) of the plurality of substrate pads.
Mehta does not disclose the first sidewall of the first semiconductor chip and the second sidewall of the second semiconductor chip being planar along the first direction an being coplanar with each other.
Zhang discloses the first sidewall (right sidewall of second layer chip, See fig. 1. ref. no. 2 and paragraph 17) of the first semiconductor chip and the second sidewall (right sidewall of third layer chip See fig. 1, ref. no. 3 and paragraph 17) of the second semiconductor chip being planar along the first direction an being coplanar with each other (the right sidewall of the second layer chip and the right sidewall of the third layer chip are vertically aligned, See fig. 1, ref. nos. 2, 3, and paragraph 17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Mehta to replace the third semiconductor chip with a semiconductor chip that has the same size as the first semiconductor and is vertically aligned with the first semiconductor chip such as that taught by Zhang in order to simplify the design of the semiconductor package by reducing the number of different sized semiconductor chips included in the semiconductor package.
Regarding Claim 2:
Mehta discloses wherein the first center is spaced apart from the second center in a second direction intersecting the first direction (the center of the top line of the pad represented by a rectangular block on the first semiconductor chip is located to the left of the center of the top line of the pad represented by a rectangular block on the third semiconductor chip in the horizontal direction, See fig. 3, ref. nos. 208 and 216).
Regarding Claims 4-5:
Mehta discloses wherein at least a portion of the first chip stack pad overlaps the second chip stack pad in the first direction (the pad represented by a rectangular block on the first semiconductor chip partially overlaps the pad represented by a rectangular block on the third semiconductor chip in the vertical direction, See fig. 3, ref. nos. 208 and 216).
Regarding Claim 7:
Mehta discloses a bonding layer (adhesive layer, See fig. 3 ref. no. 209 and col. 6 lines 17-19) between the first semiconductor chip and the second semiconductor chip, the bonding layer bonding the first semiconductor chip to the second semiconductor chip (the adhesive layer provides adhesion between the first semiconductor chip and the third semiconductor chip, See col. 4 line31-39 and col. 5 42-46).
Regarding Claim 8:
Mehta discloses wherein the bonding layer covers the first chip stack pad (adhesive layer, See fig. 3 ref. no. 209).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Mehta et al. (US 7,723,833) in view of Zhang (CN 211017055 U) further in view of Liao et al. (US 2011/0316164).
Regarding Claim 3:
The above stated combination of Mehta and Zhang discloses the above stated semiconductor package. Mehta further discloses wherein the first center is spaced part from the second center in a second direction and the first direction intersects the second direction (the center of the top line of the pad represented by a rectangular block on the first semiconductor chip is located to the left of the center of the top line of the pad represented by a rectangular block on the third semiconductor chip in the horizontal direction, See fig. 3, ref. nos. 208 and 216. The examiner notes that the vertical direction and the horizontal direction in the cross-section view shown in figure 3 intersect. The examiner further notes that the vertical direction is understood to be along the z-axis and the horizontal direction is understood to be along the x-axis.)
The above stated combination of Mehta and Zhang does not disclose wherein the first center is spaced apart from the second center in a third direction and wherein the first direction, the second direction, and the third direction intersect one another.
Liao discloses wherein the first center is spaced apart from the second center in a third direction (centers of die bond pads on the lower die and the centers of the die bond pads on the upper die are staggered in along the y-axis, See fig. 13, ref. no. 102a, 102b, 104a, 104b, and paragraphs 47-48) and wherein the first direction, the second direction, and the third direction intersect one another (The examiner notes that the x-axis, the y-axis, and the z-axis intersect one another).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Mehta and Zhang to include wherein the first center is spaced apart from the second center in a third direction and wherein the first direction, the second direction, and the third direction intersect one another as taught by Liao to provide convenient access to the pads on each of the semiconductor chips.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Mehta et al. (US 7,723,833) in view of Zhang (CN 211017055 U) further in view of Lee et al. (US 2012/0115277).
Regarding Claim 6:
The above stated combination of Mehta and Zhang discloses the above stated semiconductor package.
The above stated combination of Mehta and Zhang does not disclose wherein a spaced distance between the first center and the second center is 10µm or more.
Lee discloses a multiple-chip package with dielectric layer having a thickness of 10 um located between chips (See fig. 9, ref. nos. 250, 261, 300, paragraphs and 33-35 and 41-42).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Mehta and Zhang to include a dielectric layer having a thickness of 10 µm disposed between the back surface of the third semiconductor chip and the bonding wire as taught by Lee in order to electrically isolate the bonding wires from the third semiconductor chip. (See Lee paragraph 33) (The examiner notes that including the dielectric layer having a thickness of 10 µm in semiconductor package of Mehta will space apart the centers of the pads on the first semiconductor chip and the third semiconductor chip by at least 10 µm in the vertical direction.)
Allowable Subject Matter
Claims 9-13 and 15 are allowable.
The following is an examiner’s statement of reasons of allowance: the most relevant reference of record Zhang (CN 211017055 U) discloses a semiconductor package, comprising: a substrate (substrate, See fig. 1, ref. no. 5 and paragraph 17); a first semiconductor chip (first layer chip, See fig. 1, ref. no. 1 and paragraph 17), a second semiconductor chip (second layer chip, See fig. 1, ref. no. 2 and paragraph 17), and a third semiconductor chip (third layer chip, See fig. 1, ref. no. 3 and paragraph 17) sequentially stacked on the substrate in a first direction (the first layer chip, the second layer chip, and the third layer chip are stacked in the vertical direction, See fig. 1, ref. nos. 1, 2, 3), the second semiconductor chip exposing at least a portion of an upper surface of the first semiconductor chip (the second layer chip exposes a portion of the upper surface of the first layer chip, See fig. 1, ref. nos. 1, 2), and the third semiconductor chip not exposing an upper surface of the second semiconductor chip (the second layer chip and the third layer chip are vertically aligned, See fig. 1, ref. nos. 2, 3, and paragraph 17); a first chip stack pad (a pad is represented in figure 1 by a rectangular block located on the top surface of the first layer chip and electrically connected to a gold wire, See fig. 1, ref. no. 1 and paragraph 17) on the upper surface of the first semiconductor chip, the first chip stack pad and the second semiconductor chip having a non-overlapping relationship in the first direction (the pad on the upper surface of the first layer chip and the second layer chip do not overlap, See fig. 1, ref. nos. 1 and 2); a second chip stack pad (a pad is represented in figure 1 by a rectangular block located on the top surface of the second layer chip and electrically connected to a gold wire, See fig. 1, ref. no. 1 and paragraph 17) on the upper surface of the second semiconductor chip; a third chip stack pad (a pad is represented in figure 1 by a rectangular block located on the top surface of the third layer chip and electrically connected to a gold wire, See fig. 1, ref. no. 1 and paragraph 17) on an upper surface of the third semiconductor chip, a first center of an upper surface of the second chip stack pad and a second center of an upper surface of the third chip stack pad being spaced apart from each other in a second direction crossing the first direction (the center of the top line of the pad represented by the rectangular block on the second layer chip is located to the left of the center of the top line of the pad represented by the rectangular block on the third layer chip in the horizontal direction, See fig. 1, ref. nos. 2, 3); wherein at least a portion of the second chip stack pad overlaps the third chip stack pad in the first direction (the pad represented in figure 1 by a rectangular block located on the top surface of the second layer chip overlaps the pad represented in figure 1 by a rectangular block located on the top surface of the second layer chip, See fig. 1, ref. nos. 2,3 and paragraph 17).
Zhang does not disclose a first wire extended from the second chip stack pad to the first chip stack pad; and a second wire extended from the third chip stack pad to the first chip stack pad. Additionally, the prior art also fails to provide other relevant disclosures which are properly combinable with Zhang to teach and/or suggest these limitation of claim 9. Therefore, independent claim 9 and claim 10-13 and 15 that depend therefrom are allowable.
Claims 16-20 are allowable for the reasons stated in the Office action of January 14, 2026.
Response to Arguments
Applicant’s arguments with respect to claims 1-8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The examiner notes that Mehta is not relied on for teaching first and second semiconductor chips having sidewalls that are vertically aligned with each other.
The examiner notes that applicant’s arguments filed April 14, 2026 with respect to claims 9-13 and 15 are directed toward references other than Zhang (CN 211017055 U) and that claims 9-13 and 15 are allowable for the reasons stated in paragraph 8 which refers to Zhang.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899
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