Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 31, 2023 was filed before the mailing of a first Office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Claim 9 recites “a second wire extended from the third chip stack pad to the second chip stack pad,” on page 27 lines 9-10, this feature is not shown in the drawings. Therefore, this feature must be shown or canceled from the claim. Claim 19 recites “ wherein each of the plurality of second chip stack pads and the plurality of third chip stack pads overlaps the fourth semiconductor chip in the first direction,” on page 30 lines 2-3, this feature is not shown in the drawings. Therefore, this feature must be shown or canceled from the claim. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “420SW3” has been used to designate both the third sidewall of the second chip stack pad and the third sidewall of the third chip stack pad. Reference character 430SW3 is understood to refer to the third sidewall of the third chip stack pad. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The disclosure is objected to because of the following informalities: the specification contains the following typographical errors; on page 8 paragraph 34, “a sidewall 330W of the third semiconductor chip 330,” the reference character 330SW is understood to refer to the sidewall of the third semiconductor chip and on page 24 paragraph 91 “overlappoing semiconductor chips,” this is understood to be overlapping semiconductor chips.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-5, and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mehta et al. (US 7,723,833).
Regarding Claim 1:
Mehta discloses a semiconductor package, comprising:
a substrate (substrate, See fig. 3, ref. no. 202 and col. 5 lines 41-60);
a substrate pad (bond fingers, See fig. 3, 4B(ii), 4C, ref. no. 203, col. 5 lines 41-60 and col. 6 lines 8-40) on an upper surface (top surface of substrate, See fig. 3, ref. no. 202a and col. 5 lines 41-6) of the substrate;
a first semiconductor chip (first semiconductor chip, See fig. 3, ref. no. 208) and a second semiconductor chip (third semiconductor chip, See fig. 3, ref. no. 216) stacked on the substrate in a first direction (the first semiconductor chip and the third semiconductor chip are stacked on the substrate in the vertical direction, See fig. 3, ref.no. 202, 208, 216, and col. 6 lines 16-19), a sidewall of the first semiconductor chip and a sidewall of the second semiconductor chip being coplanar (a sidewall of the first semiconductor chip a sidewall of the second semiconductors are located in the plane shown in the cross-section view shown in figure 3, See fig. 3, ref. nos. 208, 216);
a first chip stack pad (a pad is represented in figure 3 by a rectangular block located on an active top surface of the first semiconductor chip and electrically connected to a bond wire, See fig. 3, ref. nos. 208a, 214, and col. 6 line 7-11) on an upper surface (top active surface of the first semiconductor chip, See fig. 3, ref. no. 208a and col. 5 lines 61-65) of the first semiconductor chip;
a second chip stack pad (a pad is represented in figure 3 by a rectangular block located on an active top surface of the third semiconductor chip and electrically connected to a bond wire, See fig. 3, ref. nos. 216a, 214, and col. 6 lines 19-27) on an upper surface (top active surface of the third semiconductor chip, See fig. 3, ref. no. 216a and col. 6 lines 19-27) of the second semiconductor chip, a first center of an upper surface of the first chip stack pad and a second center of an upper surface of the second chip stack pad being misaligned in the first direction (the center of the top line of the pad represented by a rectangular block on the first semiconductor chip and the center of the top line of the pad represented by a rectangular block on the third semiconductor chip cannot be intersected by a straight line in the vertical direction, See fig. 3, ref. nos. 208 and 216) and;
a first wire (bond wire, See fig. 3, ref. no. 214 and col. 6 lines 7-11) connecting the first chip stack pad with the substrate pad; and
a second wire (bond wire, See fig. 3, ref. no. 214 and col. 6 lines 19-27) connecting the second chip stack pad with the substrate pad.
Regarding Claim 2:
Mehta discloses wherein the first center is spaced apart from the second center in a second direction intersecting the first direction (the center of the top line of the pad represented by a rectangular block on the first semiconductor chip is located to the left of the center of the top line of the pad represented by a rectangular block on the third semiconductor chip in the horizontal direction, See fig. 3, ref. nos. 208 and 216).
Regarding Claims 4-5:
Mehta discloses wherein at least a portion of the first chip stack pad overlaps the second chip stack pad in the first direction (the pad represented by a rectangular block on the first semiconductor chip partially overlaps the pad represented by a rectangular block on the third semiconductor chip in the vertical direction, See fig. 3, ref. nos. 208 and 216).
Regarding Claim 7:
Mehta discloses a bonding layer (adhesive layer, See fig. 3 ref. no. 209 and col. 6 lines 17-19) between the first semiconductor chip and the second semiconductor chip, the bonding layer bonding the first semiconductor chip to the second semiconductor chip (the adhesive layer provides adhesion between the first semiconductor chip and the third semiconductor chip, See col. 4 line31-39 and col. 5 42-46).
Regarding Claim 8:
Mehta discloses wherein the bonding layer covers the first chip stack pad (adhesive layer, See fig. 3 ref. no. 209).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Mehta et al. (US 7,723,833) in view of Liao et al. (US 2011/0316164).
Regarding Claim 3:
Mehta discloses the above stated semiconductor package. Mehta further discloses wherein the first center is spaced part from the second center in a second direction and the first direction intersects the second direction (the center of the top line of the pad represented by a rectangular block on the first semiconductor chip is located to the left of the center of the top line of the pad represented by a rectangular block on the third semiconductor chip in the horizontal direction, See fig. 3, ref. nos. 208 and 216. The examiner notes that the vertical direction and the horizontal direction in the cross-section view shown in figure 3 intersect. The examiner further notes that the vertical direction is understood to be along the z-axis and the horizontal direction is understood to be along the x-axis.)
Mehta does not disclose wherein the first center is spaced apart from the second center in a third direction and wherein the first direction, the second direction, and the third direction intersect one another.
Liao discloses wherein the first center is spaced apart from the second center in a third direction (centers of die bond pads on the lower die and the centers of the die bond pads on the upper die are staggered in along the y-axis, See fig. 13, ref. no. 102a, 102b, 104a, 104b, and paragraphs 47-48) and wherein the first direction, the second direction, and the third direction intersect one another (The examiner notes that the x-axis, the y-axis, and the z-axis intersect one another).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Mehta to include wherein the first center is spaced apart from the second center in a third direction and wherein the first direction, the second direction, and the third direction intersect one another as taught by Liao to provide convenient access to the pads on each of the semiconductor chips.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Mehta et al. (US 7,723,833) in view of Lee et al. (US 2012/0115277).
Regarding Claim 6:
Mehta discloses the above stated semiconductor package.
Mehta does not disclose wherein a spaced distance between the first center and the second center is 10µm or more.
Lee discloses a multiple-chip package with dielectric layer having a thickness of 10 um located between chips (See fig. 9, ref. nos. 250, 261, 300, paragraphs and 33-35 and 41-42).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Mehta to include a dielectric layer having a thickness of 10 µm disposed between the back surface of the third semiconductor chip and the bonding wire as taught by Lee in order to electrically isolate the bonding wires from the third semiconductor chip. (See Lee paragraph 33) (The examiner notes that including the dielectric layer having a thickness of 10 µm in semiconductor package of Mehta will space apart the centers of the pads on the first semiconductor chip and the third semiconductor chip by at least 10 µm in the vertical direction.)
Claims 9-11 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Mehta et al. (US 7,723,833) in view of Park (US 2016/0071810) further in view of Lee et al. (US 2012/0115277).
Regarding Claim 9:
Mehta discloses a semiconductor package, comprising:
a substrate (substrate, See fig. 3, ref. no. 202 and col. 5 lines 41-60);
a second semiconductor chip (first semiconductor chip, See fig. 3, ref. no. 208), and a third semiconductor chip (third semiconductor chip, See fig. 3, ref. no. 216) sequentially stacked on the substrate in a first direction (the first semiconductor chip and the third semiconductor chip are stacked on the substrate in the vertical direction, See fig. 3, ref.no. 202, 208, 216, and col. 6 lines 16-19),
a second chip stack pad (a pad is represented in figure 3 by a rectangular block located on an active top surface of the third semiconductor chip and electrically connected to a bond wire, See fig. 3, ref. nos. 216a, 214, and col. 6 lines 19-27) on the upper surface (top active surface of the third semiconductor chip, See fig. 3, ref. no. 216a and col. 6 lines 19-27) of the second semiconductor chip;
a third chip stack pad (a pad is represented in figure 3 by a rectangular block located on an active top surface of the third semiconductor chip and electrically connected to a bond wire, See fig. 3, ref. nos. 216a, 214, and col. 6 lines 19-27) on an upper surface (top active surface of the third semiconductor chip, See fig. 3, ref. no. 216a and col. 6 lines 19-27) of the third semiconductor chip, a first center of an upper surface of the second chip stack pad and a second center of an upper surface of the third chip stack pad being spaced apart from each other in a second direction crossing the first direction (the center of the top line of the pad represented by a rectangular block on the first semiconductor chip is located to the left of the center of the top line of the pad represented by a rectangular block on the third semiconductor chip in the horizontal direction, See fig. 3, ref. nos. 208 and 216);
Mehta does not disclose a first semiconductor chip stacked on the substrate in the first direction, the second semiconductor chip exposing at least a portion of an upper surface of the first semiconductor chip,
and the third semiconductor chip not exposing an upper surface of the second semiconductor chip;
a first chip stack pad on the upper surface of the first semiconductor chip, the first chip stack pad and the second semiconductor chip having a non-overlapping relationship in the first direction;
a first wire extended from the second chip stack pad to the first chip stack pad; and
a second wire extended from the third chip stack pad to the second chip stack pad.
Park discloses a first semiconductor chip (second semiconductor chip, See fig. 1, ref. no. 200a and paragraph 43) stacked on the substrate in the first direction (the second, third, fourth, and fifth semiconductor chips are stacked on the package substrate in the vertical direction, See fig. 2, ref. nos. 10, 200a, 300a, 400a, 500a and paragraph 43), the second semiconductor chip exposing at least a portion of an upper surface of the first semiconductor chip (the second semiconductor chip is staggered from the third semiconductor chip, See fig. 1, ref. nos. 200a and 300a),
a first chip stack pad (bonding pad, See fig. 1, ref. no. 202a and paragraph) on the upper surface of the first semiconductor chip (the bonding pad is on the upper surface on the second semiconductor chip, See fig. 2, ref. nos. 200a and 202a), the first chip stack pad and the second semiconductor chip having a non-overlapping relationship in the first direction (the second semiconductor chip is staggered from the third semiconductor chip such that the third semiconductor chip does not overlap the bonding pad, See fig. 1, ref. nos. 200a, 202a, and 300a);
a first wire (bonding wire connecting the bonding pad of the third semiconductor chip to the bonding pad of the second semiconductor chip, See fig. 2, ref. nos. 200a, 202a, 300a, 302a) extended from the second chip stack pad to the first chip stack pad; and
a second wire (bonding wire connecting the bonding pad of the fourth semiconductor chip to the bonding pad of the third semiconductor chip, See fig. 2, ref. nos. 200a, 202a, 300a, 302a) extended from the third chip stack pad to the second chip stack pad.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Mehta to include a first semiconductor chip stacked on the substrate in the first direction, the second semiconductor chip exposing at least a portion of an upper surface of the first semiconductor chip, a first chip stack pad on the upper surface of the first semiconductor chip, the first chip stack pad and the second semiconductor chip having a non-overlapping relationship in the first direction as taught by Park to increase the functionality of the semiconductor package by increasing the number of semiconductor chips in the semiconductor package.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Mehta and Park to include a first wire extended from the second chip stack pad to the first chip stack pad and a second wire extended from the third chip stack pad to the second chip stack pad as taught by Park in order to simplify the wiring of the semiconductor package by reducing the number of bonding wires connecting to the substrate.
The above stated combination of Mehta and Park discloses the above a semiconductor package.
The above stated combination of Mehta and Park does not disclose the third semiconductor chip not exposing an upper surface of the second semiconductor chip. (The examiner notes that figure 3 of Mehta shows the first and third semiconductor chips having different sizes in the horizontal direction, while figure 4C of Mehta shows the first and third semiconductor chips having the same size.)
Lee discloses the third semiconductor chip not exposing an upper surface of the second semiconductor chip (third chip in the multi-chip package does not expose an upper surface of the second chip in the multi-chip package, See fig. 9, ref. nos. 250, 300 and paragraphs 34 and 41-42).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Mehta and Park to include the third semiconductor chip not exposing an upper surface of the second semiconductor chip as taught by Lee in order to protect a larger section of the bond wire from damage by fully covering the top surface of the first semiconductor chip. (See Mehta col. 4 lines 31-35)
Regarding Claim 10:
The above stated combination of Mehta, Park, and Lee discloses a first bonding layer (third adhesive layer, See Park fig. 1, ref no. 320a and paragraphs 71-72) between the upper surface of the first semiconductor chip and a lower surface of the second semiconductor chip; and a second bonding layer (adhesive layer between the first semiconductor chip and the third semiconductor chip, See Mehta fig. 3, ref. no. 209 and col. 6 lines 17-19) between the upper surface of the second semiconductor chip and a lower surface of the third semiconductor chip, a thickness of the first bonding layer in the first direction being less than a thickness of the second bonding layer in the first direction (the thickness the adhesive layer between the first and third semiconductor chips is greater than the thickness of the adhesive layer between the third and fourth semiconductor chip, thus, Mehta discloses adhesive layers that protect a top active surface and the associated bond wires have a thickness greater than adhesive layer the do not protect the a top active surface and the associated bond wires, See Mehta fig. 3, ref. nos. 208, 209, 216, 218).
Regarding Claim 11:
Mehta discloses wherein at least a portion of the first wire is in the second bond layer (a portion of the bond wire connected to the pad on the third semiconductor chip is in the adhesive layer, See fig. 3, ref. nos. 208 and 214)
Regarding Claim 13:
The above stated combination of Mehta, Park, and Lee discloses the above stated semiconductor package.
The above stated combination of Mehta, Park, and Lee does not disclose wherein a spaced distance between the first center and the second center is 10µm or more.
Lee discloses a multiple-chip package with dielectric layer having a thickness of 10 um located between chips (See fig. 9, ref. nos. 250, 261, 300, paragraphs and 33-35 and 41-42).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Mehta, Park, and Lee to include a dielectric layer having a thickness of 10 µm disposed between the back surface of the third semiconductor chip and the bonding wire as taught by Lee in order to electrically isolate the bonding wires from the third semiconductor chip. (See Lee paragraph 33) (The examiner notes that including the dielectric layer having a thickness of 10 µm in semiconductor package of Mehta will space apart the centers of the pads on the first semiconductor chip and the third semiconductor chip by at least 10 µm in the vertical direction.)
Regarding Claims 14-15:
Mehta discloses wherein at least a portion of the second chip stack pad overlaps the third chip stack pad in the first direction (the pad represented by a rectangular block on the first semiconductor chip partially overlaps the pad represented by a rectangular block on the third semiconductor chip in the vertical direction, See fig. 3, ref. nos. 208 and 216).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Mehta et al. (US 7,723,833) in view of Park (US 2016/0071810) in view of Lee et al. (US 2012/0115277) further in view of Liao et al. (US 2011/0316164).
Regarding Claim 12:
The above stated combination of Mehta, Park, and Lee discloses the above state semiconductor package.
The above stated combination of Mehta, Park, and Lee does not disclose wherein the first center and the second center are spaced apart from each other in a third direction intersecting the second direction.
Liao discloses wherein the first center and the second center are spaced apart from each other in a third direction intersecting the second direction (centers of die bond pads on the lower die and the centers of the die bond pads on the upper die are staggered in along the y-axis, See fig. 13, ref. no. 102a, 102b, 104a, 104b, and paragraphs 47-48. The examiner notes that the x-axis, the y-axis, and the z-axis intersect one another).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Mehta, Park, and Lee to include wherein the first center and the second center are spaced apart from each other in a third direction intersecting the second direction as taught by Liao to provide convenient access to the pads on each of the semiconductor chips.
Allowable Subject Matter
Claims 16-20 are allowable.
The following is an examiner’s statement of reasons of allowance: the disclosures and illustrations of Mehta, Park, Lee, and/or Liao et al. as discussed above fail to teach or suggest the limitations of claims 16-20. Mehta discloses a semiconductor package, comprising: a substrate (substrate, See fig. 3, ref. no. 202 and col. 5 lines 41-60); a second semiconductor chip (first semiconductor chip, See fig. 3, ref. no. 208), a third semiconductor chip (third semiconductor chip, See fig. 3, ref. no. 216), and a fourth semiconductor chip (fourth semiconductor chip, See fig. 3, ref. no. 218) sequentially stacked on the substrate in a first direction (the first semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are stacked on the substrate in the vertical direction, See fig. 3, ref.no. 202, 208, 216, and col. 6 lines 16-19), the fourth semiconductor chip exposing at least a portion of an upper surface of the third semiconductor chip (the fourth semiconductor chip and the third semiconductor chip are staggered, See fig. 3, ref. nos. 216 and 218), and the second and third semiconductor chips having sidewalls that are coplanar with each other (a sidewall of the first semiconductor chip a sidewall of the second semiconductors are located in the plane shown in the cross-section view shown in figure 3, See fig. 3, ref. nos. 208, 216) and a second bonding layer (adhesive layer between the first semiconductor chip and the third semiconductor chip, See fig. 3, ref. no. 209 and col. 6 lines 17-19) between the upper surface of the second semiconductor chip and a lower surface of the third semiconductor chip, a thickness of the first bonding layer in the first direction being less than a thickness of the second bonding layer in the first direction (the thickness of the adhesive layer between the first and third semiconductor chips is greater than the thickness of the adhesive layer between the third and fourth semiconductor chip, thus, Mehta discloses adhesive layers that protect a top active surface and the associated bond wires have a thickness greater than adhesive layer they do not protect the a top active surface and the associated bond wires, See fig. 3, ref. nos. 208, 209, 216, 218). Mehta does not disclose a first semiconductor chip stacked on the substrate in the first direction, the second semiconductor chip exposing at least a portion of an upper surface of the first semiconductor chip, a plurality of first chip stack pads on the upper surface of the first semiconductor chip, the plurality of first chip stack pads having a non-overlapping relationship with the second semiconductor chip in the first direction and being aligned in a second direction intersecting the first direction, a plurality of second chip stack pads on an upper surface of the second semiconductor chip and aligned in the second direction, a plurality of third chip stack pads on the upper surface of the third semiconductor chip and aligned in the second direction, each of the plurality of third chip stack pads corresponding to each of the plurality of second chip stack pads, a first bonding layer between the upper surface of the first semiconductor chip and a lower surface of the second semiconductor chip, a first wire extended from each of the second chip stack pads to each of the first chip stack pads, and a second wire extended from each of the third chip stack pads to each of the first chip stack pads, wherein a first center of each of the plurality of second chip stack pads and a second center of each of the plurality of third chip stack pads are spaced apart from each other in a third direction crossing the first direction and the second direction, at least a portion of each of the plurality of second chip stack pads overlapping a corresponding one of the plurality of third chip stack pads in the first direction. The prior art also fails to provide other relevant disclosures which are properly combinable with Mehta to teach and/or suggest the limitations of claims 16-20.
Conclusion
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899