DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a first post on the connection pad … the first post being separated from the conductive filler” where a lower filler of the conductive filler is connected to the connection pad, as recited in claim 17, or where a lower filler is electrically connected to the connection pad” as recited in claim 20, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim(s) 20 is/are objected to because of the following informalities:
With respect to claim 20, in line 22 “a third vertical length the solder bump” should read “a third vertical length of the solder bump”, and in line 23, “a fourth vertical length the lower filler” should read “a fourth vertical length of the lower filler.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 3-16 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 3, as currently presented the claim recites the limitation “at least one of the plurality of upper surface contact pads” be in contact with the first post. There is insufficient antecedent basis for this limitation in the claim. For purpose of compact prosecution, “the plurality of upper surface contact pads” will be treated as if it were “a plurality of upper surface contact pads”. Claims 4-16 which either directly or indirectly depend form claim 3 and inherit issues of claim 3 are rejected for similar reasons.
With respect to claim 16, as currently presented the claim requires that “each of the plurality of support posts” that include the support post “is respectively provided at each vertex of the rectangular shape of the semiconductor chip”, “wherein the support post is in a center of the bottom surface of the semiconductor chip”. It is unclear from the claim language, how “the support post” can simultaneously be in one of the vertexes of the rectangular shape semiconductor chip and in a center of the bottom surface of the semiconductor chip. For purpose of compact prosecution, it will be assumed that the semiconductor package includes a plurality of support post, which four of the support posts being provided at each vertex of the rectangular shape of the semiconductor chip and one of the support post being located in the center of the bottom surface of the semiconductor chip.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon et al. (US 2016/0005707, hereinafter “Kwon”).
Regarding claim 1, Kwon teaches in Figs. 1 and 2A-2B (Fig. 1 shown below) and related text a semiconductor package (500, Fig. 1 and ¶[0070]) comprising:
a redistribution structure (100, Fig. 1 and ¶[0070]);
a semiconductor chip (200, Fig. 1 and ¶[0070]) on the redistribution structure (100, Fig. 1);
a conductive filler (310 (311, 312), Fig. 1 and ¶¶[0069]-[0070]) between the redistribution structure (100, Fig. 1) and the semiconductor chip (200, Fig. 1) and electrically connecting the redistribution structure to the semiconductor chip (Fig. 1); and
a support post (320 (321, 322) and/or 330 (120, 331), Fig. 1 and ¶¶[0072]-[0082]) between the redistribution structure and the semiconductor chip (Fig. 1), the support post (320, Fig. 1) being spaced apart from the conductive filler (310, Fig. 1), wherein the support post comprises:
a first post (322 or 120, Fig. 1) on a top surface of the redistribution structure (100, Fig. 1); and
a second post (321 or 331, Fig. 1) comprising:
a first end connected to the first post (322, Fig. 1); and
a second end (i.e. upper end of 321, Fig. 1) oriented toward the semiconductor chip (200, Fig. 1) and supporting the semiconductor chip (200, Fig. 1).
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Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2021/0111126, hereinafter “Lin `126”).
Regarding claim 1, Lin `126 teaches in Fig. 1 (shown below) and related text a semiconductor package (100, Fig. 1 and ¶[0016]) comprising:
a redistribution structure (110/150, Fig. 1 and ¶[0016]);
a semiconductor chip (120, Fig. 1 and ¶[0017]) on the redistribution structure (110, 150, Fig. 1);
a conductive filler (120P2/150P2, Fig. 1 and ¶[0025]) between the redistribution structure (110/150, Fig. 1) and the semiconductor chip (120, Fig. 1) and electrically connecting the redistribution structure to the semiconductor chip; and
a support post (120P1/150P1, Fig. 1 and ¶[0025]) between the redistribution structure and the semiconductor chip (Fig. 1), the support post being spaced apart from the conductive filler (120P2/150P2, Fig. 1), wherein the support post comprises:
a first post (150P1, Fig. 1) on a top surface of the redistribution structure (110/150, Fig. 1); and
a second post (120P1, Fig. 1) comprising:
a first end connected to the first post (150P1, Fig. 1); and
a second end (120P1, Fig. 1) oriented toward the semiconductor chip (120, Fig. 1) and supporting the semiconductor chip (120, Fig. 1).
Regarding claim 2 (1), Lin `126 teaches wherein the conductive filler (120P2/150P2, Fig. 1) comprises:
a lower filler (150P2, Fig. 1) connected to the redistribution structure (110/150, Fig. 1); and
a solder bump (¶[0025]) in one end of the lower filler (150P2, Fig. 1) and electrically connecting the semiconductor chip (120, Fig. 1) to the lower filler (150P2, Fig. 1).
Regarding claim 3 (2), Lin `126 teaches wherein the redistribution structure (110/150, Fig. 1) comprises a plurality of upper connection pads (i.e. pads exposed at the top surface of 150, Fig. 1), wherein the plurality of upper connection pads is on a surface (Fig. 1) of the redistribution structure (110/150, Fig. 1) on which the semiconductor chip (120, Fig. 1) is located, and
wherein at least one of the plurality of upper connection pads is in contact with the lower filler (150P2, Fig. 1), and at least one of the plurality of upper surface contact pads is in contact with the first post (150P1, Fig. 1).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon, as applied to claim 1 above, and further in view of Conn et al. (US 7,667,473, hereinafter “Conn”).
Regarding claim 2 (1), teaching of Kwon was discussed above in the rejection of claim 1 and further includes wherein the conductive filler (310, Fig. 1) comprises:
a lower filler (312, Fig. 1) connected to the redistribution structure (100, Fig. 1) and
an upper filler (311, Fig. 1) in one end of the lower filler (312, Fig. 1) and electrically connecting the semiconductor chip (200, Fig. 1) to the lower filler (312, Fig. 1).
Kwon, however, does not explicitly teach that the upper filler is a solder bump. Conn, in a similar field of endeavor, teaches in Figs. 4 and 5, and related text, that a conductive filler, similar to that disclosed Kwon, that includes upper filler and lower filler (512 and 130, Fig. 5), wherein the lower filler (130, Fig. 5) is a solder bump (col. 1 and ll. 50-54), similar to that disclosed by Kwon, and a conductive filler that includes upper filler and lower filler (130 and 410, Fig. 4), wherein the upper filler is a solder bump (130, Fig. 4, col. 1 and ll. 50-54), are art recognized equivalents that could be used interchangeably to connect a semiconductor chip to a substrate, in order to meet specific design requirements.
Thus, since the prior art teaches all of the claimed elements using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the conductive filler disclosed by Kwon, so that the upper filler in one end of the lower filler is a solder bump that electrically connects the semiconductor chip to the lower filler, as disclosed by Conn, as doing so would amount to nothing more than selecting a conductive filler configurations known in the art in order to meet specific design requirements.
Regarding claim 3 (2), the combined teaching of Kwon and Conn discloses wherein the redistribution structure (Kwon, 100, Fig. 1) comprises a plurality of upper connection pads (Kwon, e.g. 112a, 111a, Fig. 1 and ¶[0055]), wherein the plurality of upper connection pads is on a surface of the redistribution structure (Kwon, 100, Fig. 1) on which the semiconductor chip (Kwon, 200, Fig. 1) is located, and
wherein at least one of the plurality of upper connection pads is in contact with the lower filler (Kwon, 312, Fig. 1 as modified by Conn), and at least one of the plurality of upper surface contact pads is in contact with the first post (Kwon, 322, Fig. 1 as modified by Conn).
Regarding claim 4 (3), the combine teaching of Kwon and Conn further discloses
a passivation layer (Kwon, 220, Fig. 1 and ¶[0063]) on a bottom surface of the semiconductor chip (Kwon, 200, Fig. 1) opposing the top surface of the redistribution structure (Kwon, 100, Fig. 1), wherein the second post (Kwon, 322, Fig. 1 as modified by Conn) is insulated from the semiconductor chip (Kwon, 200, Fig. 1) by the passivation layer (Kwon, 220, Fig. 1).
Regarding claim 5 (4), the combine teaching of Kwon and Conn further discloses wherein a first vertical length of the first post (Kwon, 321, Fig. 1 as modified by Conn) is equal to or greater than a second vertical length of the second post (Kwon, 322, Fig. 1 as modified by Conn).
Regarding claim 6 (5), the combine teaching of Kwon and Conn further discloses wherein a ratio of the second vertical length (Kwon, 322, Fig. 1 as modified by Conn and Conn 130, Fig. 4) to the first vertical length (Kwon, 321, Fig. 1 as modified by Conn and Conn, 410, Fig. 4) is at least about 1/5 and no greater than about 1/2 (i.e. the length of the first post disclosed by Conn is at least double of that of the second post 130 which would satisfy the claimed ratio).
Regarding claim 7 (5), the combine teaching of Kwon and Conn discloses wherein a third vertical length of the solder bump (Kwon, 312, Fig. 1 as modified by conn) is equal to the second vertical length (Kwon, 322, Fig. 1 as modified by Conn).
Regarding claim 8 (7), the combine teaching of Kwon and Conn discloses wherein a fourth vertical length of the lower filler (Kwon, 311, Fig. 1 as modified by Conn) is equal to the first vertical length (Kwon, 321, Fig. 1 as modified by Conn).
Claim(s) 9-10 and 12-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon and Conn as applied to claim 8 above, and further in view of Lin et al. (US 2005/0194695, hereinafter “Lin `695”).
Regarding claim 9 (8), the combine teaching of Kwon and Conn was discussed above in the rejection of claim 8. Kwon and Conn, however, do not explicitly teach that a first horizontal width of the first post is equal or greater than a second horizontal width of the second post. Lin `695, however, teaches in Figs. 8A and 8B that a post that includes a first post and a second post, similar to that disclosed by the combined teaching of Kwon and Conn (Lin `695, Fig. 8A), and a first post and second posts with the horizontal widths that are equal (Lin `695, Fig. 8B) are art known equivalents that can be used depending on specific design requirements.
Accordingly, since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the post disclosed by Lin in the embodiment of Fig. 8B that includes a first post and second post having equal horizontal widths, as doing so would amount to nothing more than using a post with a known configuration in order to meet specific design requirements.
Regarding claim 10 (8), the combine teaching of Kwon and Conn was discussed above in the rejection of claim 8. Kwon and Conn, however, do not explicitly teach wherein a horizontal cross-sectional area of the first post is equal or greater than a horizontal cross-sectional area of the second post.
Lin `695, in a similar field of endeavor, teaches in Figs. 8A and 8B that a post that includes a first post and a second post, similar to that disclosed by the combined teaching of Kwon and Conn (Lin `695, Fig. 8A), and a first post and second posts with horizontal cross-sectional areas that are equal (Lin `695, Fig. 8B) are art known equivalents that can be used depending on specific design requirements.
Accordingly, since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the post disclosed by Lin `695 in the embodiment of Fig. 8B that includes a first post and second post having horizontal cross-sectional areas, as doing so would amount to nothing more than using a post with a known configuration in order to meet specific design requirements.
Regarding claim 12 (9), the combine teaching of Kwon, Conn and Lin `695 discloses wherein the first post and the second post comprise the same material (Kwon, ¶¶[0120] and [0123] and Lin `695, ¶¶[0042] and [0044]).
Regarding claim 13 (9), the combine teaching of Kwon, Conn and Lin `695 discloses wherein the first post and the second post comprise copper (Cu) (Kwon, ¶¶[0120] and [0123] and Lin `695, ¶¶[0042] and [0044]).
Regarding claim 14 (9), the combine teaching of Kwon, Conn and Lin `695 discloses wherein the first post (Kwon, 321, Fig. 1) and the lower filler (Kwon, 311, Fig. 1) comprise the same material (Kwon, ¶¶[0120] and [0123]).
Regarding claim 15 (9), the combine teaching of Kwon, Conn and Lin `695 discloses wherein the semiconductor chip has a rectangular shape (Kwon, Figs. 1 and 2B (annotated Fig. 2B shown below)), wherein the semiconductor package comprises a plurality of support posts (Kwon, 320, Fig. 1 and annotated Fig. 2B), including the support post (Kwon, i.e. one of the posts 320, Fig. 1 and annotated Fig. 2B), and wherein the plurality of support posts are respectively provided at three of the vertexes of the rectangular shape of the semiconductor chip (Kwon, 200 in CIA, Fig 1 and annotated Fig. 2B and ¶¶[0142]-[0143]), with one of the support posts provided in the vicinity of the fourth corner of the semiconductor chip (Kwon, annotated Fig. 2B), where it would have been obvious to one of ordinary skill in the art to place the fourth support post of the plurality of support posts disclosed by Kwon at the fourth vertex of the rectangular shape of the semiconductor chip rather than in the vicinity of the corner of the rectangular chip as a matter of design choice.
[AltContent: textbox (center of the bottom surface of the semiconductor chip that includes center support posts)][AltContent: textbox (3rd support post)][AltContent: textbox (2nd support post)][AltContent: ][AltContent: ][AltContent: ][AltContent: rect][AltContent: ][AltContent: textbox (support posts in the vicinity of the vertex of the semiconductor chip)][AltContent: ][AltContent: ][AltContent: ][AltContent: textbox (semiconductor chip)][AltContent: ][AltContent: textbox (support posts in the vertexes of the semiconductor chip)][AltContent: textbox (Annotated Figure)]
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Regarding claim 16 (15), the combine teaching of Kwon, Conn and Lin `695 discloses wherein a support post is in a center of the bottom surface of the semiconductor chip (annotated Fig. 2B).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon and Conn as applied to claim 8 above, and further in view of Chen et al. (US 2021/0111125, hereinafter “Chen”).
Regarding claim 11 (8), the combine teaching of Kwon and Conn was discussed above in the rejection of claim 8. Kwon and Conn, however, do not explicitly teach that a perimeter of the second post is within a perimeter of the first post.
Chen, in a similar field of endeavor, teaches in Fig. 1 and related text that a post similar to that disclosed by Kwon and Conn, can include includes a first post (e.g. 150P1, Fig. 1 and ¶[0023]) and a second post (e.g. 120P1, Fig. 1 and ¶[0023]) formed on the first post wherein a perimeter of the second post (e.g. 120P1, Fig. 1) is within a perimeter of a the first post (150P1, Fig. 1) in order to meet specific connection requirements for the device (¶[0023]).
Thus, since the prior art teaches all of the claimed elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art to replace the post disclosed by Kwon and Conn, with the post disclosed by Chen, so that perimeter of the second post is within a perimeter of the first post in order to meet connection requirements for the device.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 2016/0005707, hereinafter “Kwon”) in view of Conn et al. (US 7,667,473, hereinafter “Conn”), Lin et al. (US 2005/0194695, hereinafter “Lin `695”) and Chen et al. (US 2021/0111125, hereinafter “Chen”).
Regarding claim 17, Kwon teaches in Fig. 9 (Fig. 9 shown below) and related text semiconductor package comprising:
a redistribution structure (100, Fig. 9 and ¶[0070]) comprising a top surface and a connection pad (112, Fig. 9 and ¶[0054]) on the top surface;
a semiconductor chip (200, Fig. 9 and ¶[0052]) on the redistribution structure, the semiconductor chip comprising a bottom surface and a passivation layer (220, Fig. 9 and ¶[0063]) on the bottom surface;
a conductive filler (310, Fig. 9 and ¶[0066]) comprising:
a lower filler (312, Fig. 9 and ¶[0069]) between the redistribution structure (100, Fig. 9) and the semiconductor chip (200, Fig. 9), and connected to the connection pad (112a, Fig. 9); and
an upper filler (311, Fig. 9 and ¶[0069]) at one end of the lower filler and electrically connecting the semiconductor chip to the lower filler (Fig. 9); and
a support post (320, Fig. 9 and ¶[0066]) comprising:
a first post (322, Fig. 9 and ¶[0072]) on the connection pad (112a, Fig. 9) and between the redistribution structure and the semiconductor chip (Fig. 1), the first post being separated from the conductive filler (310, Fig. 1), and
a second post (321, Fig. 1 and ¶[0072]) comprising:
a first end connected to the first post (322, Fig. 1); and
a second end oriented toward the semiconductor chip (200, Fig. 1) and supporting the semiconductor chip (200, Fig. 1),
wherein the second post is insulated from the semiconductor chip (200, Fig. 1) by the passivation layer (220, Fig. 1).
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Kwon, does not explicitly teach that the upper filler is a solder bump and that a first vertical length the first post is equal to or greater than a second vertical length of the second post, and that a perimeter of the second post is within a perimeter of the first post.
To begin with, Conn, in a similar field of endeavor, teaches in Figs. 4 and 5, and related text, that a conductive filler, similar to that disclosed Kwon, that includes upper and lower fillers (512 and 130, Fig. 5) wherein the lower filler (130, Fig. 5) is a solder bump (col. 1 and ll. 50-54), similar to that disclosed by Kwon, and a conductive filler that includes upper and lower fillers (130 and 410, Fig. 4) wherein the upper filler is a solder bump (130, Fig. 4, col. 1 and ll. 50-54) are art recognized equivalents that could be used interchangeably to connect a semiconductor chip to a substrate, in order to meet specific design requirements.
Thus, since the prior art teaches all of the claimed elements using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the conductive filler and the support post disclosed by Kwon, so that the upper filler and the second post include solder bumps that electrically connects the semiconductor chip to the lower filler and support the semiconductor chip, as disclosed by Conn, as doing so would amount to nothing more than selecting a conductive filler and support post configurations known in the art in order to meet specific design requirements. It is noted that when the support post disclosed by Kwon is modified by the teaching of Conn a first vertical length the first post (i.e. lower post) would equal to or greater than a second vertical length of the second post (i.e. upper post).
Moreover, Lin `695 in a similar field of endeavor, teaches in Figs. 8A and 8B, and related text, that a support post, such as that disclosed by the combined teaching of Kwon and Conn (Lin `695, Fig. 8A), and a support post having a first horizontal width of the first post that is equal to a second horizontal width of the second post (Lin `695, Fig. 8B), are art recognized equivalents, and Chen, teaches in Fig. 1 and related text, that support posts having a first horizontal width of the first post (150P2, Fig. 1 and ¶[0023]) that is equal to a second horizontal width of the second post (120P2, Fig. 1 and ¶[0023]), and a first horizontal width of the first post (150P1, Fig. 1 and ¶[0025]) that is greater than a second horizontal width of the second post (120P1, Fig. 1 and ¶[0025]) such that a perimeter of the second post is within a perimeter of the first post, are known equivalents in the art that could be used interchangeably in order to meet specific connection requirements for the device (¶[0023]).
Thus, since the prior art teaches all of the claimed elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art to replace the post disclosed by Kwon and Conn, with the post disclosed by Lin`695 and Chen, so that perimeter of the second post is within a perimeter of the first post, in order to meet connection requirements for the device.
Regarding claim 18 (17), the combined teaching of Kwon, Conn, Lin `695 and Chen discloses wherein the semiconductor chip has a rectangular shape (Kwon, Figs. 2B and 9), wherein the semiconductor package further comprises a plurality of support posts including the support post (Kwon, annotated Fig. 2B), and wherein the plurality of support posts comprises:
a plurality of first support posts located at three of the vertex of the semiconductor chip, one of the support posts located in the vicinity of the fourth vertex of the semiconductor chip, at least one second support post located at a center of the bottom surface of the semiconductor chip, and at least one third post located between at least one of the plurality of first support posts and the at least one second support post, where it would have been obvious to one of ordinary skill in the art to place the fourth support post of the plurality of support posts disclosed by Kwon at the fourth vertex of the rectangular shape of the semiconductor chip rather than in the vicinity of the corner of the rectangular chip as a matter of design choice.
Regarding claim 19 (17), the combined teaching of Kwon, Conn, Lin `695 and Chen discloses wherein the first post, the second post, and the lower filler comprise the same material, and wherein each of the first post, the second post, and the lower filler comprises copper (Cu) (Kwon, ¶¶[0120] and [0123]).
Regarding claim 20, Kwon teaches in Fig. 9 (shown above) and related text a semiconductor package comprising:
a redistribution structure (100, Fig. 9 and ¶[0070]) comprising a top surface and a connection pad (112, Fig. 9 and ¶[0054]) on the top surface;
a semiconductor chip (200, Fig. 9 and ¶[0052]) on the redistribution structure, the semiconductor chip comprising a bottom surface and a passivation layer (220, Fig. 9 and ¶[0063]) on the bottom surface;
a conductive filler (310, Fig. 9 and ¶[0066]) comprising:
a lower filler (312, Fig. 9 and ¶[0069]) between the redistribution structure (100, Fig. 9) and the semiconductor chip (200, Fig. 9), and electrically connected to the connection pad (112a, Fig. 9); and
an upper filler (311, Fig. 9 and ¶[0069]) at one end of the lower filler and electrically connecting the semiconductor chip to the lower filler (Fig. 9); and
a support post (320, Fig. 9 and ¶[0066]) comprising:
a first post (322, Fig. 9 and ¶[0072]) on the connection pad (112a, Fig. 9) and between the redistribution structure and the semiconductor chip (Fig. 1), the first post being separated from the conductive filler (310, Fig. 1), and
a second post (321, Fig. 1 and ¶[0072]) comprising:
a first end connected to the first post (322, Fig. 1); and
a second end oriented toward the semiconductor chip (200, Fig. 1) and supporting the semiconductor chip (200, Fig. 1),
wherein the second post is insulated from the semiconductor chip (200, Fig. 1) by the passivation layer (220, Fig. 1), wherein the first post and the lower filler comprise the same material (Kwon, ¶¶[0120] and [0123]).
Kwon, however, does not explicitly teach that the upper filler is a solder bump. Kwon also does not explicitly teach herein a ratio of a second vertical length of the second post to a first vertical length of the first post is between about 1/5 and about 1/2, wherein a third vertical length the solder bump is equal to the second vertical length, wherein a fourth vertical length the lower filler is equal to the first vertical length,
wherein a first horizontal width the first post is equal to or greater than a second horizontal width of the second post, and wherein a perimeter of the second post is within a perimeter of the first post.
Conn, in a similar field of endeavor, teaches in Figs. 4 and 5, and related text, that a conductive filler and a support post, similar to that disclosed Kwon, that includes upper and lower fillers and upper and lower support posts (Conn, 512 and 130, Fig. 5), wherein the lower filler or lower post (Conn, 130, Fig. 5) is a solder bump (Conn, col. 1 and ll. 50-54), similar to that disclosed by Kwon, and a conductive filler that includes upper and lower fillers (Conn, 130 and 410, Fig. 4), wherein the upper filler is a solder bump, (Conn, 130, Fig. 4, col. 1 and ll. 50-54) are art recognized equivalents that could be used interchangeably to connect a semiconductor chip to a substrate, in order to meet specific design requirements.
Thus, since the prior art teaches all of the claimed elements using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the conductive filler and support post disclosed by Kwon, so that the upper filler in one end of the lower filler and the upper support post are solder bumps, as disclosed by Conn, as doing so would amount to nothing more than selecting a conductive filler configurations known in the art in order to meet specific design requirements. It is noted that when the semiconductor package by Kwon is modified by the teaching of Conn a ratio of the second vertical length of the second post (Kwon, 322, Fig. 1 as modified by Conn and Conn 130, Fig. 4) to a first vertical length of the first post (Kwon, 321, Fig. 1 as modified by Conn and Conn, 410, Fig. 4) would be between about 1/5 and about 1/2 (i.e. the length of the first post disclosed by Conn is at least double of that of the second post 130 which would satisfy the claimed ratio), a third vertical length of the solder bump would be equal to the second vertical length of the second post (Kwon Fig. 9 as modified by Conn) and a fourth vertical length of the lower filler would be equal to the first vertical length (Kwon Fig. 9 as modified by Conn).
Moreover, Lin `695 in a similar field of endeavor, teaches in Figs. 8A and 8B, and related text, that a support post, such as that disclosed by the combined teaching of Kwon and Conn (Lin `695, Fig. 8A), and a support post having a first horizontal width of the first post that is equal to a second horizontal width of the second post (Lin`695, Fig. 8B), are art recognized equivalents, and Chen teaches in Fig. 1 and related text, that support posts having a first horizontal width of the first post (150P2, Fig. 1 and ¶[0023]) that is equal to a second horizontal width of the second post (120P2, Fig. 1 and ¶[0023]) and a first horizontal width of the first post (150P1, Fig. 1 and ¶[0025]) that is greater than a second horizontal width of the second post (120P1, Fig. 1 and ¶[0025]), such that a perimeter of the second post is within a perimeter of the first post, are known equivalents in the art and could be used interchangeably in order to meet specific connection requirements for the device (¶[0023]).
Thus, since the prior art teaches all of the claimed elements using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replace the support post disclosed by the combined teaching of Kwon and Conn, with the post disclosed by Lin `695 and Chen, so that perimeter of the second post is within a perimeter of the first post, as doing so would amount to nothing more than substituting one known element for another known element, in order to meet connection requirements for the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANETA B CIESLEWICZ whose telephone number is 303-297-4232. The examiner can normally be reached M-F 8:30 AM - 2:30 PM.
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/A.B.C/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893