Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12, 15-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bishop et al. [US 2019/0102496 A1] in view of Shi et al. [US 2024/0330738 A1].
Taking claim 1 as exemplary of claims 1, 16 and 20 [paragraph 0107], Bishop et al. teach a method comprising:
displaying, via a Graphical User Interface (GUI) [paragraph 0027 GUI], a first portion of an abstract quantum circuit [paragraph 0061 a first symbol selected by a user, 0068-0069 set of symbols, selected set of symbols, 0074 first interactive element to associate with the selected symbol], wherein the GUI enables a user to view a graphical representation of the abstract quantum circuit, the abstract quantum circuit represents a quantum circuit [paragraphs 0027 and 0057-0058, FIGS. 5-7], the abstract quantum circuit comprises:
one or more input ports, each of which representing an input register [paragraphs 0023, 0027, 0055 it is interpreted that quantum circuits formed by user-selectable symbols representative of operations to realize quantum computing algorithms corresponding to qubits and qubit registers inherently comprise input ports, 0021-0022 regarding time input would be at the left in the FIGS., paragraphs 0057-0058 symbols representative of various operations that may be performed is interpreted to include the ports necessary for operation];
one or more output ports, each of which representing an output register [paragraphs 0023, 0027, 0055 it is interpreted that quantum circuits formed by user-selectable symbols representative of operations to realize quantum computing algorithms corresponding to qubits and qubit registers inherently comprise output ports, 0021-0022 regarding time output would be at the right in the FIGS., paragraphs 0057-0058 symbols representative of various operations that may be performed is interpreted to include the ports necessary for operation];
one or more instances of modules, each of which having a set of one or more input pins and a set of one or more output pins, wherein each of the modules represents an operation to be performed on values inputted on the set of one or more input pins causing output to be provided on the set of one or more output pins [paragraphs 0023, 0027, 0055 it is interpreted that quantum circuits formed by user-selectable symbols representative of operations to realize quantum computing algorithms corresponding to qubits and qubit registers inherently comprise input pins and output pins, 0021-0022 regarding time input would be at the left and output would be to the right in the FIGS., paragraphs 0057-0058 symbols representative of various operations that may be performed is interpreted to include the pins necessary for operation]; and
wires, each of which connecting between a value feeding element and a value receiving element, the value feeding element is one of an output pin and an input port, the value receiving element is one of an output port and an input pin [paragraph 0055 each interactive element corresponds to a respective qubit of a qubit register is interpreted to include wires];
wherein at least one of the instances is an abstract instance of a module, the module representing a quantum operation [paragraph 0023 single-qubit gate operations, multi-qubit gate operations, a measurement operation, and other quantum computing operations that can be used to form a quantum circuit], the abstract instance representing a duplication of the quantum operation within the quantum circuit [paragraph 0067 multiple gates combined into a particular grouping is interpreted as a duplication];
in response to a user instruction to the GUI [paragraph 0062 further user input, 0068 user input indicative of a request to generate a subroutine], changing presented display to the user [with respect to FIG. 5 it is interpreted that the presented display is changed when the second portion is shown, with respect to FIGS. 6 and 7 it is interpreted that the user’s finger changes the presented display, 0082 modifications to the set of commands may cause the graphical representation to dynamically change], whereby showing to the user a second portion of the abstract quantum circuit [paragraph 0062 a second selected symbol may be received at the GUI, displayed in the GUI, 0069 a new symbol, 0078 second interactive element].
However, although Bishop et al. teach execution on a physical quantum processor [paragraph 0001, 0066, 0083], Bishop et al. do not teach compiling the abstract quantum circuit to obtain the quantum circuit, wherein said compiling comprises replacing the abstract instance with a plurality of instances of the module, whereby concretizing the abstract instance.
Shi et al. teach a method [FIG. 20, paragraph 0211] comprising compiling an abstract quantum circuit to obtain a quantum circuit, wherein said compiling comprises replacing abstract instances with a plurality of instances of a module, whereby concretizing the abstract instance [Abstract, paragraph 0030 need to be mapped and scheduled on real-world physical components of a quantum processing unit in order to execute the quantum circuits using quantum hardware, quantum compilation involves generating a hardware specific executable used to implement a quantum circuit on a quantum hardware device based on a provided abstract quantum algorithm or logical quantum circuit, paragraph 0063, FIG. 11].
Thus, considering that Bishop et al. teach a cloud computing environment [paragraph 0008, 0029-0030], the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because compiling an abstract circuit to obtain a quantum circuit is necessary for real-world operation.
As per claims 2 and 17, wherein the abstract instance is presented in the GUI with an instance instruction, the instance instruction indicates a number of times the module is to be duplicated and connected sequentially, whereby defining a number of the plurality of instances of the module that replace the abstract instance [paragraph 0001 based on particular sequences, 0007 depending on context, encompass a plural number, 0021 the symbols may be placed so as to reflect a sequence of the underlying operations, in other words it is interpreted that the abstract instance as cited above includes an instruction to define the number of instances to be duplicated and connected sequentially to replace the abstract instance for implementing the quantum circuit that the abstracted quantum circuit represents].
As per claim 3, the method 2, wherein the module comprising an input pin set and an output pin set, a number of input pins in the input pin set is equal to a number of output pins in the output pin set, wherein the plurality of instances of the module comprises a first instance and a second instance, wherein said replacing the abstract instance with the plurality of instances further comprises: for each output pin in the output pin set of the first instance, adding a wire that connects the each output pin with a different input pin of the input pin set of the second instance, whereby each input pin in the input pin set of the second instance is configured to receive a value that is fed from a different output pin in the output pin set of the first instance, whereby creating a sequence of instances that pass values therebetween [paragraph 0023 multi-qubit operations, 0027 a quantum circuit includes a particular sequence spread across the computing register (qubits), 0065 symbols can be moved onto different qubits, 0068 a particular grouping that can be applied to any number of qubits, 0071-0072, in other words to implement the quantum computing algorithms].
As per claim 4, the method of Claim 3, wherein a mapping between output pin set of the first instance and between the input pin set is defined based on a definition of the module [mapping is interpreted as inherent for the resultant quantum circuit, Hadamard gate operation, CNOT operation, quantum computing algorithm, etc. to be concretized].
As per claim 5, the method of Claim 4, wherein the mapping is defined based on an order of the input pin set in the module and the output pin set in the module, whereby enabling the user to change the mapping via the GUI by editing the module [order is interpreted as inherent to mapping for proper operation of the quantum circuit etc., 0063 temporal order; with respect to FIG. 5 it is interpreted that the presented display is changed when the second portion is shown, with respect to FIGS. 6 and 7 it is interpreted that the user’s finger changes the presented display, 0082 modifications to the set of commands may cause the graphical representation to dynamically change is interpreted as enabling the user to change the mapping, 0058 parametrized, query the user for parameter values is interpreted as editing].
As per claim 6, the method of Claim 4, wherein the mapping is defined based on displayed height order of input and output ports in a definition of the module, whereby enabling the user to change the mapping via the GUI by editing the module [order is interpreted as inherent to mapping for proper operation of the quantum circuit etc., 0063 temporal order, 0064 a grid ensures appropriate spacing of which height is consider an obvious parameter; with respect to FIG. 5 it is interpreted that the presented display is changed when the second portion is shown, with respect to FIGS. 6 and 7 it is interpreted that the user’s finger changes the presented display, 0082 modifications to the set of commands may cause the graphical representation to dynamically change is interpreted as enabling the user to change the mapping, 0058 parametrized, query the user for parameter values is interpreted as editing].
As per claims 7 and 18, wherein the abstract instance is presented in the GUI with a cascade instruction, the cascade instruction indicates an input pin of the module that is configured to receive different subsets of register value fed to the input pin, wherein said replacing the abstract instance with the plurality of instances of the module comprises: dividing a size of the register value fed to the input pin by a size of the register to be received by the input pin, whereby computing a number of the plurality of instances to be used to replace the abstract instance; and for each instance of the plurality of instances, feeding a different subset of the register value to a respective input pin thereof, whereby duplicating the quantum operation within the quantum circuit each time with respect to a different portion of the register value [paragraph 0068, subroutines may include multiple gates combined into a particular grouping that can be applied to any number of qubits in the qubit register is interpreted as the cascade instruction that will implement the quantum circuit indicated in paragraph 0023 or quantum computing algorithms indicated in paragraph 0027 by replacing the abstract instance accordingly, in order to apply a particular grouping the values are divided to feed the registers to replace the abstract instance for concretizing].
As per claim 8, the method of claim 7, wherein the size of the register to be received by the input pin is N, wherein the size of the register value fed to the input pin is M, wherein the number of the plurality of instances is M/N, wherein instance number i of the plurality of instances is fed with bits of range [N - (i - 1)... (N - i) - 1] from the register value, whereby defining the different portion using different offsets in the register value [the variables N and M are considered a design choice].
As per claim 9, the method of Claim 1, wherein the abstract instance is presented in the GUI with an app parameter instruction, the app parameter instruction indicates, for each instance of the plurality of instances, whether an internal module of the module is to be replaced by an identity module within the instance [paragraph 0058 provides examples including the identity gate].
As per claim 10, the method of Claim 9, wherein the app parameter instruction has a value parameter, the value parameter defines for an i-th instance of the plurality of instances whether to use the internal module or to replace the internal module with the identity module, based on a value of the i-th digit of the value parameter in binary basis [parameter 0058 parameterized gate operations, user selection].
As per claim 11, the method of Claim 1 further comprises: in response to an edit user instruction to the GUI, modifying an abstract command associated with the abstract instance, wherein the abstract command effects a manner in which the abstract instance is replaced in said replacing, thereby changing how the abstract instance is concretized [paragraph 0021 command line interface (CLI), modifications can be dynamically reflected, 0023 user-selectable, used to form a quantum circuit, 0082 and FIG. 8, 0083 such that execution of the quantum circuit can be performed on an actual physical quantum processor].
As per claim 12, the method of Claim 11, wherein the abstract command is at least one of:
a cascade instruction or a parameter thereof [paragraph 0068, subroutines may include multiple gates combined into a particular grouping that can be applied to any number of qubits in the qubit register is interpreted as the cascade instruction that will implement the quantum circuit indicated in paragraph 0023 or quantum computing algorithms indicated in paragraph 0027 by replacing the abstract instance accordingly];
an instance instruction or a parameter thereof [paragraph 0001 based on particular sequences, 0007 depending on context, encompass a plural number, 0021 the symbols may be placed so as to reflect a sequence of the underlying operations, in other words it is interpreted that the abstract instance as cited above includes an instruction to define the number of instances to be duplicated and connected sequentially to replace the abstract instance for implementing the quantum circuit that the abstracted quantum circuit represents];
an app parameter instruction or a parameter thereof, wherein the app parameter instruction defines for different instances to replace an internal module in the module with an identity module [paragraph 0058 provides examples including the identity gate]; and
a usage of an index parameter in a definition of the module, wherein the usage of the index parameter defines different functionalities for different instances of the module that replace the abstract instance [user selection, design choice].
As per claim 15, the method of Claim 1 further comprising providing the quantum circuit for execution by a quantum execution platform [paragraph 0066 completed quantum circuit may be executed on a physical quantum processor, 0001, 0083; Shi et al.].
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over CHAI et al. [WO 2024/181917 A1] in view of Shi et al. [US 2024/0330738 A1].
Taking claim 1 as exemplary of claims 1, 16 and 20 [paragraph 0014 computer-implemented], Chai et al. teach a method comprising:
displaying, via a Graphical User Interface (GUI) [paragraph 0069 GUI], a first portion of an abstract quantum circuit [paragraph 0070-0071 Palette includes representations of circuit operations, can also include Components, in different variants], wherein the GUI enables a user to view a graphical representation of the abstract quantum circuit, the abstract quantum circuit represents a quantum circuit [paragraph 0039 low-level components refer to suitable abstractions that represent a simple part of a FTQ circuit such as Hadamard gate or CNOT gate but can also refer to a sub-circuit, 0055], the abstract quantum circuit comprises:
one or more input ports, each of which representing an input register [paragraph 0044 the definition of a Component is interpreted to include input ports representing an input register for the taking as input some qubits and bits];
one or more output ports, each of which representing an output register [paragraph 0044 the definition of a Component is interpreted to include output ports representing an output register for outputting the results];
one or more instances of modules, each of which having a set of one or more input pins and a set of one or more output pins, wherein each of the modules represents an operation to be performed on values inputted on the set of one or more input pins causing output to be provided on the set of one or more output pins [paragraph 0044 the definition of a Component is interpreted to include pins, 0099 each instantiated copy of the Component is its own version]; and
wires, each of which connecting between a value feeding element and a value receiving element, the value feeding element is one of an output pin and an input port, the value receiving element is one of an output port and an input pin [paragraph 0044 the definition of a Component is interpreted to include wires];
wherein at least one of the instances is an abstract instance of a module, the module representing a quantum operation, the abstract instance representing a duplication of the quantum operation within the quantum circuit [paragraph 0044 a Component is used to represent simple gate operations that act on basic units of information in a pre-defined way, 0055 the user can manipulate such a single object while effectively manipulating as a whole all of the underlying parts at the same time, 0058 repetitive circuit components, 0099 each instantiated copy of the Component is its own version];
in response to a user instruction to the GUI, changing presented display to the user [paragraph 0070-0071 drag and drop, the user can repeatedly place copies into the editor], whereby showing to the user a second portion of the abstract quantum circuit [paragraph 0072Components can be re-arranged by the user, and their connections changed, internal compositions can be changed by the user, toggle views of different representations, 00109contemporaneous update of the display].
However, although Chai et al. teach that the user can transfer the output to another tool [paragraph 0092], Chai et al. do not teach compiling the abstract quantum circuit to obtain the quantum circuit, wherein said compiling comprises replacing the abstract instance with a plurality of instances of the module, whereby concretizing the abstract instance.
Shi et al. teach a method [FIG. 20, paragraph 0211] comprising compiling an abstract quantum circuit to obtain a quantum circuit, wherein said compiling comprises replacing abstract instances with a plurality of instances of a module, whereby concretizing the abstract instance [Abstract, paragraph 0030 need to be mapped and scheduled on real-world physical components of a quantum processing unit in order to execute the quantum circuits using quantum hardware, quantum compilation involves generating a hardware specific executable used to implement a quantum circuit on a quantum hardware device based on a provided abstract quantum algorithm or logical quantum circuit, paragraph 0063, FIG. 11].
Thus, considering Chai et al. teach there is a need to facilitate large-scale quantum computing [paragraph 0013] and a quantum circuit, i.e. a concrete sequence [paragraph 0080], and that Shi et al. allow for compilation of a wide-variety of quantum circuits [Abstract] the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because the combination of teachings would result in an optimized quantum circuit according to the user’s need.
As per claims 2 and 17, wherein the abstract instance is presented in the GUI with an instance instruction, the instance instruction indicates a number of times the module is to be duplicated and connected sequentially, whereby defining a number of the plurality of instances of the module that replace the abstract instance [paragraph 0058 repetitive circuit components, 0081 the user may enter input information, or by programmatically, or by text fields, 0089 RDR].
As per claim 3, the method 2, wherein the module comprising an input pin set and an output pin set, a number of input pins in the input pin set is equal to a number of output pins in the output pin set, wherein the plurality of instances of the module comprises a first instance and a second instance, wherein said replacing the abstract instance with the plurality of instances further comprises: for each output pin in the output pin set of the first instance, adding a wire that connects the each output pin with a different input pin of the input pin set of the second instance, whereby each input pin in the input pin set of the second instance is configured to receive a value that is fed from a different output pin in the output pin set of the first instance, whereby creating a sequence of instances that pass values therebetween [paragraph 0072 Editor is a space where position can be re-arranged, connections changed, internal compositions can be changed].
As per claim 4, the method of Claim 3, wherein a mapping between output pin set of the first instance and between the input pin set is defined based on a definition of the module [paragraph 0054 mapping solutions, 00111 visualize different options for the mapping].
As per claim 5, the method of Claim 4, wherein the mapping is defined based on an order of the input pin set in the module and the output pin set in the module, whereby enabling the user to change the mapping via the GUI by editing the module [paragraph 0054 mapping solutions, 00111 visualize different options for the mapping].
As per claim 6, the method of Claim 4, wherein the mapping is defined based on displayed height order of input and output ports in a definition of the module, whereby enabling the user to change the mapping via the GUI by editing the module [paragraph 0054 mapping solutions, 0097 grid points or to align suggest height order, 00111 visualize different options for the mapping].
As per claims 7 and 18, wherein the abstract instance is presented in the GUI with a cascade instruction, the cascade instruction indicates an input pin of the module that is configured to receive different subsets of register value fed to the input pin, wherein said replacing the abstract instance with the plurality of instances of the module comprises: dividing a size of the register value fed to the input pin by a size of the register to be received by the input pin, whereby computing a number of the plurality of instances to be used to replace the abstract instance; and for each instance of the plurality of instances, feeding a different subset of the register value to a respective input pin thereof, whereby duplicating the quantum operation within the quantum circuit each time with respect to a different portion of the register value [paragraph 0057 is interpreted to provide the functionality of a cascade instruction as a logical abstraction that handles the necessary computations involving dividing and feeding for the underlying components and structure, 0058 repetitive circuit components, subdivided into portions, 0089 RDR].
As per claim 8, the method of claim 7, wherein the size of the register to be received by the input pin is N, wherein the size of the register value fed to the input pin is M, wherein the number of the plurality of instances is M/N, wherein instance number i of the plurality of instances is fed with bits of range [N - (i - 1)... (N - i) - 1] from the register value, whereby defining the different portion using different offsets in the register value [the variables N and M are considered a design choice for either reference].
As per claim 9, the method of Claim 1, wherein the abstract instance is presented in the GUI with an app parameter instruction, the app parameter instruction indicates, for each instance of the plurality of instances, whether an internal module of the module is to be replaced by an identity module within the instance [paragraph 0058 repetitive circuit components, 0081the user may enter input information, or by programmatically, or by text fields, 0089 RDR].
As per claim 10, the method of Claim 9, wherein the app parameter instruction has a value parameter, the value parameter defines for an i-th instance of the plurality of instances whether to use the internal module or to replace the internal module with the identity module, based on a value of the i-th digit of the value parameter in binary basis [paragraph 0058 repetitive circuit components, 0081the user may enter input information, or by programmatically, or by text fields].
As per claim 11, the method of Claim 1 further comprises: in response to an edit user instruction to the GUI, modifying an abstract command associated with the abstract instance, wherein the abstract command effects a manner in which the abstract instance is replaced in said replacing, thereby changing how the abstract instance is concretized [paragraph 0058 repetitive circuit components, 0081the user may enter input information, or by programmatically, or by text fields, 0072 and 00106 Editor].
As per claim 12, the method of Claim 11, wherein the abstract command is at least one of:
a cascade instruction or a parameter thereof [paragraph 0057 is interpreted to provide the functionality of a cascade instruction as a logical abstraction that handles the necessary computations involving dividing and feeding for the underlying components and structure, 0058 repetitive circuit components, subdivided into portions, 0089 RDR];
an instance instruction or a parameter thereof [paragraph 0058 repetitive circuit components, 0081 the user may enter input information, or by programmatically, or by text fields, 0089 RDR];
an app parameter instruction or a parameter thereof, wherein the app parameter instruction defines for different instances to replace an internal module in the module with an identity module [paragraph 0058 repetitive circuit components, 0081the user may enter input information, or by programmatically, or by text fields, 0089 RDR]; and
a usage of an index parameter in a definition of the module, wherein the usage of the index parameter defines different functionalities for different instances of the module that replace the abstract instance [paragraph 0057 logical abstraction, paragraph 0058 repetitive circuit components, the tool thus abstracts the working unit of quantum information as cited above, 0065-0067 rules, 0089 RDR into different visual representations according to the needs of the user].
As per claims 13 and 19, wherein the GUI is a hierarchical GUI enabling editing and display of the abstract quantum circuit, wherein said displaying the first portion of the abstract quantum circuit displays the abstract quantum circuit at a first hierarchical level, wherein the user instruction is an instruction to edit the abstract instance, whereby causing the GUI to display the abstract quantum circuit at a second hierarchical level, the second hierarchical level is a lower level than the first hierarchical level, wherein an input pin of the module is shown in the second hierarchical level as an input port, wherein an output pin of the module is shown in the second hierarchical level as an output port, wherein the module comprises an internal module that is not displayed in the first portion and is displayed in the second portion [these features are interpreted following the citations provided above to include paragraph 0039 starting with low-level components, but can also refer to a sub-circuit, a user can build FTQ circuits of higher and higher complexity with a ground up approach which is interpreted as providing a hierarchical GUI enabling editing and display accordingly at first and second hierarchical levels as cited above, 0053 easily modified in that user can add or delete any Component at any point in the circuit, sub-Components can also be edited, 0055 to be used in larger circuits, 0058 multiple layers of relevance, 0065-0066 rules, 0072 successive layers, 0083 complex circuits can be built]
As per claim 14, the method of Claim 13, wherein in the second hierarchical level, an index parameter is utilized in the definition of at least one element in the module, wherein said replacing the abstract instance with a plurality of instances comprises: providing for each instance of the plurality of instances a different value for the index parameter, whereby enabling i-th and j-th instances to differ based on the definition of the at least one element [this is interpreted as design choice according to the targeted design and need of the user provided for by the RDR data structure].
As per claim 15, the method of Claim 1 further comprising providing the quantum circuit for execution by a quantum execution platform [Shi et al.].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See, for example, Aleksandrowicz et al. [US 2025/0139481 A1] at entire document; Huffman et al. [US 2024/0177036 A1] at entire document. Minev et al. [US 2022/0036226 A1] at Abstract, FIG. 3; Huffman et al. [US 2024/0152790 A1] at Abstract.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEIGH M GARBOWSKI whose telephone number is (571)272-1893. The examiner can normally be reached M-F 9-5 EST.
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/LEIGH M GARBOWSKI/ Primary Examiner, Art Unit 2851
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