DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to amendment
2. This Office Action is in response to Amendment filed on 04/08/2026
Specification
The new title has been amended and the specification objection mailed on01/22/2026 has been withdrawn.
Claims
Claims 1-2, 4, 7, 12 and 17-18 have been amended.
Claims 3, 5-6, 8-11, 13-16 and 19-20 have been remained
Claims 1-20 are currently pending in the application.
Response to Arguments
3. Applicant's arguments filed 04/08/2026 have been fully considered but they are notpersuasive.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
4. Claims 1-4 and 9-14 are rejected under 35 U.S.C. 103(a) as being unpatentable over LEE et al., hereafter “LEE” (U.S. Publication No. 2022/0246568 A1) in view of KR’222 (KR-20110045222-A)
Regarding claim 1, LEE discloses a semiconductor package, comprising:
a lower redistribution structure (140), including a redistribution insulation layer (141), a plurality of ball pads (145b) in the redistribution insulation layer (141) apart from one another, a double via having a first active via (1st 143, Left) and a dummy via (149) located on at least one of the plurality of ball pads (145b) and apart from each other in the redistribution insulation layer (141), and a first active redistribution layer (145a) electrically connected to the first active via ((1st 143, Left) in the redistribution insulation layer (141);
solder balls (150) electrically connected to the plurality of ball pads (145b) under the lower redistribution structure (140);
a first semiconductor chip (110) on the lower redistribution structure (140) and electrically connected to the first active via (1st 143, Left) and the first active redistribution layer (145a) of the lower redistribution structure (140); and
a molding layer (120) molding the first semiconductor chip (110) on the lower redistribution structure (1400 (see Fig. 1 below and para [0022]-[0033]).
LEE discloses the features of the claimed invention as discussed above, but does not disclose wherein the dummy via is a support via.
KR’222, however, teaches or suggests wherein the dummy via (392/393) is a support via (Fig. 8b and English Text).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of LEE to provide wherein the dummy via is a support via as taught by KR’222 for a purpose of stably supporting the ball pads and the solder balls of the top package.
Regarding claim 2, LEE and KR’222 discloses the features of the claimed invention as discussed above, but does not disclose wherein the dummy via is configured to increase adhesion between the redistribution insulation layer and the plurality of ball pads. However, the recitation of “wherein the dummy via is configured to increase adhesion between the redistribution insulation layer and the plurality of ball pads” as recited in the claim above, is a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Regarding claim 3, LEE and KR’222 (citations to LEE unless otherwise noted) discloses wherein the dummy via (149) has a larger diameter than the first active via (1st 143, Left) (see Fig. 1 below).
Regarding claim 4, LEE and KR’222 (citations to LEE unless otherwise noted) disclose wherein the dummy via (149) and the first active via (1st 143, Left) are spaced apart from each other in any one of a first horizontal direction (X-direction) and a second horizontal direction on the at least one ball pad (145b) ((see Fig. 1 below)).
Regarding claim 9, LEE and KR’222 (citations to LEE unless otherwise noted) disclose wherein a first diameter of each of the plurality of ball pads (145b) is greater than a second diameter of each of the solder balls (150) (see Fig. 1 below).
Regarding claim 10, LEE and KR’222 (citations to LEE unless otherwise noted) disclose wherein the double via (1st 143, Left/149) is located in a region near an edge of the first semiconductor chip (110) (see Fig. 1 below).
Regarding claim 11, LEE and KR’222 ((citations to LEE unless otherwise noted) disclose wherein the double via (1st 143, Left/149) is located in a peripheral region of the first semiconductor chip (110) (see Fig. 1 below).
Regarding claim 12, LEE discloses a semiconductor package, comprising:
a lower redistribution structure (140) having a fan-in region and a fan-out region, the lower redistribution structure (140) including a redistribution insulation layer (141), a plurality of ball pads (145b) in the redistribution insulation layer (141) apart from one another, first active vias (1st 143, Left) electrically connected to the plurality of ball pads (145b), and a first active redistribution layer (145a) electrically connected to the first active vias (1st 143, Left);
solder balls (150) electrically connected to the plurality of ball pads (145b) under the lower redistribution structure (140);
a first semiconductor chip (110) on the fan-in region of the lower redistribution structure (140) and electrically connected to the first active vias (1st 143, Left) and the first active redistribution layer (145a) of the lower redistribution structure (140); and
a molding layer (120) molding the first semiconductor chip (110) on the fan-out region of the lower redistribution structure (140), wherein: the lower redistribution structure (140) further includes a dummy via (149) on at least one ball pad (145b) from among the plurality of ball pads (145) in the fan-out region, and a double via including a first active via (1st 143, Left) and the dummy via (149) spaced apart from each other is on the at least one ball pad (145b) of the fan-out region (see Fig. 1 below).
LEE discloses the features of the claimed invention as discussed above, but does not disclose wherein the dummy via is a support via.
KR’222, however, teaches or suggests wherein the dummy via (392/393) is a support via (Fig. 8b and English Text).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of LEE to provide wherein the dummy via is a support via as taught by KR’222 for a purpose of stably supporting the ball pads and the solder balls.
Regarding claim 13, LEE and KR’222 (citations to LEE unless otherwise noted)
disclose wherein the double via (1st 143, Left/149) is in a boundary region between the fan-in region (FI) and the fan-out region (FO) (see Fig. 1 above).
Regarding claim 14, LEE and KR’222 (citations to LEE unless otherwise noted) disclose wherein the dummy via (140) and the first active via (1st143, Left) constituting the double via are spaced apart from each other in any one of a first horizontal direction (X-direction) and a second horizontal direction on the at least one ball pad (145b) (see Fig. 1 above).
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Regarding claim 13, LEE and KR’22 (citations to LEE unless otherwise noted) disclose wherein the double via (1st 143, Left/149) is in a boundary region between the fan-in region (FI) and the fan-out region (FO) (see Fig. 1 above).
Regarding claim 14, LEE and KR’222 (citations to LEE unless otherwise noted) disclose wherein the dummy via (140) and the first active via (1st143, Left) constituting the double via are spaced apart from each other in any one of a first horizontal direction (X-direction) and a second horizontal direction on the at least one ball pad (145b) (see Fig. 1 above).
Allowable Subject Matter
5. The following is a statement of reason for the indication of allowable subject matter:
Claims 18-20 would be allowed.
Claims 18-20 are considered allowable since the prior art of record and the considered pertinent to the applicant’s disclosure does not teach or suggest the claimed invention of a semiconductor package having an upper redistribution structure being positioned on the lower molding layer, the redistribution connection via, and the first semiconductor chip, and electrically connected to the lower redistribution structure through the redistribution connection via, and an upper semiconductor package mounted on the lower semiconductor package including a second semiconductor chip electrically connected to the upper redistribution structure and an upper molding layer molding the second semiconductor chip, as cited in the independent claim 18.
Claims 19-20 are directly depend on the independent claim 18, then, they are also being allowed.
Claims 5-8 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion6. Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Phuc T. Dang whose telephone number is (571) 272-1776. The examiner can normally be reached on M-F (9-6:00pm). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Choi, can be reached on 469-295-9060 The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/PHUC T DANG/Primary Examiner, Art Unit 2897
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