DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Oath/Declaration
2. The oath/declaration filed on 11/01/2023 is acceptable.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. The office acknowledges receipt of the following items from the applicant:
Information Disclosure Statement (IDS) filed on 11/01/2023.
Specification
5. The specification is objected to for the following reason: The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed (see MPEP 606.01).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless --
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. Claims 1, 3-4 and 9-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE et al., hereafter “LEE” (U.S. Publication No. 2022/0246568 A1).
Regarding claim 1, LEE discloses a semiconductor package, comprising:
a lower redistribution structure (140), including a redistribution insulation layer (141), a plurality of ball pads (145b) in the redistribution insulation layer (141) apart from one another, a double via having a first active via (1st 143, Left) and a dummy via (149) located on at least one of the plurality of ball pads (145b) and apart from each other in the redistribution insulation layer (141), and a first active redistribution layer (145a) electrically connected to the first active via ((1st 143, Left) in the redistribution insulation layer (141);
solder balls (150) electrically connected to the plurality of ball pads (145b) under the lower redistribution structure (140);
a first semiconductor chip (110) on the lower redistribution structure (140) and electrically connected to the first active via (1st 143, Left) and the first active redistribution layer (145a) of the lower redistribution structure (140); and
a molding layer (120) molding the first semiconductor chip (110) on the lower redistribution structure (1400 (see Fig. 1 below and para [0022]-[0033]).
Regarding claim 3, LEE discloses wherein the dummy via (149) has a larger diameter than the first active via (1st 143, Left) (see Fig. 1 below).
Regarding claim 4, LEE discloses wherein the dummy via (149) and the first active via (1st 143, Left) are spaced apart from each other in any one of a first horizontal direction (X-direction) and a second horizontal direction on the at least one ball pad (145b) ((see Fig. 1 below)).
Regarding claim 9, LEE discloses wherein a first diameter of each of the plurality of ball pads (145b) is greater than a second diameter of each of the solder balls (150) (see Fig. 1 below).
Regarding claim 10, LEE discloses wherein the double via (1st 143, Left/149) is located in a region near an edge of the first semiconductor chip (110) (see Fig. 1 below).
Regarding claim 11, LEE discloses wherein the double via (1st 143, Left/149) is located in a peripheral region of the first semiconductor chip (110) (see Fig. 1 below).
Regarding claim 12, LEE discloses a semiconductor package, comprising:
a lower redistribution structure (140) having a fan-in region and a fan-out region, the lower redistribution structure (140) including a redistribution insulation layer (141), a plurality of ball pads (145b) in the redistribution insulation layer (141) apart from one another, first active vias (1st 143, Left) electrically connected to the plurality of ball pads (145b), and a first active redistribution layer (145a) electrically connected to the first active vias (1st 143, Left);
solder balls (150) electrically connected to the plurality of ball pads (145b) under the lower redistribution structure (140);
a first semiconductor chip (110) on the fan-in region of the lower redistribution structure (140) and electrically connected to the first active vias (1st 143, Left) and the first active redistribution layer (145a) of the lower redistribution structure (140); and
a molding layer (120) molding the first semiconductor chip (110) on the fan-out region of the lower redistribution structure (140), wherein: the lower redistribution structure (140) further includes a dummy via (149) on at least one ball pad (145b) from among the plurality of ball pads (145) in the fan-out region, and a double via including a first active via (1st 143, Left) and the dummy via (149) spaced apart from each other is on the at least one ball pad (145b) of the fan-out region (see Fig. 1 below).
Regarding claim 13, LEE discloses wherein the double via (1st 143, Left/149) is in a boundary region between the fan-in region (FI) and the fan-out region (FO) (see Fig. 1 above).
Regarding claim 14, LEE discloses wherein the dummy via (140) and the first active via (1st143, Left) constituting the double via are spaced apart from each other in any one of a first horizontal direction (X-direction) and a second horizontal direction on the at least one ball pad (145b) (see Fig. 1 above).
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Regarding claim 13, LEE discloses wherein the double via (1st 143, Left/149) is in a boundary region between the fan-in region (FI) and the fan-out region (FO) (see Fig. 1 above).
Regarding claim 14, LEE discloses wherein the dummy via (140) and the first active via (1st143, Left) constituting the double via are spaced apart from each other in any one of a first horizontal direction (X-direction) and a second horizontal direction on the at least one ball pad (145b) (see Fig. 1 above).
Allowable Subject Matter
7. The following is a statement of reason for the indication of allowable subject matter:
Claims 18-20 would be allowed.
Claims 18-20 are considered allowable since the prior art of record and the considered pertinent to the applicant’s disclosure does not teach or suggest the claimed invention of a semiconductor package having an upper redistribution structure being positioned on the lower molding layer, the redistribution connection via, and the first semiconductor chip, and electrically connected to the lower redistribution structure through the redistribution connection via, and an upper semiconductor package mounted on the lower semiconductor package including a second semiconductor chip electrically connected to an upper redistribution structure and an upper molding layer molding the second semiconductor chip, as cited in the independent claim 18.
Claims 19-20 are directly depend on the independent claim 18, then, they are also being allowed.
Claims 2, 5-8 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Phuc T. Dang whose telephone number is 571-272-1776. The examiner can normally be reached on 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHUC T DANG/Primary Examiner, Art Unit 2897