DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 22, 2026 has been entered.
Response to Amendment
Applicant’s arguments with respect to claims 1 – 20 have been considered, but they are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. (KR 2017-0086921A).
Regarding claim 1, in Figure 1, Cho discloses a circuit board, comprising: an insulating layer (160); a circuit wiring (161) disposed inside the insulating layer; a plurality of first conductive pads (comprising 133/131) disposed in a first region (middle region comprising cavity 111) on the insulating layer and connected to the circuit wiring; an auxiliary pad (140) disposed over at least one of the plurality of first conductive pads and having a diameter smaller than that of the at least one of the plurality of first conductive pads (portion 133 of layer 133/131 has a larger diameter than pad 140, Figure 1), wherein a portion of the auxiliary pad protrudes from the at least one of the plurality of first conductive pads (Figure 1); and a solder resist layer (150) disposed over the insulating layer, having a first opening (111) overlapping the first region, and spaced apart from the auxiliary pad (Figure 1).
Regarding claim 2, Cho discloses wherein: the plurality of first conductive pads do not contact the solder resist layer (Figure 1).
Regarding claim 3, Cho discloses wherein: the auxiliary pad does not contact the solder resist layer (Figure 1).
Regarding claim 4, Cho discloses wherein: a side portion of the auxiliary pad has an undercut (Figure 1).
Regarding claim 5, Cho discloses wherein: the circuit board further includes: a plurality of second conductive pads disposed in a second region on a portion on the insulating layer different from the first region, the plurality of second conductive pads are connected to the circuit wiring (Figure 1).
Regarding claim 6, Cho discloses wherein: the solder resist layer has a second opening overlapping the plurality of second conductive pads (Figure 1).
Regarding claim 7, in Figure 1, Cho discloses an electronic component package, comprising: a circuit board including an insulating layer (160), a circuit wiring (161) disposed inside the insulating layer, a plurality of first conductive pads (comprising 133/131) disposed in a first region (middle region comprising cavity 111) on the insulating layer and connected to the circuit wiring, an auxiliary pad (140) disposed over at least one of the plurality of first conductive pads and having a diameter smaller than that of the at least one of the plurality of first conductive pads (portion 133 of layer 133/131 has a larger diameter than pad 140, Figure 1), wherein a portion of the auxiliary pad protrudes from the at least one of the plurality of first conductive pads (Figure 1), and a solder resist layer (150) disposed over the insulating layer, having a first opening (111) overlapping the first region, and spaced apart from the auxiliary pad (Figure 1); an electronic component (180, Figure 2) spaced apart from the solder resist layer and disposed over the first opening; and a conductive adhesive member (SB, Figure 2) electrically connecting the auxiliary pad and the electronic component (Figure 2).
Regarding claim 8, Cho discloses wherein: the conductive adhesive member includes: a conductive bump transmitting an electrical signal of the electronic component; and an auxiliary adhesive member attaching the auxiliary pad and the conductive bump to each other (Figure 1).
Regarding claim 9, Cho discloses wherein: a diameter of the conductive bump is smaller than that of at least one first conductive pad among the plurality of first conductive pads (Figure 1).
Regarding claim 10, Cho discloses wherein: the plurality of first conductive pads do not contact the solder resist layer (Figure 1).
Regarding claim 11, Cho discloses an underfill filling between the electronic component and an upper surface of the insulating layer, wherein the underfill contacts a side surface of at least one first conductive pad among the plurality of first conductive pads (Figure 1).
Regarding claim 12, Cho discloses wherein: a side portion of the auxiliary pad has an undercut (Figure 1).
Regarding claim 13, Cho discloses wherein: the auxiliary adhesive member includes: a first adhesive part disposed between the auxiliary pad and the conductive bump; and a second adhesive part extending from the first adhesive part along the side portion of the auxiliary pad to fill the undercut (Figure 1).
Regarding claim 14, Cho discloses wherein: the circuit board further includes: a plurality of second conductive pads disposed in a second region on a portion on the insulating layer different from the first region, the plurality of second conductive pads are connected to the circuit wiring; and the solder resist layer has a second opening overlapping the plurality of second conductive pads (Figure 1).
Regarding claim 15, Cho discloses wherein: the underfill does not contact a side surface of at least one second conductive pad among the plurality of second conductive pads (Figure 1).
Regarding claim 16, Cho discloses wherein: a shortest gap between a lower surface of the electronic component and an upper surface of the insulating layer is longer than a shortest gap between an extension line along the lower surface of the electronic component and an upper surface of the solder resist layer in the second region (Figure 1).
Regarding claim 17, in Figure 1, Cho discloses a method of manufacturing an electronic component package, comprising: forming an insulating layer (160) having a circuit wiring (161) disposed therein; forming a plurality of first conductive pads (comprising 133/131) in a first region (middle region comprising cavity 111) on the insulating layer, the plurality of first conductive pads is connected to the circuit wiring; forming a solder resist layer (150) over the insulating layer, the solder resist layer has a first opening (111) overlapping the first region (Figure 1); forming an auxiliary pad (140), which has a diameter smaller than that of at least one of the plurality of first conductive pads (portion 133 of layer 133/131 has a larger diameter than pad 140, Figure 1) and is spaced apart from the solder resist layer, over the at least one of the plurality of first conductive pads (Figure 1), wherein a portion of the auxiliary pad protrudes from the at least one of the plurality of first conductive pads (Figure 1); and electrically connecting the auxiliary pad and an electronic component (180, Figure 2) via a conductive adhesive member (SB, Figure 2).
Regarding claim 18, Cho discloses positioning the electronic component over the first opening while being spaced apart from the solder resist layer; and filling an underfill between the electronic component and an upper surface of the insulating layer, wherein the underfill contacts a side surface of at least one first conductive pad among the plurality of first conductive pads (Figure 1).
Regarding claim 19, Cho discloses forming a plurality of second conductive pads in a second region on a portion on the insulating layer different from the first region while forming the plurality of first conductive pads, the plurality of second conductive pads is connected to the circuit wiring, wherein the underfill does not contact a side surface of at least one second conductive pad among the plurality of second conductive pads (Figure 1).
Regarding claim 20, Cho discloses wherein: a portion of the at least one of the plurality of first conductive pads protrudes from a surface of the insulating layer, a surface of the undercut is inclined relative to a surface of the at least one of the plurality of first conductive pads, the conductive bump is a pillar, and the electronic component is spaced apart from the auxiliary pad (Figure 1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847
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