DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s arguments with respect to claims 1 – 20 have been considered, but they are not persuasive. In the response to the Office Action dated September 25, 2025, Applicant first argues that Lee does not disclose a circuit board comprising a plurality of first conductive pads as claimed in independent claims 1, 7, and 17. Applicant contends that regarding connection terminal 1400, Lee explicitly states that it is a part of the semiconductor chip 1100 instead of the printed circuit board. Examiner first points out that connection terminals 1400 were not cited as the plurality of first conductive pads. Examiner cited solder bumps 1420 as the plurality of first conductive pads, and contends that though the solder bumps 1420 are a part of the semiconductor chip 1100, they are also a part of the circuit board 1000 (see Figure 4 of Lee). The claims do not preclude solder bumps 1420 from being a part of the semiconductor chip 1100.
Secondly, Applicant argues that Lee does not disclose “an auxiliary pad disposed over at least one of the plurality of first conductive pads and having a diameter smaller than that of the at least one of the plurality of first conductive pads” as recited in claims 1, 7, and 17. Examiner respectfully disagrees. Examiner has cited connection terminal 1400 as the auxiliary pad. Connection terminal 1400 clearly has a smaller diameter than that of the solder bump 1420 (“cited first conductive pad”).
Thus, Applicant’s traversal of the instant rejection on these grounds is deemed unsuccessful.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (U.S. Patent Publication No. 2022/0173025).
Regarding claim 1, in Figure 4, Lee discloses a circuit board (1000), comprising: an insulating layer (10); a circuit wiring (50) disposed inside the insulating layer; a plurality of first conductive pads (1420) disposed in a first region (region where bump 1420 is disposed) on the insulating layer and connected to the circuit wiring; an auxiliary pad (1400) disposed over at least one of the plurality of first conductive pads and having a diameter smaller than that of the at least one of the plurality of first conductive pads (Figure 4); and a solder resist layer (45) disposed over the insulating layer, having a first opening overlapping the first region, and spaced apart from the auxiliary pad (Figure 4).
Regarding claim 2, Lee discloses wherein: the plurality of first conductive pads do not contact the solder resist layer (Figure 4).
Regarding claim 3, Lee discloses wherein: the auxiliary pad does not contact the solder resist layer (Figure 4).
Regarding claim 4, Lee discloses wherein: a side portion of the auxiliary pad has an undercut (Figure 4).
Regarding claim 5, Lee discloses wherein: the circuit board further includes: a plurality of second conductive pads disposed in a second region on a portion on the insulating layer different from the first region, the plurality of second conductive pads are connected to the circuit wiring (Figure 4).
Regarding claim 6, Lee discloses wherein: the solder resist layer has a second opening overlapping the plurality of second conductive pads (Figure 4).
Regarding claim 7, in Figure 4, Lee discloses an electronic component package, comprising: a circuit board (1000) including an insulating layer (10), a circuit wiring (50) disposed inside the insulating layer, a plurality of first conductive pads (1420) disposed in a first region (region where bump 1420 is disposed) on the insulating layer and connected to the circuit wiring, an auxiliary pad (1400) disposed over at least one of the plurality of first conductive pads and having a diameter smaller than that of the at least one of the plurality of first conductive pads (Figure 4), and a solder resist layer (45) disposed over the insulating layer, having a first opening overlapping the first region, and spaced apart from the auxiliary pad (Figure 4); an electronic component (1100) spaced apart from the solder resist layer and disposed over the first opening; and a conductive adhesive member (solder electrically connecting the connection terminal of semiconductor chip 1100 to connection terminal 1400; not shown, Figure 4) electrically connecting the auxiliary pad and the electronic component (Figure 4).
Regarding claim 8, Lee discloses wherein: the conductive adhesive member includes: a conductive bump transmitting an electrical signal of the electronic component; and an auxiliary adhesive member attaching the auxiliary pad and the conductive bump to each other (Figure 4).
Regarding claim 9, Lee discloses wherein: a diameter of the conductive bump is smaller than that of at least one first conductive pad among the plurality of first conductive pads (Figure 4).
Regarding claim 10, Lee discloses wherein: the plurality of first conductive pads do not contact the solder resist layer (Figure 4).
Regarding claim 11, Lee discloses an underfill filling between the electronic component and an upper surface of the insulating layer, wherein the underfill contacts a side surface of at least one first conductive pad among the plurality of first conductive pads (Figure 4).
Regarding claim 12, Lee discloses wherein: a side portion of the auxiliary pad has an undercut (Figure 4).
Regarding claim 13, Lee discloses wherein: the auxiliary adhesive member includes: a first adhesive part disposed between the auxiliary pad and the conductive bump; and a second adhesive part extending from the first adhesive part along the side portion of the auxiliary pad to fill the undercut (Figure 4).
Regarding claim 14, Lee discloses wherein: the circuit board further includes: a plurality of second conductive pads disposed in a second region on a portion on the insulating layer different from the first region, the plurality of second conductive pads are connected to the circuit wiring; and the solder resist layer has a second opening overlapping the plurality of second conductive pads (Figure 4).
Regarding claim 15, Lee discloses wherein: the underfill does not contact a side surface of at least one second conductive pad among the plurality of second conductive pads (Figure 4).
Regarding claim 16, Lee discloses wherein: a shortest gap between a lower surface of the electronic component and an upper surface of the insulating layer is longer than a shortest gap between an extension line along the lower surface of the electronic component and an upper surface of the solder resist layer in the second region (Figure 4).
Regarding claim 17, in Figure 4, Lee discloses a method of manufacturing an electronic component package, comprising: forming an insulating layer (10) having a circuit wiring (50) disposed therein; forming a plurality of first conductive pads (1420) in a first region (region where bump 1420 is disposed) on the insulating layer, the plurality of first conductive pads is connected to the circuit wiring; forming a solder resist layer (45) over the insulating layer, the solder resist layer has a first opening overlapping the first region (Figure 4); forming an auxiliary pad (1400), which has a diameter smaller than that of at least one of the plurality of first conductive pads and is spaced apart from the solder resist layer (Figure 4), over the at least one of the plurality of first conductive pads; and electrically connecting the auxiliary pad and an electronic component (1100) via a conductive adhesive member (solder electrically connecting the connection terminal of semiconductor chip 1100 to connection terminal 1400; not shown, Figure 4).
Regarding claim 18, Lee discloses positioning the electronic component over the first opening while being spaced apart from the solder resist layer; and filling an underfill between the electronic component and an upper surface of the insulating layer, wherein the underfill contacts a side surface of at least one first conductive pad among the plurality of first conductive pads (Figure 4).
Regarding claim 19, Lee discloses forming a plurality of second conductive pads in a second region on a portion on the insulating layer different from the first region while forming the plurality of first conductive pads, the plurality of second conductive pads is connected to the circuit wiring, wherein the underfill does not contact a side surface of at least one second conductive pad among the plurality of second conductive pads (Figure 4).
Regarding claim 20, Lee discloses wherein: a portion of the at least one of the plurality of first conductive pads protrudes from a surface of the insulating layer, a portion of the auxiliary pad protrudes from the at least one of the plurality of first conductive pads, a surface of the undercut is inclined relative to a surface of the at least one of the plurality of first conductive pads, the conductive bump is a pillar, and the electronic component is spaced apart from the auxiliary pad (Figure 4).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847