DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (20210013186) in view of Saito (20150295131)
Regarding Claim 1, in Figs. 8-10, especially Fig. 9 and especially paragraph 0027, Chen et al. discloses a display device, comprising: a substrate 102 on which a plurality of sub-pixels is defined; a light-emitting element LD2 disposed on each of the plurality of sub-pixels and having an inversely tapered shape; a first connection electrode ce1/RL1 configured to surround a side surface of a lower portion of the light-emitting element LD2 (see Fig. 9); a second connection electrode ce2/RL2 configured to cover an upper portion of the light-emitting element (see Fig. 9); and a first planarization layer PL1 disposed between the first connection electrode ce1/RL1 and the second connection electrode ce2/RL2 (see the right hand side of Fig. 9). Chen et al. fails to disclose the newly added limitation of wherein the first connection electrode contacts to the side surface of the lower portion of the light-emitting element. However, Saito discloses a light emitting device where in Figs.1A and 1B, in paragraphs 0009 and 0029 elements 30 and 40, first connection electrode 30/40 contacts (not necessarily directly as the claim language does not require it) to the side surface of the lower portion of the (inverse tapered shaped) light-emitting element 20
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required connection electrode in Chen et al as taught by Saito et al, in order to facilitate for self-transfer/self-assembly for the light emitting elements during manufacture.
Regarding Claim 2, in Chen et al., the light- emitting element LD2 comprises: a first semiconductor layer SE1 electrically connected to the first connection electrode; a second semiconductor layer SE2 electrically connected to the second connection electrode; and a light-emitting layer MQL disposed between the first semiconductor layer SE1 and the second semiconductor layer SE2
Regarding Claim 3, in Chen et al, the light- emitting element LD2 is configured such that the light-emitting layer MQL and the second semiconductor layer SE2 are disposed on the first semiconductor layer, wherein an area of a top surface of the first semiconductor SE1 layer is smaller than an area of a top surface of the second semiconductor layer SE2, and wherein a top surface of the first planarization layer PL1 is disposed at a height equal to or lower than a height of the top surface of the second semiconductor layer.
Regarding Claim 4, in Chen et al, a metal layer ce2 disposed between the second semiconductor SE2 layer and the second connection electrode RL2 of the light-emitting element, wherein the metal layer is made of the same material as the first connection electrode RL1.
Regarding Claim 5, in Chen et al, the second connection electrode RL2 is electrically connected to the second semiconductor layer SE2 through the metal layer ce2.
Regarding Claim 6, in Chen et al, a bonding layer 116 disposed below the light-emitting element LD2 and the first connection electrode RL1; a driving transistor TFT disposed between the substrate 102 and the bonding layer 116; and a power line ML1 disposed between the substrate 102 and the bonding layer 116, wherein the first connection electrode RL1 electrically connects the driving transistor TFT and the first semiconductor layer SE1 through a contact hole of the bonding layer, and wherein the second connection electrode RL1 electrically connects the power line 116 and the second semiconductor layer SE2 through a contact hole of the bonding layer 116.
Regarding Claim 7, in Chen et al., a passivation layer 118 disposed between the driving transistor TFT and the power line and the bonding layer; a first reflective electrode DE/TH3 disposed between the passivation layer 118 and the bonding layer 116 and electrically connected to the driving transistor TFT and the first connection electrode RL1; and a second reflective electrode CM disposed on the passivation layer 118 and the bonding layer 118 and electrically connected to the power line ML1 and the second connection electrode RL2 .
Regarding Claim 8, in Chen et al, an interlayer insulating layer 120 disposed on the first connection electrode RL1 and disposed to surround the first semiconductor layer SE1 of the light-emitting element; and a third reflective electrode disposed between the interlayer insulating layer and the first planarization layer PL1, wherein the third reflective electrode ML3 is separated from the first semiconductor layer and the first connection electrode by the interlayer insulating layer (see Fig. 12)
Regarding Claim 9, in Chen et al., a cross- section of the third reflective electrode ML3 is exposed from a top surface and a side surface of the first planarization layer PL1, and wherein the exposed cross-section of the third reflective electrode ML3 adjoins the second connection electrode RL2.
Regarding Claim 10, in Chen et al, the light- emitting element LD2 is configured such that the light-emitting layer MQL and the first semiconductor layer SE1 are disposed on the second semiconductor layer SE2 , wherein an area of a top surface of the second semiconductor layer SE2 is smaller than an area of a top surface of the first semiconductor layer SE1, and wherein a top surface of the first planarization layer PL1 is disposed at a height equal to or lower than a height of a top surface of the first semiconductor layer SE1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 5/26/2026
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