DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 in the reply filed on 1/5/2026 is acknowledged.
Claims 11-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method claims, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/5/2026
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (20210013186)
Regarding Claim 1, in Figs. 8-10, especially Fig. 9 and especially paragraph 0027, Chen et al. discloses a display device, comprising: a substrate 102 on which a plurality of sub-pixels is defined; a light-emitting element LD2 disposed on each of the plurality of sub-pixels and having an inversely tapered shape; a first connection electrode ce1/RL1 configured to surround a side surface of a lower portion of the light-emitting element LD2 (see Fig. 9); a second connection electrode ce2/RL2 configured to cover an upper portion of the light-emitting element (see Fig. 9); and a first planarization layer PL1 disposed between the first connection electrode ce1/RL1 and the second connection electrode ce2/RL2 (see the right hand side of Fig. 9).
Regarding Claim 2, the light- emitting element LD2 comprises: a first semiconductor layer SE1 electrically connected to the first connection electrode; a second semiconductor layer SE2 electrically connected to the second connection electrode; and a light-emitting layer MQL disposed between the first semiconductor layer SE1 and the second semiconductor layer SE2
Regarding Claim 3, the light- emitting element LD2 is configured such that the light-emitting layer MQL and the second semiconductor layer SE2 are disposed on the first semiconductor layer, wherein an area of a top surface of the first semiconductor SE1 layer is smaller than an area of a top surface of the second semiconductor layer SE2, and wherein a top surface of the first planarization layer PL1 is disposed at a height equal to or lower than a height of the top surface of the second semiconductor layer.
Regarding Claim 4, a metal layer ce2 disposed between the second semiconductor SE2 layer and the second connection electrode RL2 of the light-emitting element, wherein the metal layer is made of the same material as the first connection electrode RL1.
Regarding Claim 5, the second connection electrode RL2 is electrically connected to the second semiconductor layer SE2 through the metal layer ce2.
Regarding Claim 6, a bonding layer 116 disposed below the light-emitting element LD2 and the first connection electrode RL1; a driving transistor TFT disposed between the substrate 102 and the bonding layer 116; and a power line ML1 disposed between the substrate 102 and the bonding layer 116, wherein the first connection electrode RL1 electrically connects the driving transistor TFT and the first semiconductor layer SE1 through a contact hole of the bonding layer, and wherein the second connection electrode RL1 electrically connects the power line 116 and the second semiconductor layer SE2 through a contact hole of the bonding layer 116.
Regarding Claim 7, a passivation layer 118 disposed between the driving transistor TFT and the power line and the bonding layer; a first reflective electrode DE/TH3 disposed between the passivation layer 118 and the bonding layer 116 and electrically connected to the driving transistor TFT and the first connection electrode RL1; and a second reflective electrode CM disposed on the passivation layer 118 and the bonding layer 118 and electrically connected to the power line ML1 and the second connection electrode RL2 .
Regarding Claim 8, an interlayer insulating layer 120 disposed on the first connection electrode RL1 and disposed to surround the first semiconductor layer SE1 of the light-emitting element; and a third reflective electrode disposed between the interlayer insulating layer and the first planarization layer PL1, wherein the third reflective electrode ML3 is separated from the first semiconductor layer and the first connection electrode by the interlayer insulating layer (see Fig. 12)
Regarding Claim 9, a cross- section of the third reflective electrode ML3 is exposed from a top surface and a side surface of the first planarization layer PL1, and wherein the exposed cross-section of the third reflective electrode ML3 adjoins the second connection electrode RL2.
Regarding Claim 10, the light- emitting element LD2 is configured such that the light-emitting layer MQL and the first semiconductor layer SE1 are disposed on the second semiconductor layer SE2 , wherein an area of a top surface of the second semiconductor layer SE2 is smaller than an area of a top surface of the first semiconductor layer SE1, and wherein a top surface of the first planarization layer PL1 is disposed at a height equal to or lower than a height of a top surface of the first semiconductor layer SE1.
Pertinent Prior Arts Not Relied Upon
Shim et al. (KR20170076865) (submitted by the applicant on 6/12/2024) in Figs. 2 and 3 discloses reverse tapered light emitting element 200/180/190.
Choi et al. 20250006789 Fig. 3 discloses an OLED device with driver TFT and mini/micro LED with tapered shape. Especially with respect to claims that that does not define surface area between the first and second semiconductor layers, examiner is in the opinion that reverse tapered and tapered limitations could interchangeably applied.
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 2/11/2026