DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5, 6, and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bayerer US 2014/0035118 A1. Bayerer discloses (see, for example, FIG. 3) a power semiconductor module arrangement comprising a housing 7/10, substrate 2, holding pins 4, first end 42, holding elements 71, and sleeve 72. The holding pins 4 extends from the substrate 2 in a vertical direction perpendicular to a top surface of the substrate 2 towards a different one of the one of more holding elements 71 such that the free end 42 of each of the one or more holding pins 4 is arranged inside the respective holding element 71. In paragraph [0044], Bayerer discloses the holding pin 4 being connected by the free end 42 by a press-fit contact (i.e. force-fitting).
Regarding claim 3, see, for example, FIG. 3 wherein Bayerer discloses two holding
elements 71 arranged on opposing sides of the housing 7/10.
Regarding claim 5, see, for example, FIG. 3 wherein Bayerer discloses additional holding elements 83 as well as holding elements 71, which are more than the holding pins 4.
Regarding claim 6, see, for example, FIG. 3 wherein Bayerer discloses the holding elements 71 having a sleeve 72, which are contact holes that receive the free end 42 of one of the holding pins 4.
Regarding claim 11, see, for example, paragraph [0043] wherein Bayerer discloses sheet metal (i.e. connection layer) on the upper metallization layer 21 and/or the semiconductor component 1.
Allowable Subject Matter
Claims 7 thru 9, and 15 thru 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The references of record, either singularly or in combination, do not teach or suggest at least a power semiconductor module arrangement comprising: further comprising a plurality of ribs extending from inner diameter of the sleeve towards a center of an opening defined by the sleeve, the ribs defining a reduced diameter in defined sections of the sleeve, wherein the reduced diameter is smaller than the inner diameter.
Regarding claim 8, the following is a statement of reasons for the indication of allowable subject matter: The references of record, either singularly or in combination, do not teach or suggest at least a power semiconductor module arrangement comprising: wherein at least one of the one or more holding pins comprises a collar arranged at the free end of the respective holding pin, an outer diameter of the holding pin is smaller than a smallest diameter of the holding element, and the collar is bent in a direction towards the substrate and smoothly adapts to an inner contour of the holding element.
Regarding claim 15, the following is a statement of reasons for the indication of allowable subject matter: The references of record, either singularly or in combination, do not teach or suggest at least a power semiconductor module arrangement comprising: wherein each of the one or more holding pins comprises an electrically conducting material but does not provide an electrical connection to any component inside the housing.
Regarding claim 16, the following is a statement of reasons for the indication of allowable subject matter: The references of record, either singularly or in combination, do not teach or suggest at least a power semiconductor module arrangement comprising: wherein each of the one or more holding pins comprises a plastic material.
Regarding claim 17, the following is a statement of reasons for the indication of allowable subject matter: The references of record, either singularly or in combination, do not teach or suggest at least a power semiconductor module arrangement comprising: wherein the free end of each of the one or more holding pins does not extend outside the housing.
Regarding claim 18, the following is a statement of reasons for the indication of allowable subject matter: The references of record, either singularly or in combination, do not teach or suggest at least a power semiconductor module arrangement comprising: wherein the housing solely comprises sidewalls and a cover.
Regarding claim 19, the following is a statement of reasons for the indication of allowable subject matter: The references of record, either singularly or in combination, do not teach or suggest at least a power semiconductor module arrangement comprising: wherein the power semiconductor module arrangement is configured to be attached to a base plate or heat sink, and wherein the force-fitting connection between the free end of each of the one or more holding pins and the respective holding element secures the substrate in a desired position with regard to the housing before the power semiconductor module arrangement is attached to the base plate or heat sink.
Response to Arguments
Regarding applicant’s arguments that the structure 7 is not a “housing”, this argument is not persuasive because the structure 7 simultaneously functions as an outer housing that protects the chip 1 as well as printed circuit board. Even though Bayerer labels the structure 7 as a printed circuit board, and has a material/functional role as such, the printed circuit board also has a simultaneous role, because of its structure and position, as a housing that serves as the top exterior surface of the complete semiconductor module arrangement that protects and encloses the chip 1. As shown in FIG. 3 of Bayerer, the printed circuit board 7 structurally acts as a housing by enclosing and protecting the chip from the outer environment. The structures 7 and 10 together serve as a housing for the semiconductor module arrangement. Even if Bayerer discloses the structure 7 being optional, it does not preclude the fact that when present, it physically serves as the most outer surface of the semiconductor module arrangement that protects and encloses the chip 1, and therefore, still qualifies, in a broadest reasonable interpretation, a “housing” in a power semiconductor module arrangement.
Regarding the applicant’s argument on the bottom of page 8 of the amendment filed
7/29/26, the Examiner is interpreting the structure 7 and 10 together as the “housing” as stated in the applicant’s claims. In FIG. 3, Bayerer discloses the free end 42 of the holding pin 4 being arranged inside the respective holding element 71 wherein the holding element 71 lines the edges of the housing 7 and descends into the sleeve 72, and, therefore, the free end 42 of the holding pin 4 forms a form-fitting connection with the holding element 71 within the top housing 7/10. See annotated FIG. 3 of Bayerer US 2014/0035118 A1 below.
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Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
INFORMATION ON HOW TO CONTACT THE USPTO
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Eugene Lee
September 13, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815
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