Prosecution Insights
Last updated: October 02, 2026
Application No. 18/386,456

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING LOW-K DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME

Non-Final OA §102
Filed
Nov 02, 2023
Priority
May 11, 2021 — CIP of 11/871,580
Examiner
NGUYEN, DAO H
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SanDisk Technologies Inc.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
1164 granted / 1274 resolved
+23.4% vs TC avg
Moderate +6% lift
Without
With
+5.7%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
40 currently pending
Career history
1294
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
35.8%
-4.2% vs TC avg
§102
54.5%
+14.5% vs TC avg
§112
5.8%
-34.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1274 resolved cases

Office Action

§102
DETAILED ACTION 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action is in response to the communications dated 06/26/2026. Claims 1-20 are pending in this application. Applicant made a provisional election without traverse to prosecute the invention of Group I, claims 1-15, is acknowledged. Claims 16-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected group there being no allowable generic or linking claim. Applicant has the right to file a divisional application covering the subject matter of the non-elected claims. Acknowledges 2. Receipt is acknowledged of the following items from the Applicant. Information Disclosure Statement (IDS) filed on 11/02/2023. The references cited on the PTOL 1449 form have been considered. Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609. Specification 3. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 5. Claims 1-3, and 10-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanaka et al. (US 2020/0051995) Regarding claim 1, Tanaka discloses a three-dimensional memory device, comprising: an alternating stack of insulating layers 32 and electrically conductive layers 246 & 46 (Fig. 20) located over a substrate 9, wherein the electrically conductive layers comprise word-line-level electrically conductive layers 46 and drain-select-level electrically conductive layers 246 overlying the word- line-level electrically conductive layers 46; an array of memory opening fill structures 58 located within an array of memory openings 49 (Fig. 4A) vertically extending through the alternating stack; and an encapsulated cavity 149’ (cavity 149’ in Figs. 19E is encapsulated by layers 150, 153, 603, and 63 in Fig. 19F, and filled by dielectric core 162 in Fig. 19H) vertically extending through the drain-select-level electrically conductive layers 246; wherein: the array of memory opening fill structures 58 comprises two rows of first memory opening fill structures 58 (along sidewalls of the drain-select-level isolation structure 272, fig. 8B) that are arranged along a first horizontal direction hd1; and each of the first memory opening fill structures 58 (along the sidewalls of the drain-select-level isolation structure 272, fig. 8B) comprises a respective planar straight sidewall in contact with a respective portion of a pair of straight sidewalls of the encapsulated (and filled) cavity 149’. Regarding claim 2, Taneka discloses the three-dimensional memory device of Claim 1, further comprising a cover dielectric liner 73 overlying the alternating stack, wherein the bottom surface of the cover dielectric liner 73 forms a planar top surface of the encapsulated cavity. See Fig. 20. Regarding claim 3, Taneka discloses the three-dimensional memory device of Claim 2, wherein the encapsulated cavity has a pair of lengthwise edges that laterally extend generally along a first horizontal direction. See Figs. 10F, 10G. Regarding claim 10, Tanaka discloses the three-dimensional memory device of Claim 1, wherein each of the first memory opening fill structures 58 comprises a memory film 54, a vertical semiconductor channel 160, and a dielectric core 62. See Figs. 10, 20, and para. 0142. Regarding claim 11, Tanaka discloses the three-dimensional memory device of Claim 10, wherein: each of the memory film 54, the vertical semiconductor channel 160, and the dielectric core 62 comprises a respective planar surface segment that laterally extends along the first horizontal direction and is in contact with the encapsulated cavity; and a bottom surface of the encapsulated cavity is located above the word-line-level electrically conductive layers. See Figs. 10, 19, 20. Regarding claim 12, Tanaka discloses the three-dimensional memory device of Claim 10, further comprising a contact-level dielectric layer 73 overlying the alternating stack and the array of memory opening fill structures. See fig. 20. Regarding claim 13, Tanaka discloses the three-dimensional memory device of Claim 12, wherein: each of the first memory opening fill structures 58 further comprises a drain region 63 that is contacted by a respective drain contact via structure 88 that extends through the contact- level dielectric layer 73; and the drain region 63 is in contact with the encapsulated cavity. See Figs. 19, 20. Regarding claim 14, Tanaka discloses the three-dimensional memory device of Claim 12, wherein: each of the first memory opening fill structures 58 comprises a drain region 63 that is contacted by a respective drain contact via structure 88 that extends through the contact-level dielectric layer 73; and a bottom surface of the drain region 63 overlies a horizontal plane including a top surface of the encapsulated cavity (filled by dielectric core 162). See Figs. 19, 20. Regarding claim 15, Tanaka discloses the three-dimensional memory device of Claim 1, wherein sidewalls of the drain-select- level electrically conductive layers 246 are in contact with the encapsulated cavity and wherein the encapsulated cavity (at void 169, Figs. 10) is free of any solid phase material therein. Allowable Subject Matter 6. Claims 4-9 are allowable. Claims 4-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed three-dimensional memory device (in addition to the other limitations in the claim) further comprising a contact-level dielectric layer overlying the alternating stack and the array of memory opening fill structures, wherein the cover dielectric liner comprises a horizontally-extending portion in contact with a top surface of the contact-level dielectric layer. Conclusion 7. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)). A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633. /DAO H NGUYEN/Primary Examiner, Art Unit 2818 August 6, 2026
Read full office action

Prosecution Timeline

Nov 02, 2023
Application Filed
Aug 11, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
97%
With Interview (+5.7%)
1y 11m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1274 resolved cases by this examiner. Grant probability derived from career allowance rate.

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