Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Examiner’s Comment – Independent Claim 1
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Sullivan et al. (5,355,422; “Sullivan”) in view of Yong et al. (Flip-chip integrated silicon Mach-Zehnder modulator with a 28nm fully depleted silicon-on-insulator CMOS driver, Opt. Express 25, 6112-6121, 2017; “Yong”) and further in view of Settaluri et al. (Demonstration of an optical chip-to-chip link in a 3D integrated electronic-photonic platform," ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), Graz, Austria, 2015, pp. 156-159; “Settaluri”).
Elections/Restriction
Applicant's election with traverse of claims 1-14 in the reply filed on 4 February 2026 is acknowledged. The traversal is on the ground(s) that ‘there exists considerable overlapping subject matter between claims 1 and 15.’ This is not found persuasive because method of manufacturing claim 15’ recites processes, for example, depositing and bonding, would require consideration and searching efforts not required to examine device claim 1.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 8, and 13-14
Claims 1-3, 8, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Sullivan et al. (5,355,422; “Sullivan”) in view of Yong et al. (Flip-chip integrated silicon Mach-Zehnder modulator with a 28nm fully depleted silicon-on-insulator CMOS driver, Opt. Express 25, 6112-6121, 2017; “Yong”) and further in view of Settaluri et al. (Demonstration of an optical chip-to-chip link in a 3D integrated electronic-photonic platform," ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), Graz, Austria, 2015, pp. 156-159; “Settaluri”).
Regarding claim 1, Sullivan discloses in figure 2, and related figures and text, for example, Sullivan – Selected Text, embodiments of a, “Broadband optical modulator 10 has a light waveguide 12 having modulator 14 for modulating light traveling down waveguide 12 as shown in FIG. 1. The total number of electrodes 14 in modulator 14 of FIG. 2 depends on the application and requirements of modulator 10. Each of the modulator electrodes 14 has one element connected to ground and the other element connected to a distributed amplifier driver 16. Driver 16 consists of a gate artificial transmission line 18, a plurality of discrete field effect transistors 20 and a drain artificial transmission line 22. Transistors 20 may be heterojunction bipolar transistors or any other device having equivalent functionality.” Sullivan, figure 2 and column 1, line 50 – column 2, line 9. And Sullivan discloses, “Transistors cannot be on lithium niobate but need to be on a semiconductor chip…Preferred substrate material for distributed amplifier driver 16 and optical modulators 14 is gallium arsenide. … The preferred composition, doping and thickness of the optical waveguide 12 layers depend on specific design requirements such as operating wavelength, mode size, and so forth, as is well known to those skilled in guided-wave optics.” Sullivan, column 3, lines 40-63.
Sullivan – Figure 2
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Sullivan – Selected Text
Abstract.
A broadband optical modulator having a light waveguide and modulating electrodes incorporated into an output or drain transmission line of a distributed amplifier driver. The modulator has a distributed gain mechanism which overcomes the electrical losses in the modulating electrodes and provides broadband velocity matching between the driving electrical signal and the modulated lightwave signal.
Column 1, line 50 – column 2, line 9
Broadband optical modulator 10 has a light waveguide 12 having modulator 14 for modulating light traveling down waveguide 12 as shown in FIG. 1. The total number of electrodes 14 in modulator 14 of FIG. 2 depends on the application and requirements of modulator 10. Each of the modulator electrodes 14 has one element connected to ground and the other element connected to a distributed amplifier driver 16. Driver 16 consists of a gate artificial transmission line 18, a plurality of discrete field effect transistors 20 and a drain artificial transmission line 22. Transistors 20 may be heterojunction bipolar transistors or any other device having equivalent functionality. Input or gate transmission line 18 consists of lumped inductors 24 and the input capacitances including gate-to-source capacitances of transistors 20. Output or drain transmission line 22 consists of lumped inductors 26 and the output capacitances including drain-to-source capacitances of transistors 20, and capacitances C.sub.m of waveguide modulator 14 electrode segments. Transmission lines 18 and 22 are essentially loaded constant-k lines, wherein the parasitic resistances of the transistors are considered the dominant loss factors. Lines 18 and 22 are terminated in their characteristic impedances at both ends whether the impedance be of a termination device or the impedance of an input or output device. Input or gate transmission line 18 and output or drain transmission line 22 are coupled through the transistors 20.
Column 3, lines 40-63
(10) Waveguide 12 and modulators 14 may be monolithically integrated with distributed amplifier 16. However, hybrid integration may be achieved for devices 12 and 16 provided that output transmission line 22 of distributed amplifier driver 16 has a plurality of connections to optical modulator elements 14. The modulator may be made of lithium niobate, or any other material in which the amplitude or phase of an optical wave propagating in the material may be affected by an impressed electrical signal, but the preferred embodiment is in gallium arsenide (GaAs). Transistors cannot be on lithium niobate but need to be on a semiconductor chip.
(11) Preferred substrate material for distributed amplifier driver 16 and optical modulators 14 is gallium arsenide. The preferred materials for optical waveguide 12 are alloys of gallium arsenide and aluminum arsenide, but other ternary materials or quaternary materials may also be used, depending on the defect densities, the refractive indices, and the optical nonlinearities. The preferred composition, doping and thickness of the optical waveguide 12 layers depend on specific design requirements such as operating wavelength, mode size, and so forth, as is well known to those skilled in guided-wave optics.
Further regarding claim 1, Yong discloses in figure 1, and related figures and text, embodiments of “[A] silicon electro-optic transmitter consisting of a 28nm ultra-thin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) CMOS driver flip-chip integrated onto a Mach-Zehnder modulator. The Mach-Zehnder silicon optical modulator was optimized to have a 3dB bandwidth of around 25 GHz at −1V bias and a 50 Ω impedance. The UTBB FD-SOI CMOS driver provided a large output voltage swing around 5 Vpp to enable a high dynamic extinction ratio and a low device insertion loss. At 44 Gbps, the transmitter achieved a high extinction ratio of 6.4 dB at the modulator quadrature operation point. This result shows open eye diagrams at the highest bit rates and with the largest extinction ratios for silicon electro-optic transmitter using a CMOS driver.” Yong, figure 1 and abstract (disclosing modulator waveguides vertically coupled to vertical ground and signal metal electrodes). Yong, figure 1 and related figures and text.
Yong – Figure 1
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Consequently, in light of Yong’s disclosure of vertical metallic electrode connections, it would have been obvious to one of ordinary skill in the art to modify Sullivan’s embodiments of electro-optical modulator assemblies to disclose: a transistor including a gate, a drain, a source, and a film forming a channel layer for the transistor disposed on a substrate; a photonic modulator including a first waveguide structure positioned between a first electrode and a second electrode, the photonic modulator including a portion disposed over a portion of the transistor; and a metal connection coupled between the drain of the transistor and one of the first and second electrodes of the photonic modulator; Sullivan, figure 2, and related figures and text, for example, Sullivan – Selected Text; Yong, figure 1 and related figures and text; because the resulting configuration would facilitate designing, fabricating, and deploying high density ‘wafer-scale heterogeneous platforms, where the photonics and CMOS chips are 3D integrated using wafer bonding and low-parasitic capacitance thru-oxide vias (TOVs).’ Settaluri, figure 1, and related figures and text, for example, Settaluri – Selected Text (“300mm photonic and electronic wafers are manufactured separately in CNSE 300mm foundry and then bonded face-to-face using oxide bonding”).
Settaluri – Figure 1
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Settaluri – Selected Text
Abstract—A full optical chip-to-chip link is demonstrated for the first time in a wafer-scale heterogeneous platform, where the photonics and CMOS chips are 3D integrated using wafer bonding and low-parasitic capacitance thru-oxide vias (TOVs). This development platform yields 1000s of functional photonic components as well as 16M transistors per chip module. The transmitter operates at 6Gb/s with an energy cost of 100fJ/bit and the receiver at 7Gb/s with a sensitivity of 26μA (-14.5dBm) and 340fJ/bit energy consumption. A full 5Gb/s chip-to-chip link, with the on-chip calibration and self-test, is demonstrated over a 100m single mode optical fiber with 560fJ/bit of electrical and 4.2pJ/bit of optical energy.
II. 3D INTEGRATION OF CMOS AND PHOTONICS
Traditional heterogeneous platforms capitalize on the ability to individually optimize the photonic and electronic macros, an element missing in other forms of integration. However, the large interface capacitance associated with thru silicon via (TSV) and μ-bump technologies limits the overall system performance as well as energy-efficiency.
As illustrated in Fig. 1, in this process, 300mm photonic and electronic wafers are manufactured separately in CNSE 300mm foundry and then bonded face-to-face using oxide bonding. The silicon substrate is then removed on the photonic SOI wafer and TOVs are punched through at 4μm pitch to connect the top layer metal of the photonic wafer to the top layer metal on the 65nm bulk CMOS wafer.
For packaging, wire-bonded back metal pads are deposited on top of the selected TOVs. The connection from the CMOS wafer to the photonic device is achieved through the TOVs passivated on top with an oxide layer, which minimizes the parasitic capacitance. Our measurements estimate the TOV capacitance to be ~3fF, which enables low-power and high sensitivity electronic-photonic systems for a variety of applications. This represents an order of magnitude reduction in parasitic capacitance, and two orders of magnitude higher density compared to previously demonstrated μ-bump flip-chip electronic-photonic integration.
Regarding dependent claims 2-3, 8, and 13-14, it would have been obvious to one of ordinary skill in the art to modify Sullivan in view of Yong and further in view of Settaluri, as applied in the rejection of claim 1, to disclose:
2. The electro-optical modulator assembly of claim 1, wherein the metal connection extends in a vertical path having a first end at the drain of the transistor and a second end at the one of the first and second electrodes of the photonic modulator. Sullivan, figure 2, and related figures and text, for example, Sullivan – Selected Text; Yong, figure 1 and related figures and text; Settaluri, figure 1, and related figures and text, for example, Settaluri – Selected Text.
3. The electro-optical modulator assembly of claim 1, wherein a first oxide layer disposed on a top side of the transistor is bonded to a second oxide layer disposed on one side of the photonic modulator. Sullivan, figure 2, and related figures and text, for example, Sullivan – Selected Text; Yong, figure 1 and related figures and text; Settaluri, figure 1, and related figures and text, for example, Settaluri – Selected Text.
8. The electro-optical modulator assembly of claim 1, wherein the photonic modulator is configured as a Mach-Zehnder interferometer (MZI) modulator and includes a second waveguide structure positioned outside the first and second electrodes. Sullivan, figure 2, and related figures and text, for example, Sullivan – Selected Text; Yong, figure 1 and related figures and text; Settaluri, figure 1, and related figures and text, for example, Settaluri – Selected Text.
13. The electro-optical modulator assembly of claim 1, wherein the photonic modulator is disposed on the film forming the channel layer for the transistor. Sullivan, figure 2, and related figures and text, for example, Sullivan – Selected Text; Yong, figure 1 and related figures and text; Settaluri, figure 1, and related figures and text, for example, Settaluri – Selected Text.
14. The electro-optical modulator assembly of claim 1, wherein the first waveguide structure is formed on a lower side of a slab of LiNbO.sub.3, the lower side of the slab of LiNbO.sub.3 facing the transistor. Sullivan, figure 2, and related figures and text, for example, Sullivan – Selected Text; Yong, figure 1 and related figures and text; Settaluri, figure 1, and related figures and text, for example, Settaluri – Selected Text.
because the resulting configurations would facilitate designing, fabricating, and deploying high density ‘wafer-scale heterogeneous platforms, where the photonics and CMOS chips are 3D integrated using wafer bonding and low-parasitic capacitance thru-oxide vias (TOVs).’ Settaluri, figure 1, and related figures and text, for example, Settaluri – Selected Text
Claims 4 and 9-11
Claims 4 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Sullivan et al. (5,355,422; “Sullivan”) in view of Yong et al. (Flip-chip integrated silicon Mach-Zehnder modulator with a 28nm fully depleted silicon-on-insulator CMOS driver, Opt. Express 25, 6112-6121, 2017; “Yong”) and further in view of Settaluri et al. (Demonstration of an optical chip-to-chip link in a 3D integrated electronic-photonic platform," ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), Graz, Austria, 2015, pp. 156-159; “Settaluri”), as applied in the rejection claims 1-3, 8, and 13-14, and further in view of Kato, Tomoaki (2012/0251032; “Kato”).
Regarding claims 4-9, Kato discloses in figures 1-12, and related text, for example, Kato – Selected Text, embodiments of optical modulators characterized by lithium niobate waveguides and modulation frequency bands exceeding 100 GHz. Kato, figures 1-12 and related text, for example, Kato – Selected Text.
Kato – Selected Text
[0004] In an optical transmitter for such a high-capacity wavelength-division multiplexing communication system, an optical modulator is required. In the optical modulator, high speed operation with small wavelength dependence is indispensable. Further, an unwanted optical phase modulation component which degrades the waveform of the received optical signal after long-distance transmission (in the case of using optical intensity modulation as a modulation method), or an optical intensity modulation component (in the case of using optical phase modulation as a modulation method) should be suppressed as small as possible. A Mach-Zehnder (MZ) optical intensity modulator in which waveguide-type optical phase modulators are embedded into an optical waveguide-type MZ interferometer is suitable for such a use. In general, a currently used MZ optical intensity modulator is based on a so-called planar waveguide circuit in which titanium is diffused into the surface of a lithium niobate (LN: LiNbO.sub.3) substrate which is a typical electro-optic crystal having a refractive index that changes in proportion to an applied electric field. A typical MZ interferometer has a configuration in which waveguide-type optical phase modulator regions and optical waveguide-type multiplexer/demultiplexer regions are monolithically integrated on the same LN substrate. Further, electrodes for applying the electric field to the waveguide-type optical phase modulator are provided in the waveguide-type optical phase modulator.
[0066] Thus, when the segmented waveguide-type optical phase modulator regions 14 have a small capacitance and are each regarded as a lumped-constant circuit element (lumped-constant type optical modulator) and when the lines connecting the individual driving circuits 21 and the waveguide-type optical phase modulator regions 14 are sufficiently shorter than a propagating wavelength at a frequency of a modulation electric signal, the degree of freedom of each of the value of the termination resistor and the formation position thereof can be increased. As for the resistance value, for example, if the required frequency band is 50 GHz and the frequency band estimated from a CR product at a termination of 50.OMEGA. can be set to 100 GHz, which is a value twice as large as the required value, when the resistance value of the terminator is doubled, i.e., 100.OMEGA., the output voltage amplitude can be doubled assuming that the output current from the output-stage transistor of each driving circuit is the same. Additionally, the drive current can be suppressed to 1/2 while maintaining the same driving voltage. In the former case, a reduction in the operation current density of the output-stage transistors leads to a high reliability. In the latter case, miniaturization of the output-stage transistors leads to a high-speed operation due to a reduction in element capacitance, and the margin of the operation speed can also be applied to one of these. Furthermore, a Joule loss (that is, heat generation) in the terminator is in proportion to a square of a drive current and a resistance. Accordingly, when the drive current is reduced by half, the calorific value can be suppressed to 1/2. Obviously, this is favorable in terms of reliability for the elements forming the driving circuit. Moreover, a mode can be implemented in which a terminator is directly formed on a driving IC or an optical modulator (a so-called on-chip terminal), which is advantageous in terms of high-frequency characteristics but cannot be conventionally adopted because of a concern about temperature characteristics. This is advantageous in terms of improvement in high-frequency characteristics. On the other hand, the terminator can be effectively treated as lumped element. Accordingly, even when the terminator is disposed on the individual driving circuit or the optical modulator or in the middle of these circuits, the effect of this position on the frequency response characteristic can be suppressed to a level low enough to be practically negligible. As a result, the degree of freedom of the module implementation form can be increased in terms of circuit configuration.
[0070] When each of the segmented electrodes (optical modulator regions) can be regarded as a lumped element (lumped type optical modulator), a measure of the modulation frequency band thereof is generally given by the product (CR product) of the capacitance of the optical modulator region and the resistance of the terminator. According to an exemplary aspect of the present invention, this capacitance decreases substantially in inverse proportion to the number of the segmented regions. Therefore, a modulation frequency band of more than 100 GHz seems to be relatively easily achieved in each of the segmented optical modulator regions, which is advantageous in terms of high-speed operation.
[0071] Furthermore, as described above, a reduction in driving voltage amplitude can be achieved, thereby enabling production of a driving circuit using a semiconductor process technology, which has a low voltage amplitude but is excellent in mass production, high uniformity, and high integration of CMOS-IC (Complementary Metal Oxide Semiconductor-Integrated Circuit), SiGe-HBT (Heterojunction Bipolar Transistor)-IC, and the like. Therefore, the present invention is advantageous in terms of smaller size, lower cost, lower power consumption, and the like, as compared to the case of using the existing driving circuit which is based on a III-V compound semiconductor such as GaAs or InP and which has a higher driving voltage and is inferior in mass production and high integration while achieving a high-speed operation. Moreover, light source elements can be highly integrated to reduce the number of components, which leads to a further reduction in cost.
Consequently, it would have been obvious to one of ordinary skill in the art to modify Sullivan in view of Yong and further in view of Settaluri’s embodiments, as applied in the rejection of claim 1-3, 8, and 13-14, to disclose:
4. The electro-optical modulator assembly of claim 1, wherein the transistor is arranged in proximity to the photonic modulator to minimize a length of the metal connection and enable operation of the photonic modulator at frequencies up to and above 100 GHz. Sullivan, figure 2, and related figures and text, for example, Sullivan – Selected Text; Yong, figure 1 and related figures and text; Settaluri, figure 1, and related figures and text, for example, Settaluri – Selected Text; Kato, figures 1-12 and related text, for example, Kato – Selected Text.
9. The electro-optical modulator assembly of claim 8, wherein the first and second waveguide structures are fabricated from at least one of Lithium Niobate (LiNbO.sub.3) and Silicon Nitride (SiN) and configured to propagate an optical energy signal. Sullivan, figure 2, and related figures and text, for example, Sullivan – Selected Text; Yong, figure 1 and related figures and text; Settaluri, figure 1, and related figures and text, for example, Settaluri – Selected Text; Kato, figures 1-12 and related text, for example, Kato – Selected Text.
10. The electro-optical modulator assembly of claim 9, wherein the transistor is configured to receive a radio-frequency signal at the gate and to provide a modulation voltage to one of the first and second electrodes via the metal connection to induce a phase shift in the optical energy signal of the first waveguide structure. Sullivan, figure 2, and related figures and text, for example, Sullivan – Selected Text; Yong, figure 1 and related figures and text; Settaluri, figure 1, and related figures and text, for example, Settaluri – Selected Text; Kato, figures 1-12 and related text, for example, Kato – Selected Text.
11. The electro-optical modulator assembly of claim 10, wherein the optical energy signal of the first waveguide structure is combined with the optical energy signal of the second waveguide structure to provide an optical signal having an amplitude modulation corresponding to the radio-frequency signal received at the gate of the transistor. Sullivan, figure 2, and related figures and text, for example, Sullivan – Selected Text; Yong, figure 1 and related figures and text; Settaluri, figure 1, and related figures and text, for example, Settaluri – Selected Text; Kato, figures 1-12 and related text, for example, Kato – Selected Text.
because the resulting configurations would facilitate designing, fabricating, and deploying high density ‘wafer-scale heterogeneous platforms, where the photonics and CMOS chips are 3D integrated using wafer bonding and low-parasitic capacitance thru-oxide vias (TOVs);’ Settaluri, figure 1, and related figures and text, for example, Settaluri – Selected Text; that are characterized by smaller size, lower cost, lower power consumption. Kato, paragraph [0071].
Claims 5-7
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Sullivan et al. (5,355,422; “Sullivan”) in view of Yong et al. (Flip-chip integrated silicon Mach-Zehnder modulator with a 28nm fully depleted silicon-on-insulator CMOS driver, Opt. Express 25, 6112-6121, 2017; “Yong”) and further in view of Settaluri et al. (Demonstration of an optical chip-to-chip link in a 3D integrated electronic-photonic platform," ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), Graz, Austria, 2015, pp. 156-159; “Settaluri”), as applied in the rejection claims 1-3, 8, and 13-14, and further in view of Lerner et al. (Flexible and Scalable Heterogeneous Integration of GaN HEMTs on Si-CMOS by Micro-Transfer-Printing. Phys. Status Solidi A, 215: 1700556.; “Lerner”).
Regarding claims 5-7, Lerner discloses in figures 1-11, and related text, “Tomorrow’s power electronic systems require cost-saving and more efficient power conversion solutions. The heterogeneous integration of GaN-based high electron mobility transistors (HEMTs) together with silicon CMOS by micro- Transfer-Printing could be a key technology for this. It enables the integration of highly integrated mature CMOS logic functionality with fast GaN HEMT output drivers with very low on-state and switching losses. The scalability by design measures of the printed HEMT is investigated in terms of drain-to-gate spacing and channel width defining breakdown voltage and area-related parameters like on-resistance. The design flexibility of the micro-Transfer-Printing by printing the HEMTs on top of the CMOS devices without restrictive design rule limits is investigated by CMOS DC parameter comparison and thermal TCAD Design Of Experiment (DOE) study. No electrical or thermal functional limitation of printing the HEMTs directly on top of the CMOS dielectric layer stack was found. This enables the usage of the isolation capabilities of the CMOS dielectric layer stack to enhance the HEMT breakdown voltage.” Lerner, abstract.
Consequently, it would have been obvious to one of ordinary skill in the art to modify Sullivan in view of Yong and further in view of Settaluri’s embodiments, as applied in the rejection of claim 1-3, 8, and 13-14, to disclose:
5. The electro-optical modulator assembly of claim 1, wherein the transistor is a III-Nitride transistor. Sullivan, figure 2, and related figures and text, for example, Sullivan – Selected Text; Yong, figure 1 and related figures and text; Settaluri, figure 1, and related figures and text, for example, Settaluri – Selected Text; Lerner, figures 1-11 and related text.
6. The electro-optical modulator assembly of claim 5, wherein the transistor is a III-Nitride High-Electron-Mobility Transistor (HEMT). Sullivan, figure 2, and related figures and text, for example, Sullivan – Selected Text; Yong, figure 1 and related figures and text; Settaluri, figure 1, and related figures and text, for example, Settaluri – Selected Text; Lerner, figures 1-11 and related text.
7. The electro-optical modulator assembly of claim 1, wherein the substrate is one of a Silicon (Si) substrate and a Silicon Carbide (SiC) substrate. Sullivan, figure 2, and related figures and text, for example, Sullivan – Selected Text; Yong, figure 1 and related figures and text; Settaluri, figure 1, and related figures and text, for example, Settaluri – Selected Text; Lerner, figures 1-11 and related text.
because the resulting configurations would facilitate designing, fabricating, and deploying high density ‘wafer-scale heterogeneous platforms, where the photonics and CMOS chips are 3D integrated using wafer bonding and low-parasitic capacitance thru-oxide vias (TOVs);’ Settaluri, figure 1, and related figures and text, for example, Settaluri – Selected Text; that are characterized by enhanced breakdown voltages. Lerner, abstract.
Claim 12
Claim 12, as dependent upon claim 8, is rejected under 35 U.S.C. 103 as being unpatentable over Sullivan et al. (5,355,422; “Sullivan”) in view of Yong et al. (Flip-chip integrated silicon Mach-Zehnder modulator with a 28nm fully depleted silicon-on-insulator CMOS driver, Opt. Express 25, 6112-6121, 2017; “Yong”) and further in view of Settaluri et al. (Demonstration of an optical chip-to-chip link in a 3D integrated electronic-photonic platform," ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), Graz, Austria, 2015, pp. 156-159; “Settaluri”), as applied in the rejection claims 1-3, 8, and 13-14, and further in view of Chang et al. (Thin film wavelength converters for photonic integrated circuits, Optica 3, 531-535 (2016); “Chang”).
Regarding claim 12, Chang discloses in figure 2, and related figures and text, SiN waveguides disclosed on LN slabs. Chang, 2. Fabrication (“Due to the high index contrast structure (∼0.6) and the submicrometer thickness of the LN film, the waveguide modes are confined into an area that is more than one order of magnitude smaller than that obtained with proton exchange or with Ti in-diffusion [10]. This directly relates to more than an extra order of magnitude improvement for the efficiency of nonlinear effects … For both modes, over 90% of the power is confined in the LN film.”
Consequently, it would have been obvious to one of ordinary skill in the art to modify Sullivan in view of Yong and further in view of Settaluri’s embodiments, as applied in the rejection of claim 1-3, 8, and 13-14, to disclose that at least one of the first and second waveguide structures are fabricated from a SiN film disposed on a slab of LiNbO.sub.3; Chang, figure 2; because the resulting configuration would facilitate designing, fabricating, and deploying high density ‘wafer-scale heterogeneous platforms, where the photonics and CMOS chips are 3D integrated using wafer bonding and low-parasitic capacitance thru-oxide vias (TOVs);’ Settaluri, figure 1, and related figures and text, for example, Settaluri – Selected Text; that are characterized by enhanced mode confinement. Chang, 2. Fabrication.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER RADKOWSKI whose telephone number is (571)270-1613. The examiner can normally be reached on M-Th 9-5. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hollweg, can be reached on (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/PETER RADKOWSKI/Primary Examiner, Art Unit 2874
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