DETAILED ACTION
This is the Office action based on the 18386520 application filed November 2, 2023, and in response to applicant’s argument/remark filed on January 16, 2024. Claims 2-21 are currently pending and have been considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claim 9 objected to because of the following informalities: -the phrase “removing portions of the third conductive material to form a word line that that extends in a first direction parallel to the plane” appears to contain a typographical error. For the purpose of examining it will be assumed that this phrase is “removing portions of the third conductive material to form a word line that extends in a first direction parallel to the plane”. Appropriate correction is required.-the phrase “removing portions of the fourth conductive material to form a bit line that that extends in a second direction parallel to the plane” appears to contain a typographical error. For the purpose of examining it will be assumed that this phrase is “removing portions of the fourth conductive material to form a bit line that extends in a second direction parallel to the plane”. Appropriate correction is required.
Claim Interpretations
Claim 1 recites “A method, comprising:
forming a substrate; and
forming, from a chalcogenide material deposited above the substrate, a self- selecting storage element…” for the purpose of examining this will be interpreted that the method comprises a step of depositing the chalcogenide material above the substrate after the forming the substrate and before the forming the self- selecting storage element.
Claim 9 recites the limitation “removing portions of the third conductive material to form a word line that that extends in a first direction parallel to the plane” and “removing portions of the fourth conductive material to form a bit line that that extends in a second direction parallel to the plane” (emphasis added). Since claim 9 does not recite any actual forming the word line or the bit line, or using the remaining portion as a word line or a bit line, for the purpose of examining the phrase “to form a word line” and “to form a bit line” will be interpreted as an intention, and may or may not occur.
Claim 12 recites the limitation “increasing the duration of the etching to increase a width of the sidewall region, decrease a width of the bulk region, or both” (emphasis added). Since claim 12 does not recite any actual increase a width of the sidewall region or decrease of the width of the bulk region, for the purpose of examining the phrase “to increase a width of the sidewall region, decrease a width of the bulk region, or both” will be interpreted as an intention, and may or may not occur.
Claim 19 recites the limitation “increasing the duration of the cleaning to increase a width of the sidewall region” (emphasis added). Since claim 19 does not recite any actual increase a width of the sidewall region, for the purpose of examining the phrase “to increase a width of the sidewall region” will be interpreted as an intention, and may or may not occur.
Claim 20 recites the limitation “increasing the duration of the doping to increase a width of the sidewall region” (emphasis added). Since claim 20 does not recite any actual increase a width of the sidewall region, for the purpose of examining the phrase “to increase a width of the sidewall region” will be interpreted as an intention, and may or may not occur.
Claim 21 recites the limitation “increasing the temperature of the temperature-treating, the duration of the temperature-treating, or both to increase a structural integrity, resistivity, or both, of the sidewall region” (emphasis added). Since claim 21 does not recite any actual increase a structural integrity or resistivity of the sidewall region, for the purpose of examining the phrase “to increase a structural integrity, resistivity, or both, of the sidewall region” will be interpreted as an intention, and may or may not occur.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-10 and 18 rejected under 35 U.S.C. 103 as being obvious over Redaelli et al. (U.S. PGPub. No. 20180315475), hereinafter “Redaelli”, in view of Hu et al. (U.S. PGPub. No. 20170358629), hereinafter “Hu” :--Claim 2: Redaelli teaches a method of fabricating a self-selecting memory device (abstract, [0013-0014]), comprising (Fig. 6)(i) forming a first conductive material layer 805 on a substrate (Fig. 8, [0087]);(ii) forming a second conductive layer 810 on the first conductive material layer 805 ([0088]);(iii) forming a chalcogenide layer 815 on the second conductive layer 810 ([0088]);(iv) forming a third conductive layer 820 on the chalcogenide layer 815 to form a stack (Fig. 8, [0083, 0088]); (v) etching the above stack to form a plurality of memory components ([0084, 0089]); (vi) filling the spaces between the components with a dielectric material 830 ([0090], drawings 800-b in Fig. 8), thus forming the self-selecting memory device;(vii) forming a fourth conductive layer 825 on the third conductive material layer 820 ([0090], drawing 800-c in Fig. 8); (viii) applying a voltage to either the fourth conductive layer 825 or the first conductive material layer 805, the voltage causes ions within the chalcogenide layer 815 to migrate to either the bottom portion or the top portion of the chalcogenide layer 815 ([0091-0094], Fig. 9, drawings 105-d or 105-e in Fig. 3, [0051-0055]) Redaelli further teaches that the second and third conductive layer may be carbon ([0088]). Redaelli fails to teach the claimed feature “a self-selecting storage element comprising a bulk region and a sidewall region that extend between the first conductive material and the second conductive material, the bulk region comprising at least a first portion of the chalcogenide material having a first composition and the sidewall region comprising at least a second portion of the chalcogenide material having a second composition that is different than the first composition”. Hu, also directed to a method of fabricating a phase change memory device comprising a chalcogenide storage element ([0002-0003]) comprising etching a stack comprising a chalcogenide sandwiched between two carbon conductive layer to form a plurality of memory components (Fig. 2 and 3, [0014-0018]), then filling dielectric materials between the components (Fig. 6, [0023]), teaches that the carbon conductive layers are chemically inert, thus may cause poor adhesion to the dielectric material, resulting in reliability issues ([0009-0010]). Hu teaches to remedy this problem by treating the sidewall of the memory component stack with an adhesion species ([0011]), comprising implanting the adhesion species into the sidewall by using a low-energy plasma immersion technique, such as by using a plasma comprises BF3 and a carrier gas to implant boron as the adhesion species ([0019-0021], Fig. 4). Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention of Redaelli to modify step (v) to include an implanting adhesion species into the sidewall of the memory components subsequent to the etching in the invention of Redaelli because Hu teaches that this would prevent poor adhesion of the dielectric material 830 on the sidewall that would cause reliability issue. It is noted that the implantation of the adhesive species on the sidewall of the chalcogenide layer 815 would form a peripheral portion adjacent to the sidewall having a composition different than the composition at the center portion.--Claim 3: It is noted that each of the first conductive layer and the second conductive layer contacts both the center portion and the peripheral portion of the chalcogenide layer (Fig. 2 and 3 of Redaelli)..--Claim 4: Redaelli further teaches that the etching the stack is performed such that the resulting memory components have an asymmetric shape in a first direction and a symmetric shape in a second direction, and the chalcogenide material to have a first orientation or a second orientation, by using wet etch, plasma etch and/or CMP ([0084-0085]). Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to perform the etching such that a width of the sidewall region is based at least in part on the etching process, or such that a first portion, second portion, third portion or fourth portion of the sidewall is based at least in part on the etching process because it’s been well established that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”. MPEP 2144.05(II)(A).--Claims 5, 7: It is noted that Redaelli modified by Hu teaches a method of doping the exposed surface of the chalcogenide material for a duration of time by using a plasma comprising an adhesion species, such as BF3 and a carrier gas, to form a doped peripheral region to improve adhesion, wherein the boron species is implanted into the chalcogenide layer. Since the implanting the adhesion species into the sidewall may comprise bombarding the sidewall of the stack with ions of BF3 and of the carrier gas, it may be considered a clean step. Since the bombarding would change a temperature of the sidewall region, the implanting the adhesion species into the sidewall may be considered a temperature treating step. It is noted that the amount or concentration of the implant species in the sidewall region is based on the duration of the implant step. Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to adjust the duration of the implant to optimize a concentration of dopant species in the chalcogenide layer because it’s been well established that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”. MPEP 2144.05(II)(A).--Claim 6: Since the depth of implantation depends on the size of the implant species; therefore, a concentration of the implant species at the peripheral portion is based on the type/size of the implant species.--Claim 8: Redaelli further teaches that the etching the stack is performed such that the resulting memory components have an asymmetric shape in a first direction and a symmetric shape in a second direction, and the chalcogenide material to have a first orientation or a second orientation, by using wet etch, plasma etch and/or CMP ([0084-0085]).--Claim 9: It is noted that claim 9 does not recite that a word line or a bit line is actually formed, i.e. “to form a word line” or “to form a bit line” is interpreted as an intention. Nevertheless, Redaelli teaches that the fourth conductive layer (label 115 in Fig. 2) may be representative of a bit line, and that the first conductive layer (label 110-a in Fig. 2) may be representative of a word line ([0085, 0029], Fig. 2), and that “(b)it lines 115-a may then be formed, for example, by depositing a layer of material and selectively etching to form the line structure depicted in FIG. 2” ([0046]). It is noted that the first conductive layers have a portion removed during the modified step (v). It is noted that the bit line 115-a extends in a first direction parallel to the substrate and the word line 110-a extends in a second direction parallel to the substrate (Fig. 2).--Claim 10: Fig. 2 and Fig. 3 show that a width of the bit line 115-a and 205-c is about equal to a first width of the chalcogenide layer in a first direction and a width of the word line 110-a and 210-c is about equal to a second width of the chalcogenide layer in a second direction. Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to perform the modified step (v) so that a first portion and a second portion, opposite from the first portion, of the peripheral portion are based on the word line 110-a, and a third portion and a fourth portion, opposite from the third portion, of the peripheral portion are based on the bit line 115-a. It is noted that since the chalcogenide layer is symmetrical in the lateral direction, a width,
stability, resistivity, and composition of the first portion of the sidewall region and the second portion of the sidewall region being equivalent, and a width, stability, resistivity, and composition of the third portion of the sidewall region and the fourth portion of the sidewall region being equivalent--Claim 18: It is noted that Redaelli modified by Hu teaches a method of doping the exposed surface of the chalcogenide material for a duration of time by using a plasma comprising BF3 and a carrier gas to form a doped peripheral region to improve adhesion. It would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to adjust a duration of the doping such that an optimum amount of doping is included in the peripheral region because it’s been well established that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”. MPEP 2144.05(II)(A). Since the implanting the adhesion species into the sidewall comprise bombarding the sidewall of the stack with ions of BF3 and of the carrier gas, it may be considered a clean step. Since the bombarding would change a temperature of the sidewall region, the implanting the adhesion species into the sidewall may be considered a temperature treating step. It is noted that the modified step (v) comprises the sequence etching/doping, and may be considered an etching or a cleaning step. Alternately, it is noted that the composition of the peripheral portion is inherent. It is noted that claim 18 does not recite any particular value for the composition for the peripheral region other than it is different than the composition in the bulk region. Any modified step (v) would obtain a composition of the peripheral portion.
Claims 19-21 rejected under 35 U.S.C. 103 as being obvious over Redaelli in view of Hu as applied to claim 18 above, and further in view of Collins et al. (U.S. PGPub. No. 20060081558), hereinafter “Collins”:--Claims 19, 20, 21: Redaelli modified by Hu teaches the invention as in claim 18. Redaelli and Hu fail to teach the claimed feature increasing the duration of the etching or doping to increase a width or structural integrity of the sidewall region. It is noted that since the implanting the adhesion species into the sidewall may comprise bombarding the sidewall of the stack with ions of BF3 and of the carrier gas, it may be considered a clean step. Since the bombarding would change a temperature of the sidewall region, the implanting the adhesion species into the sidewall may be considered a temperature treating step. Collins, also directed to a method of doping by using BF3 by using plasma immersion, teaches that an immersion time of 60 seconds would yield a sheet resistance about 1200 ohms/square, and the implant time may be adjusted up or down to optimize the sheet resistance ([0099]). Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to use plasma immersion method taught by Collins in the invention of Redaelli modified by Hu because Hu is silent about a details of the plasma immersion method and Collins teaches that this method would be effective. It would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to increase an implant time to enable more dopant species to be included in the sidewall portion because Hu teaches that this would improve adhesion of dielectric materials. It is noted that this would also increase the width and the structural integrity of the sidewall portion. It is also noted that the increasing a width of the sidewall region in claims 19-20, and the increase in the structural integrity recited in claim 21 are interpreted an intention (see Claim Interpretations)
Claims 2-11 and 13-18 rejected under 35 U.S.C. 103 as being obvious over Redaelli in view of Lee et al. (U.S. PGPub. No. 20050040136), hereinafter “Lee” :--Claims 2, 11, 16, 17: Redaelli teaches a method of fabricating a self-selecting memory device (abstract, [0013-0014]), comprising (Fig. 6)(i) forming a first conductive material layer 805 on a substrate (Fig. 8, [0087]);(ii) forming a second conductive layer 810 on the first conductive material layer 805 ([0088]);(iii) forming a chalcogenide layer 815 on the second conductive layer 810 ([0088]);(iv) forming a third conductive layer 820 on the chalcogenide layer 815 to form a stack (Fig. 8, [0083, 0088]); (v) etching the above stack to form a plurality of memory components ([0084, 0089]); (vi) filling the spaces between the components with a dielectric material 830 ([0090], drawings 800-b in Fig. 8), thus forming the self-selecting memory device;(vii) forming a fourth conductive layer 825 on the third conductive material layer 820 ([0090], drawing 800-c in Fig. 8); (viii) applying a voltage to either the fourth conductive layer 825 or the first conductive material layer 805, the voltage causes ions within the chalcogenide layer 815 to migrate to either the bottom portion or the top portion of the chalcogenide layer 815 ([0091-0094], Fig. 9, drawings 105-d or 105-e in Fig. 3, [0051-0055]) Redaelli further teaches that the second and third conductive layer may be carbon ([0088]). Redaelli fails to teach the claimed feature “a self-selecting storage element comprising a bulk region and a sidewall region that extend between the first conductive material and the second conductive material, the bulk region comprising at least a first portion of the chalcogenide material having a first composition and the sidewall region comprising at least a second portion of the chalcogenide material having a second composition that is different than the first composition”. Redaelli further teaches that the chalcogenide may be Ge-Sb-Te alloy ([0102]), and the etching the stack is performed such that the resulting memory components have an asymmetric shape in a first direction and a symmetric shape in a second direction, and the chalcogenide material to have a first orientation or a second orientation, by using wet etch, plasma etch and/or CMP, and that one or more etching steps may be employed ([0084-0085]), but is silent about the process parameters of the etching. Lee, also directed to a method of plasma etching a stack comprising a chalcogenide layer, such as Ge-Sb-Te alloy (abstract), teaches that the chalcogenide layer may be etched by using a plasma comprising BCl3 (Claims 1, 2 and 8). Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention to etch the chalcogenide layer by using a plasma comprising BCl3 in the invention of Redaelli because Redaelli is silent about the details of the plasma etching and Lee teaches that such method would be effective. It is noted that such plasma etching would expose the chalcogenide layer to a plasma generated from BCl3, causing at least some of the boron ions or radicals to be implanted into the sidewall surface of the component, i.e. doping, as evidenced by Hu ([0019-0021], Fig. 4), resulting in a peripheral portion of the chalcogenide layer comprising a different amount of boron atoms than a center portion of the chalcogenide layer.--Claim 3: It is noted that each of the first conductive layer and the second conductive layer contacts both the center portion and the peripheral portion of the chalcogenide layer (Fig. 2 and 3 of Redaelli).--Claim 4: Redaelli further teaches that the etching the stack is performed such that the resulting memory components have an asymmetric shape in a first direction and a symmetric shape in a second direction, and the chalcogenide material to have a first orientation or a second orientation, by using wet etch, plasma etch and/or CMP ([0084-0085]). Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to perform the etching such that a width of the sidewall region is based at least in part on the etching process, or such that a first portion, second portion, third portion or fourth portion of the sidewall is based at least in part on the etching process because it’s been well established that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”. MPEP 2144.05(II)(A).--Claim 5, 7: It is noted that step (v) comprises doping the peripheral portion of the chalcogenide layer by the boron ions in the plasma. Since the plasma etching removes materials from the stack, it may be considered a clean step. Since contacting the plasma would change a temperature of the chalcogenide layer, the plasma etching may be considered a temperature treating step. It is noted that a duration of exposure to the plasma comprising boron would affect the concentration of the boron species penetrating into the chalcogenide layer. Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to adjust a duration of the etching to optimize a concentration of dopant species in the chalcogenide layer because it’s been well established that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”. MPEP 2144.05(II)(A).--Claim 6: Since the depth of peripheral portion, i.e. a penetration depth of the dopants, depends on the size of the doping species; therefore, a concentration of the doping species at the peripheral portion is based on the type/size of the doping species.--Claim 8: Redaelli further teaches that the etching the stack is performed such that the resulting memory components have an asymmetric shape in a first direction and a symmetric shape in a second direction, and the chalcogenide material to have a first orientation or a second orientation, by using wet etch, plasma etch and/or CMP ([0084-0085]).--Claim 9: It is noted that claim 9 does not recite that a word line or a bit line is actually formed, i.e. “to form a word line” or “to form a bit line” is interpreted as an intention. Nevertheless, Redaelli teaches that the fourth conductive layer (label 115 in Fig. 2) may be representative of a bit line, and that the first conductive layer (label 110-a in Fig. 2) may be representative of a word line ([0085, 0029], Fig. 2), and that “(b)it lines 115-a may then be formed, for example, by depositing a layer of material and selectively etching to form the line structure depicted in FIG. 2” ([0046]). It is noted that the first conductive layers have a portion removed during the modified step (v). It is noted that the bit line 115-a extends in a first direction parallel to the substrate and the word line 110-a extends in a second direction parallel to the substrate (Fig. 2).--Claims 10, 15: Fig. 2 and Fig. 3 show that a width of the bit line 115-a and 205-c is about equal to a first width of the chalcogenide layer in a first direction and a width of the word line 110-a and 210-c is about equal to a second width of the chalcogenide layer in a second direction. Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to perform the modified step (v) so that a first portion and a second portion, opposite from the first portion, of the peripheral portion are based on the word line 110-a, and a third portion and a fourth portion, opposite from the third portion, of the peripheral portion are based on the bit line 115-a. It is noted that since the chalcogenide layer is symmetrical in the lateral direction, a width,
stability, resistivity, and composition of the first portion of the sidewall region and the second portion of the sidewall region being equivalent, and a width, stability, resistivity, and composition of the third portion of the sidewall region and the fourth portion of the sidewall region being equivalent.--Claims 13, 14: Lee further teaches that the plasma further comprises Cl2 (Claim 19). It is noted that structural integrity and mechanical stability are desirable qualities of a semiconductor device. Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention to increase the structural integrity and mechanical stability of the sidewall while performing the etching, i.e. doping the exposed surface of the chalcogenide material for a duration of time by using a plasma comprising BCl3 and Cl2 to form a doped peripheral region while removes materials from the chalcogenide layer, based on a gas flows during the etching. --Claim 18: It is noted that Redaelli modified by Lee teaches a method of etching/doping the exposed surface of the chalcogenide material for a duration of time by using a plasma comprising BCl3 and Cl2 to form a doped peripheral region, wherein the plasma also removes materials from the chalcogenide layer, thus this method may also be considered a cleaning process. Thus, the composition of the peripheral region has a different concentration of the boron species, being on directed contact with the plasma comprising BCl3 and Cl2. It is noted that claim 18 does not recite any particular value for the composition for the peripheral region other than it is different than the composition in the bulk region. It is noted that a duration of exposure to the plasma comprising boron would affect the concentration of the boron species penetrating into the chalcogenide layer. Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to adjust a duration of the etching to optimize a concentration of dopant species in the chalcogenide layer because it’s been well established that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”. MPEP 2144.05(II)(A).
Claims 12 and 19-21 rejected under 35 U.S.C. 103 as being obvious over Redaelli in view of Lee as applied to claim 11 and 18 above, and further in view of Dutta et al. (U.S. PGPub. No. 20210091306), hereinafter “Dutta”:--Claim 12: Redaelli modified by Lee teaches the invention as in claims 11 and 18. Redaelli and Lee fail to teach the claimed feature “increasing the duration of the etching to increase a width of the sidewall region,
decrease a width of the bulk region, or both”. Dutta, also directed to etching a stack on a semiconductor substrate by using a plasma (Step 202 in Fig. 2, [0031]), teaches that due to a variation in the thickness of the stack the etch time may be adjusted dynamically for each substrate by using endpoint detection ([0040]). Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to use the endpoint detection method taught by Dutta to adjust, i.e. increase or decrease, the etching time for each substrates in the invention of Redaelli because Dutta teaches that this may be necessary due to a variation in the thickness of the incoming stack. It is obvious that increasing the duration of the etching would cause the width of the component to be smaller, and cause the width of the center region that does not have any boron atoms to be reduced.--Claims 19, 20, 21: It is noted that structural integrity is a desirable quality of a semiconductor device. Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention to increase the structural integrity and mechanical stability of the sidewall while increasing the duration of the etching step because it’s been well established that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”. MPEP 2144.05(II)(A). See KSR, 550 U.S. at 421 (“A person of ordinary skill is also a person of ordinary creativity, not an automaton.”). It is also noted that the increasing a width of the sidewall region in claims 19-20, and the increase in the structural integrity recited in claim 21 are interpreted an intention (see Claim Interpretations)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS PHAM whose telephone number is (571) 270-7670 and fax number is (571) 270-8670. The examiner can normally be reached on MTWThF9to6 PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Allen can be reached on (571) 270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THOMAS T PHAM/Primary Examiner, Art Unit 1713