Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-6, 8-10, and 18 are rejected under 35 U.S.C. 102(a)(1) as being being unpatentable by Kim et al. (CN-113972212-A referred as Kim).
Regarding claim 1. Kim discloses a semiconductor device comprising:
a substrate including cell regions ([pg 12, paragraph 1 of attached Machine Translation], figure 10, a substrate #100 with cell regions #CR. Please note all page/paragraph references relating to Kim comes from the Machine Translation document);
active patterns adjacent to each other in first and second directions that are parallel to a lower surface of the substrate and intersect each other on the cell regions ([pg 12, paragraph 2], figure 10, figure 12, active patterns #CACT are seen adjacent in the first direction #D3 and the second direction #D1 each other that are parallel to a lower surface of the substrate #100 while also intersecting each other on the cell regions #CR);
a shield pattern surrounding side surfaces of the active patterns ([pg 18, paragraph 1], figure 10, the component isolation patterns #150C1/150C2 includes shield pattern #142 surrounding the side surfaces of the active patterns #CACT);
a first isolation pattern surrounding the active patterns between the active patterns and the shield pattern ([pg 18, paragraph 1], figure 10, the single component isolation pattern #150C1 includes a first isolation pattern #140 surrounding the active pattern #CACT and the shield pattern #142);
second isolation patterns between adjacent active patterns in the first direction ([pg 18, paragraph 1], figure 10, the component isolation pattern #150C1 includes a second isolation patterns #144 between the adjacent active patterns #CACT); and
word lines crossing the active patterns and the shield pattern in the second direction ([pg 12, paragraph 1], figure 9-10, word lines #WL are seen crossing the active patterns #CACT and the shield pattern #142 in the second direction #1).
Regarding claim 2. Kim discloses wherein the shield pattern surrounds the second isolation patterns (figure 10, the shield pattern #142 is seen surrounding the second isolation pattern #144).
Regarding claim 3. Kim discloses wherein the shield pattern is interposed between the first isolation pattern and the second isolation patterns (figure 10, the shield pattern #142 is seen interposed between the first isolation pattern #140 and the second isolation pattern #144).
Regarding claim 5. Kim discloses wherein an uppermost surface of the shield pattern is positioned at a level higher than a lowermost surface of each of the word lines ([pg 11 paragraph 11], figure 11, the uppermost surface of the shield pattern #142 from the component isolation pattern #150C2 is seen with a higher level than the lowermost surface of each of the word lines #WL).
Regarding claim 6. Kim discloses wherein the shield pattern covers a side surface of each of the word lines (figure 10, the shield patterns #142 are seen covering a side surface of the word lines #WL).
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Regarding claim 8. Kim discloses wherein the shield pattern is one shield pattern, and wherein the one shield pattern surrounds side surfaces of two or more of the active patterns (annotated figure 10 above, the shield pattern #142 is one shield pattern. And the one shield pattern #142 is seen surrounding two side surfaces of active pattern #CACT1 and #CACT2).
Regarding claim 9. Kim discloses further comprising: active trench regions defined between the active patterns neighboring in the first direction (figure 14-15, the active trench region #CT1 defined between the active patterns #CACT are neighboring in the first direction #D3),
wherein the shield pattern covers inner walls of the active trench regions (fig 16, the shield pattern #142 is seen covering the inner walls of the active trench region #CT1),
wherein the first isolation pattern is interposed between the shield pattern and the inner walls of the active trench regions (fig 16, the first isolation pattern #140 is seen interposed between the shield pattern #142 and the inner walls of the active trench region #Ct1), and
wherein the second isolation patterns are surrounded by the shield pattern in the active trench region (fig 16, the second isolation pattern #144 is seen surrounded by the shield pattern #142 in the active trench region).
Regarding claim 10. Kim discloses further comprising: active trench regions defined between active patterns neighboring in the second direction (figure 14-15, the active trench region #CT2 between the active patterns #CACT neighboring in the second direction #D1),
wherein the first isolation pattern covers inner walls of the active trench regions (figure 16, the first isolation pattern #140 is seen covering inner walls of the active trench region #CT2),
wherein the shield pattern fills insides of the active trench regions (figure 16, the shield pattern #142 is seen filling in the inside of the active trench region #CT2), and
wherein the second isolation patterns are not provided in the active trench regions (figure 16, the second isolation pattern #144 is not seen present in the active trench region #CT2).
Regarding claim 18. Kim discloses a semiconductor device comprising:
a substrate including a cell region ([pg 12, paragraph 1 of attached Machine Translation], figure 9, a substrate #100 with cell regions #CR);
active patterns adjacent to each other in first to third directions that are parallel to a lower surface of the substrate and intersect each other on the cell region ([pg 12, paragraph 2], figure 10, figure 12, active patterns #CACT are seen adjacent in the first direction #D3 and the third direction #D2 each other that are parallel to a lower surface of the substrate #100 while also intersecting each other on the cell regions #CR);
a shield pattern surrounding side surfaces of the active patterns ([pg 18, paragraph 1], figure 10, the component isolation patterns #150C1/150C2 includes shield pattern #142 surrounding the side surfaces of the active patterns #CACT);
a first isolation pattern surrounding the active patterns between the active patterns and the shield pattern ([pg 18, paragraph 1], figure 10, the single component isolation pattern #150C1 includes a first isolation pattern #140 surrounding the active pattern #CACT and the shield pattern #142);
second isolation patterns between adjacent active patterns in the first direction ([pg 18, paragraph 1], figure 10, the component isolation pattern #150C1 includes a second isolation patterns #144 between the adjacent active patterns #CACT);
word lines crossing the active patterns and the shield pattern in the second direction ([pg 12, paragraph 1], figure 9-10, word lines #WL are seen crossing the active patterns #CACT and the shield pattern #142 in the second direction #D1);
bit lines extending in the third direction on the active patterns ([pg 12, paragraph 1], figure 9-10, bit lines #BL extending in the third direction #D2 on the active patterns #CACT);
storage node contacts interposed between adjacent bit lines on the active patterns and adjacent to each other in the second and third directions ([pg 13, paragraph 1-3], figure 9-10, storage node contacts #BC interposed between the adjacent bit lines #BL on the active patterns #CACT and also adjacent to each other in the second #D1 and third direction #D2);
landing pads on the storage node contacts ([pg 13, paragraph 3-5], figure 11, landing pads #LP are seen on the storage node contacts #BC); and
data storage patterns on the landing pads ([pg 14, paragraph 1], figure 11, the data storage pattern #CA is seen on the landing pads #LP. Please note the data storage pattern is made up of a capacitor which contains two electrodes and a dielectric layer).
Claims 13-17 are rejected under 35 U.S.C. 102(a)(1) as being being unpatentable by Lee et al. (US-20150333059-A1 referred as Lee).
Regarding claim 13. Lee discloses a semiconductor device comprising: a first active pattern and a second active pattern adjacent to each other in a first direction ([0085-0086], figure 8b, a first active pattern #ACT-left and a second active pattern #ACT-right are seen adjacent with each other in a first direction);
a device isolation pattern surrounding the first active pattern and the second active pattern ([0085-0086], figure 8b, a device isolation pattern #102 is seen surrounding the first active pattern #ACT-left and the second active pattern #ACT-right);
a word line crossing the device isolation pattern in a second direction crossing the first direction between the first active pattern and the second active pattern ([0085-0086], figure 8a-8b, a word line #WL crossing the device isolation pattern #102 in a second direction and crossing the first direction between the first active pattern #ACT-left and the second active pattern #ACT-right. Also further viewed in figure 8a) ; and
a shield pattern between the first active pattern and the word line and between the second active pattern and the word line ([0085-0086], figure 8b, a shield pattern #104 is seen between the first active pattern #ACT-left and the word line #WL and also in between the second active pattern #ACT-right and the word line #WL).
Regarding claim 14. Lee discloses wherein an uppermost surface of the shield pattern is positioned at a level higher than a lowermost surface of the word line (figure 8b, the uppermost surface of the shield pattern #104 is seen positioned at a higher level than a lowermost surface of the word line #WL).
Regarding claim 15. Lee discloses wherein the device isolation pattern surrounds the shield pattern (figure 8b, the device isolation pattern #102 is seen surrounding on of the shield pattern #104).
Regarding claim 16. Lee discloses wherein the shield pattern is one shield pattern, and wherein the one shield pattern surrounds side surfaces of the first active pattern and the second active pattern (figure 8b, the shield pattern #104 is one shield pattern seen in the center.. wherein the one shield pattern surrounds the side surfaces of the first active pattern #ACT-left and the second active pattern #ACT-right).
Regarding claim 17. Lee discloses wherein the device isolation pattern surrounds the first active pattern between the first active pattern and the shield pattern ([0085-0086], figure 8b, the device isolation pattern #102 surrounds the first active pattern #ACT-left and the shield pattern #104), and surrounds the second active pattern between the second active pattern and the shield pattern ([0085-0086], figure 8b, the device isolation pattern #102 surrounds the second active pattern #ACT-right and the shield pattern #104).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 7, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (CN-113972212-A referred as Kim) in view of Lee et al. (US-20150333059-A1 referred as Lee).
Regarding claim 4. Kim lacks wherein the word lines are spaced apart from each other in a third direction crossing the first and second directions, with the shield pattern interposed therebetween.
Lee discloses wherein the word lines are spaced apart from each other in a third direction crossing the first and second directions, with the shield pattern interposed therebetween ([0086], figure 8b, the word lines #WL are seen spaced apart from each other in the third direction with the shield pattern #104 disposed in between).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim to have word lines are spaced apart from each other in a third direction crossing the first and second directions, with the shield pattern interposed therebetween as taught by Lee in order to increase the workload in the device, reduce points of failure from overloading, and to provide additional protection to the word lines.
Regarding claim 7. Kim lacks wherein the shield pattern is one shield pattern, and wherein the one shield pattern covers side surfaces of two or more of the word lines ([0085-0086], figure 8a-8b, the shield pattern #104 is one shield pattern (as seen in the cut of I-I’ and II-II’ in fig 8a that atleast shows a shared #104 defining as one shield pattern) is seen covering the side surfaces of two or more word lines).
Lee discloses wherein the shield pattern is one shield pattern, and wherein the one shield pattern covers side surfaces of two or more of the word lines ([0085-0086], figure 8a-8b, the shield pattern #104 is one shield pattern (as seen in the cut of I-I’ and II-II’ in fig 8a that atleast shows a shared #104 defining as one shield pattern) is seen covering the side surfaces of two or more word lines).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim to have the shield pattern is one shield pattern, and wherein the one shield pattern covers side surfaces of two or more of the word lines as taught by Lee in order to increase the workload in the device, reduce points of failure from overloading, and to provide additional protection to the word lines.
Regarding claim 19. Kim lacks wherein the shield pattern is one shield pattern, and wherein the one shield pattern covers side surfaces of two or more of the word lines.
Lee discloses wherein the shield pattern is one shield pattern, and wherein the one shield pattern covers side surfaces of two or more of the word lines ([0085-0086], figure 8a-8b, the shield pattern #104 is one shield pattern (as seen in the cut of I-I’ and II-II’ in fig 8a that atleast shows a shared #104 defining as one shield pattern) is seen covering the side surfaces of two or more word lines).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim to have the shield pattern is one shield pattern, and wherein the one shield pattern covers side surfaces of two or more of the word lines as taught by Lee in order to increase the workload in the device, reduce points of failure from overloading, and to provide additional protection to the word lines.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (CN-113972212-A referred as Kim) in view of Choi et al. (US-20220375982-A1 referred as Choi).
Regarding claim 11. Kim lacks wherein the first isolation pattern includes a first sub-isolation pattern on a side surface of the shield pattern and a second sub- isolation pattern on an upper surface of the shield pattern.
Choi discloses wherein the first isolation pattern includes a first sub-isolation pattern on a side surface of the shield pattern and a second sub- isolation pattern on an upper surface of the shield pattern ([0093], figure 13, the first isolation pattern includes a first sub-isolation pattern #53 on a side surface of the shield pattern #51 and a second sub-isolation pattern #55 on an upper surface of the shield pattern #51).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim to include wherein the first isolation pattern includes a first sub-isolation pattern on a side surface of the shield pattern and a second sub- isolation pattern on an upper surface of the shield pattern as taught by Choi in order to increase the electrical protection in the circuitry, extend the devices lifetime, and to reduce device failure.
Regarding claim 12. Kim lacks wherein the shield pattern includes a conductive material.
Choi discloses wherein the shield pattern includes a conductive material ([0093], figure 13, the shield pattern #51 could be made of metal, such as tungsten which is known to be a conductive material).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim to include wherein the shield pattern includes a conductive material as taught by Choi in order to increase device versatility, reduce manufacturing costs, and to provide additional functionality.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (CN-113972212-A referred as Kim) in view of Nishi et al. (US-20230027990-A1 referred as Nishi).
Regarding claim 20. Kim as modified lacks wherein the substrate further includes a peripheral region surrounding the cell region, and wherein the semiconductor device further includes a contact pattern provided on the peripheral region and electrically connected to the shield pattern.
Nishi discloses wherein the substrate further includes a peripheral region surrounding the cell region ([0050], figure 3, the substrate #101c further includes a peripheral region (defined in [0047] which states the contact pattern #3 is where peripheral region is located) surrounding the cell region #1), and wherein the semiconductor device further includes a contact pattern provided on the peripheral region and electrically connected to the shield pattern ([0050], figure 3 with a closer view of A3 in figure 5, the device further includes a contact pattern #3 provided on the peripheral region and electrically connected to the shield pattern #30).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include wherein the semiconductor device further includes a contact pattern provided on the peripheral region and electrically connected to the shield pattern as taught by Nishi in order to increase connectivity outreach in the device, provide additional device functionality, and to improve the devices integrity.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure includes Park et al. (US-20230031546-A1) and Cantoro et al. (US-20170294437-A1) for the cell regions, word lines and shield patterns.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272 - 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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