DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 14-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/26/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20230006050 A1 (Park).
Re claim 1, Park teaches a semiconductor memory device, comprising:
an active pattern (active pattern 105) provided on a substrate and enclosed by a device isolation pattern (isolation pattern 110); and
a word line (horizontal data lines connecting to the gate electrodes in trenches 130 of the selection transistors in DRAM array Fig. 4, 11) crossing the active pattern and the device isolation pattern in a first direction (D1) parallel to a bottom surface of the substrate, and comprising a first gate electrode (either first gate structure 191 or second gate structure 193) and a second gate electrode (either first gate structure 191 or second gate structure 193), which are adjacent to each other in the first direction, wherein a second work function of the second gate electrode is greater than a first work function of the first gate electrode (in [0036] Park teaches that the materials for layer 150 and 170 can either be the same or different, therefore for different materials one will have a higher workfunction than the other and first and second gate electrodes can be either 193 or 191) (Figs. 4-12).
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Re claim 2, Park teaches wherein a first side surface of the first gate electrode faces the first direction (D1), and wherein the second gate electrode is on the first side surface of the first gate electrode (Fig. 11).
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Re claim 3, Park teaches wherein the word line comprises a pair of word lines (any two adjacent horizontal word lines in D2 Fig. 11) crossing the active pattern in the first direction (D1), and wherein the first gate electrode of a first one of the pair of word lines and the second gate electrode of a second one of the pair of word lines are adjacent to each other in a second direction (D2) crossing the first direction (Fig. 11).
Re claim 4, Park teaches wherein the word line is a first word line, wherein the active pattern is a first active pattern, wherein the semiconductor memory device further comprises: a second word line, which is adjacent to the first word line in a second direction (D2) crossing the first direction (D1); and a second active pattern, which is adjacent to the first active pattern in a third direction crossing the first and second directions, and wherein the second gate electrode of the second word line is interposed between the first active pattern and the second active pattern (portions of gate electrode 175 exist between the first and second active patterns of adjacent wordlines see annotated Fig. 11).
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Re claim 5, Park teaches wherein the first gate electrode comprises a plurality of first gate electrodes (array of second gate electrodes 193), wherein the second gate electrode comprises a plurality of second gate electrodes (array of first gate electrodes 193), and wherein the plurality of first gate electrodes and the plurality of second gate electrodes are alternately disposed in the first direction (see Fig. 11).
Re claim 6, Park teaches wherein a top surface of the second gate electrode is located at a level, which is equal to or higher than a top surface of the first gate electrode along a vertical direction perpendicular to the bottom surface of the substrate (Fig. 12).
Re claim 7, Park teaches wherein a bottom surface of the second gate electrode is in contact with the device isolation pattern (gate electrode includes gate conductor and gate dielectric Fig. 12).
Re claim 8, Park teaches wherein the first gate electrode and the second gate electrode comprise different materials ([0036]), each of which comprises at least one of Ti, TiN, TiSiN, TiON, W, WN, Mo, MoN, MoOxNy, Ta, TaN, or poly Si ([0028, 0036]).
Re claim 9, Park teaches wherein the second gate electrode has a resistivity smaller than the first gate electrode (second gate electrode 193 contain conductive material layer 150 formed by PVD which has large grains, conductive layers with large grains have higher parasitic resistivity).
Re claim 20, Park teaches semiconductor memory device, comprising:
an active pattern (active pattern 105) provided on a substrate and enclosed by a device isolation pattern (isolation pattern 110);
a word line (horizontal data lines connecting to the gate electrodes in trenches 130 of the selection transistors in DRAM array Fig. 4, 11) crossing the active pattern and the device isolation pattern in a first direction (D1) parallel to a bottom surface of the substrate, the word line comprising (either first gate structure 191 or second gate structure 193) and a second gate electrode (either first gate structure 191 or second gate structure 193), which are adjacent to each other in the first direction;
a bit line (bit line 395) provided on the active pattern and extended in a second direction (D2) crossing the first direction;
a bit line contact (conductive layer 255) between the active pattern and the bit line (Fig. 36);
a storage node contact (lower contact pads 475) on the active pattern;
a landing pad (metal silicide pattern 500) on the storage node contact; and
a data storage pattern (capacitor 665) on the landing pad, wherein a second work function of the second gate electrode is greater than a first work function of the first gate electrode (in [0036] Park teaches that the materials for layer 150 and 170 can either be the same or different, therefore for different materials one will have a higher workfunction than the other and first and second gate electrodes can be either 193 or 191) (Figs. 4-12).
Allowable Subject Matter
Claims 10-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2014/0054689 A1 (Park)
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US 2016/0056160 A1 (Jang)
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US 10,062,6132 B1 (Chang)
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US 10,319,726 B2 (Nam)
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US 2019/0088657 A1 (Im)
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
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