DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Arguments
Applicant's arguments with respect to claims 1 – 8 and 15 - 18 have been considered, and have found to be persuasive. Please find below the ground(s) of rejection in view of a different embodiment of the prior art, Hsu.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 8 and 15 – 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu (U.S. Patent Publication No. 2007/0158847).
Regarding claim 1, in Figure 2D-2, Hsu discloses a circuit board comprising: an insulating layer (22) including a first area (left area in which conductive structure 23c is disposed in) and a second area (right area in which circuit layer 21 is disposed in); a circuit wire (210) disposed inside the first area of the insulating layer; a first conductive pad (24) connected to the circuit wire and having an upper surface protruding above an upper surface of the insulating layer and a lower surface embedded in the insulating layer (a portion of the lower surface of pad 24 is embedded in dielectric layer 22; Figure 2D-2); and a circuit element (21) including an element pad (21) and disposed inside the second area of the insulating layer, wherein an extension line of an upper surface of the first conductive pad and an upper surface of the element pad are spaced apart from each other along a direction perpendicular to an upper surface of the insulating layer (Figure 2D-2), and based on a direction perpendicular to the upper surface of the insulating layer, the upper surface of the first conductive pad is disposed on the upper surface of the insulating layer (Figure 2D-2), and the upper surface of the element pad is disposed below the upper surface of the insulating layer (Figure 2D-2).
Regarding claim 2, Hsu discloses wherein a layer on which the circuit element is disposed in the second area and a layer on which a portion of the circuit wire is disposed in the first area are disposed on the same layer (Figure 2D-2).
Regarding claim 3, Hsu discloses wherein a width of the element pad is wider than a width of the first conductive pad (Figure 2D-2).
Regarding claim 4, Hsu discloses wherein the circuit element further includes an element main body having an upper surface on which the element pad is disposed, and an element insulating layer disposed on the upper surface of the element main body and having a first opening exposing at least a part of the element pad (Figure 2D-2).
Regarding claim 5, Hsu discloses wherein based on the upper surface of the element main body, a height of an upper surface of the first conductive pad is higher than a height of an upper surface of the element pad (Figure 2D-2).
Regarding claim 6, Hsu discloses wherein the circuit element is disposed to have a boundary surface parallel to the upper surface of the insulating layer in the second area, and at least a portion of the circuit wire is disposed on the same layer as the boundary surface (Figure 2D-2).
Regarding claim 7, Hsu discloses a second conductive pad connected to the circuit wire and protruding downwardly from a lower surface of the insulating layer, and a first solder resist layer covering the lower surface of the insulating layer and having a second opening exposing at least a part of the second conductive pad (Figure 2D-2).
Regarding claim 8, Hsu discloses a second solder resist layer covering the upper surface of the insulating layer and having a third opening exposing at least a part of the first conductive pad (Figure 2D-2).
Regarding claim 9, Hsu discloses wherein the circuit element includes an integrated passive element (Figure 2D-2).
Regarding claim 15, in Figure 2D-2, Hsu discloses an electronic component package, comprising: a circuit board including an insulating layer (22) having a first area (left area in which conductive structure 23c is disposed in) and a second area (right area in which circuit layer 21 is disposed in); a circuit wire (210) disposed in the first area inside the insulating layer; a first conductive pad (24) connected to the circuit wire and having an upper surface protruding above an upper surface of the insulating layer and a lower surface embedded in the insulating layer (a portion of the lower surface of pad 24 is embedded in dielectric layer 22; Figure 2D-2); a circuit element (21) including an element pad (21) disposed inside and at the second area of the insulating layer; an electronic component disposed on the circuit board; and a conductive adhesive member disposed on the electronic component and electrically connected to the first conductive pad and the element pad (Figure 2D-2), wherein an extension line of an upper surface of the first conductive pad and an upper surface of the element pad are spaced apart from each other along a direction perpendicular to an upper surface of the insulating layer (Figure 2D-2), and based on a direction perpendicular to the upper surface of the insulating layer, the upper surface of the first conductive pad is higher than the upper surface of the insulating layer (Figure 2D-2), and the upper surface of the element pad is lower than the upper surface of the insulating layer (Figure 2D-2).
Regarding claim 16, Hsu discloses wherein the conductive adhesive member includes a bump disposed to cover a signal wire of the electronic component, a first adhesive member that adheres the bump and the first conductive pad to each other, and a second adhesive member that adheres the bump and the element pad to each other, and a maximum width of the second adhesive member is wider than a maximum width of the first adhesive member (Figure 2D-2).
Regarding claim 17, Hsu discloses wherein a layer on which the circuit element is disposed in the second area and a layer on which a portion of the circuit wire is disposed in the first area are disposed on the same layer (Figure 2D-2).
Regarding claim 18, Hsu discloses wherein a width of the element pad is wider than a width of the first conductive pad (Figure 2D-2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847
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