DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-16, and 18-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kinzer et al. (U.S. Publication No. 2022/0102251 A1; hereinafter Kinzer)
With respect to claim 1, Kinzer discloses a package, comprising: a mounting plate [200] having a first part [235] configured to dissipate heat and a second part [225] configured to transmit and/or receive electrical signals (see Figure 2B); a first electronic chip [705] having a first semiconductor substrate (see ¶[0064]); a second electronic chip [710] having a second semiconductor substrate (see ¶[0064]); wherein the first and second semiconductor substrates are different; a cladding housing the first and second electronic chips (see ¶[0033]); wherein the first electronic chip is thermally coupled to the first part of the mounting plate (see ¶[0034], ¶[0045-00046] and ¶[0064-0065]), electrically coupled to the second electronic chip by connecting wires, and electrically coupled to the second part of the mounting plate by connecting wires (See Figure 7A); and wherein the second electronic chip is thermally coupled to the first part of the mounting plate and electrically coupled to the second part of the mounting plate by at least a first array of connection balls (see ¶[0034], ¶[0045-00046] and ¶[0064-0065]).
With respect to claim 5, Kinzer discloses the package being of the flat no-leads type (see ¶[0064]).
With respect to claim 6, Kinzer discloses wherein the first semiconductor substrate includes gallium nitride (see ¶[0064]).
With respect to claim 7, Kinzer discloses wherein the second semiconductor substrate includes silicon (see ¶[0064]).
With respect to claim 8, Kinzer discloses a support [320] having a mounting face and an attaching face opposite to the mounting face, wherein the attaching face is connected to the first and second parts of the mounting plate by the first array of connection balls (see Figure 3 and ¶[0076]), wherein the mounting face is connected to the second electronic chip by a second array of connection balls, and wherein the support comprises an interconnection network [330] configured to electrically couple the first array of connection balls, the second array of connection balls and the first electronic chip (See ¶[0119]).
With respect to claim 9, Kinzer discloses wherein the connecting wires include first connecting wires and second connecting wires, the first electronic chip has a rear face attached to the first part of the mounting plate by a layer of thermally conductive glue and a front face electrically connected to the second part of the mounting plate by the first connecting wires and electrically connected to the interconnection network by the second connecting wires (See Figure 3, 7A, and 11).
With respect to claim 10, Kinzer discloses at least one surface-mount device [345] component mounted to the support and housed within the cladding, and wherein the interconnection network of the support is also configured to electrically couple said at least one surface-mount device component to the first electronic chip and to the second electronic chip (See Figure 3 and 7A).
With respect to claim 11, Kinzer discloses wherein the first part is a central part and the second part is a peripheral part (See Figure 3 and 7A).
With respect to claim 12, Kinzer discloses a method for manufacturing a package, comprising: forming a mounting plate [200] having a first part [235] configured to dissipate heat and a second part [225] configured to transmit and/or receive electrical signals (see Figure 2B); forming a first electronic chip [705] having a first semiconductor substrate; forming a second electronic chip [710] having a second semiconductor substrate (see ¶[0064]); wherein the first and second semiconductor substrates are different; thermally coupling the first electronic chip to the first part, electrically coupling the first electronic chip to the second electronic chip by connecting wires, and electrically coupling the first electronic chip to the second part by connecting wires (see Figure 7A and ¶[0034], ¶[0045-00046] and ¶[0064-0065]); thermally coupling the second electronic chip to the first part and electrically coupling the second electronic chip to the second part by at least a first array of connection balls (See ¶[0119]); and forming a cladding that houses at least the first and second electronic chips (see ¶[0033]).
With respect to claim 13, Kinzer discloses comprising: forming a support [320] having a mounting face and an attaching face opposite to the mounting face; connecting the attaching face of the support to the first part of the mounting plate and to the second part of the mounting plate by the first array of connection balls (see Figure 3 and ¶[0076]); connecting the mounting face of the support to the second electronic chip by a second array of connection balls; and forming an interconnection network [330] on and in the support to electrically couple the first array of connection balls, the second array of connection balls and the first electronic chip (see ¶[0119]).
With respect to claim 14, Kinzer discloses mounting at least one surface-mount device [345] component to the support in electrical connection to the first electronic chip and the second electronic chip; and housing said at least one surface-mount device component in the cladding (See ¶[0008] and Figure 3 and Figure 7A)
With respect to claim 15, Kinzer discloses wherein forming the mounting plate comprises forming a first central part and a second peripheral part (See Figure 3 and 7A).
With respect to claim 16, Kinzer discloses wherein the package is of the flat no-leads type (see ¶[0064])
With respect to claim 18, Kinzer discloses a package, comprising: a leadframe including a die pad and a plurality of leads (see ¶[0006]); a first electronic chip [705] having a first semiconductor substrate with a rear face mounted to the die pad and a front face electrically connected to first ones of the plurality of leads by first bonding wires; a support [325] including an interconnection network [330] with a rear face electrically connected by first bumps to the die pad and to second ones of the plurality of leads (see ¶[0076]); a second electronic chip [710] having a second semiconductor substrate with a first face mounted to a front face of the support and electrically connected to the interconnection network; and a cladding encapsulating the leadframe, the support and the first and second electronic chips (see ¶[0033]); wherein the first and second semiconductor substrates are different (See ¶[0064]).
With respect to claim 19, Kinzer discloses wherein the first face of the second electronic chip is a front face with second bumps electrically connected to the interconnection network (See ¶[0119]).
With respect to claim 20, Kinzer discloses second bonding wires electrically connecting the front face of the first electronic chip to the interconnection network at the front face of the support (See Figure 3 and 7A).
With respect to claim 21, Kinzer discloses a surface mount device [345] mounted and electrically connected to the interconnection network at the front face of the support, wherein the surface mount device is encapsulated within the cladding (See Figure 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2-4 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kinzer in view of Moriwaki et al. (U.S. Publication No. 2021/0242144 A1; hereinafter Moriwaki)
With respect to claim 2, Kinzer discloses fails to explicitly disclose the first semiconductor substrate is configured to give off, in operation, a first quantity of heat, wherein the second semiconductor substrate is configured to give off, in operation, a second quantity of heat, and wherein the second quantity of heat is less than the first quantity of heat, however does disclose the ability for the package to handle variable heat production (see ¶[0055] and ¶[0057]).
In the same field of endeavor, Moriwaki teaches the first semiconductor substrate is configured to give off, in operation, a first quantity of heat, wherein the second semiconductor substrate is configured to give off, in operation, a second quantity of heat, and wherein the second quantity of heat is less than the first quantity of heat, however does disclose the ability for the package to handle variable heat production (See ¶[0039] and ¶[0069]). Implementation of a substrate with heat dissipation capabilities of a wide range of thermal output as taught by Moriwaki allows for increased versability and high heat dissipation characteristics, thereby preserving device integrity and functionality (See ¶[0069]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention.
With respect to claim 3, the combination of Kinzer and Moriwaki discloses wherein the first quantity of heat corresponds to a dissipated power of several watts (See Moriwaki ¶[0069]).
With respect to claim 4, the combination of Kinzer and Moriwaki discloses wherein the second quantity of heat corresponds to a dissipated power of less than 1 watt (See Moriwaki ¶[0039]).
With respect to claim 17, Kinzer fails to disclose wherein the first semiconductor substrate is configured to give off, in operation, a first quantity of heat, wherein the second semiconductor substrate is configured to give off, in operation, a second quantity of heat, and wherein the second quantity of heat is less than the first quantity of heat, however does disclose the ability for the package to handle variable heat production (see ¶[0055] and ¶[0057]).
In the same field of endeavor, Moriwaki teaches the first semiconductor substrate is configured to give off, in operation, a first quantity of heat, wherein the second semiconductor substrate is configured to give off, in operation, a second quantity of heat, and wherein the second quantity of heat is less than the first quantity of heat, however does disclose the ability for the package to handle variable heat production (See ¶[0039] and ¶[0069]). Implementation of a substrate with heat dissipation capabilities of a wide range of thermal output as taught by Moriwaki allows for increased versability and high heat dissipation characteristics, thereby preserving device integrity and functionality (See ¶[0069]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818