Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18387325 filed on 11/06/2023.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of claims 1-12, 21-28 in the reply filed on 04/16/206 is acknowledged.
Allowable Subject Matter
Claims 4-10 are objected to as being dependent upon a rejected base claim (independent claim 1), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Meylan et al. (US 2019/0140072).
With respect to dependent claims 4-5, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein the first doped semiconductor region comprises a first surface in contact with the second layer, and a second surface opposite to the first surface, the surface area of the second surface being greater than the surface area of the first surface”.
With respect to dependent claims 6-10, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein the second layer is formed in a semiconductor substrate, the method further comprising: forming an insulating third layer covering the second layer, and forming a second doped semiconductor region providing part of the collector of the bipolar transistor at a location flush with an upper surface of the substrate”.
Claims 21-28 are allowed.
The following is an examiner' s statement of reasons for allowance:
Claims 21-28: The primary reason for the allowance of the claims is the inclusion of the limitation “forming a cavity crossing through the base layer and the insulating first layer; wherein the insulating spacers at least partially cover side walls of the transistor base layer”, in all of the claims in combination with the remaining features of independent claim 21.
Meylan et al. (US 2019/0140072) teach a method of manufacturing a bipolar transistor, comprising: forming a first transistor collector layer (Fig. 2, element 105, paragraph 0023) made of a doped semiconductor material; forming an insulating first layer (Fig. 2, elements 107/108/119, paragraph 0027) covering the first collector layer; forming a transistor base layer (Fig. 2, element 127, paragraph 033) over the insulating first layer; forming a cavity (Fig. 3, element 121, paragraph 0028) crossing through the insulating first layer; forming insulating spacers (Fig. 4, elements 123, paragraph 0029) against lateral walls of the cavity, etching the insulating spacers so that an upper surface of the insulating spacers is coplanar with an upper surface of the insulating first layer (Fig. 5, paragraph 0030); forming a second transistor collector layer (Figs. 5 & 6, elements 125 & 126, paragraph 0030-0031) made of a doped semiconductor material in the cavity by epitaxial growth from the first collector layer; wherein the second transistor collector layer has a doping concentration decreasing from the first transistor collector layer (Figs. 5 & 6, paragraph 0023, 0030-0031 disclose element 105 & 125 with n type doping region & element 126 with counter doped region p type. Therefore, the n type doping decreases from region 105 & 125 towards p type region 126).
However, Meylan et al. do not teach or render obvious the above-quoted features recited in independent claim 21.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Meylan et al. (US 2019/0140072).
Regarding independent claim 1, Meylan et al. teach a method of manufacturing a bipolar transistor, comprising:
forming a collector of the bipolar transistor by: forming an insulating first layer (Fig. 2, element 107, paragraph 0024) covering a second layer made of a doped semiconductor material (Fig. 2, element 105, paragraph 0023), the second layer forming a first portion of the collector (paragraph 0023);
forming a cavity (Fig. 3, element 121, paragraph 0028) crossing through the insulating first layer to reach the second layer;
forming insulating spacers (Fig. 4, elements 123, paragraph 0029) against lateral walls of the cavity; and
epitaxially growing, from the second layer, a first doped semiconductor region (Figs. 5 & 6, elements 125 & 126, paragraph 0030-0031) in the cavity, the first doped semiconductor region forming a second portion of the collector (paragraph 0030);
wherein the first doped semiconductor region has a doping concentration decreasing from the second layer (Figs. 5 & 6, paragraph 0023, 0030-0031 disclose element 105 & 125 with n type doping region & element 126 with counter doped region p type. Therefore, the n type doping decreases from region 105 & 125 towards p type region 126).
Regarding claim 11, Meylan et al. teach further comprising forming a seventh layer (Fig. 2, element 127, paragraph 033) providing part of a base (paragraph 0033) of the bipolar transistor, wherein the seventh layer covers the first doped semiconductor region.
Regarding claim 12, Meylan et al. teach further comprising forming an emitter region (Fig. 14, element 133’, paragraph 0037) over the first doped semiconductor region, wherein the emitter region is separated from the first doped semiconductor region by the seventh layer providing part of the base of the bipolar transistor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Meylan et al. (US 2019/0140072) in view of Sinha et al. (US 12,324,226).
Regarding claim 2, Meylan et al. teach all of the limitations as discussed above.
Meylan et al. do not explicitly disclose wherein the spacers have a profile decreasing from the second layer.
Sinha et al. teach a BJT comprising spacers having a profile decreasing from the bottom (Fig. 7, elements 231 are the spacers).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Meylan et al. according to the teachings of Sinha et al. with the motivation to provide structural support for self-aligned patterning.
Regarding claim 3, Meylan et al. modified by Sinha et al. teach wherein the spacers and the first doped semiconductor region fill the cavity (Fig. 7 of Meylan).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813
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