Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities:
The examiner is not certain about the scope of the limitation “a first axis length is the same as a second axis length one-dimensionally or planarily”. It’s not clear to the examiner how two lengths can be “planarily” the same.
The meaning will be interpreted as the first upper/lower bonding pads are disposed in a a line or in an array that has a 2-dimensional shape, wherein the two dimensions of the array are equal in length.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-10 and 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over Liao (US # 20230395427) in view of Jayantha (US # 20080217384).
Regarding Claim 1, Liao (US # 20230395427) teaches a semiconductor package comprising:
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a lower chip (100) including a lower bonding insulation layer (143), a first lower bonding pad (151), and a second lower bonding pad (153); and
an upper chip (300) disposed on the lower chip, the upper chip including an upper bonding insulation layer (333), a first upper bonding pad (343 on left), and a second upper bonding pad (343 on left) respectively hybrid-bonded to the lower bonding insulation layer, the first lower bonding pad, and the second lower bonding pad ([0089] teaches a hybrid bonding process where a “front surface 300F S of the second chip 300 may be bonded onto the front surface 100F S of the first chip 100”).
Although Liao discloses much of the claimed invention, it does not explicitly teach the particular bonding pad shapes and arrangement between the chips, specifically wherein each of the first lower bonding pad and the first upper bonding pad have a first shape in which a first axis length is the same as a second axis length one-dimensionally or planarily, and the first lower bonding pad and the first upper bonding pad are disposed in a first center region which is near a center point of the lower chip and the upper chip, each of the second lower bonding pad and the second upper bonding pad have a second shape in which a third axis length differs from a fourth axis length one-dimensionally or planarily, and the second lower bonding pad and the second upper bonding pad are disposed in a first edge region which is near a corner point of the lower chip and the upper chip, and the third axis length is greater than the first axis length, and in the second lower bonding pad and the second upper bonding pad disposed in the first edge region, the third axis length is arranged in a direction perpendicular to a radial direction from the center point.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
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For example, Jayantha (US # 20080217384) is in the same or analogous field, and it teaches a package wherein each of a first lower bonding pad (20) and a first upper bonding pad (22) have a first shape (circular) in which a first axis length (a first diameter of a circular pad) is the same as a second axis length (any other diameter of the circular pad) one-dimensionally or planarily, and the first lower bonding pad and the first upper bonding pad are disposed in a first center region (see the smallest annotated circular region containing feature 20 in annotated Fig. 4A) which is near a center point (that is the central portion, as shown in Fig. 3A) of the lower chip and the upper chip,
each of the second lower bonding pad (feature 26 is the same as the other pair of pads, but elliptical shaped; see [0032]) and the second upper bonding pad have a second shape (elliptical) in which a third axis length differs from a fourth axis length (Fig. 4B shows major and minor axes) one-dimensionally or planarily, and the second lower bonding pad and the second upper bonding pad are disposed in a first edge region (these elliptical bonding pads are shown the upper-right corner of the bonding area) which is near a corner point (shown) of the lower chip and the upper chip, and the third axis length is greater than the first axis length (major axis is longer, as shown in Fig. 4B), and
in the second lower bonding pad and the second upper bonding pad disposed in the first edge region, the third axis length is arranged in a direction perpendicular to a radial direction from the center point (the major axis of features 26 appear to be tangential to a radial vector pointing from the center of the bonding pad center point).
A person having ordinary skill in the art would have recognized that modifying the pad configuration of Liao with the pad configuration suggested by Jayantha would be obvious. Specifically, the modification suggested by Jayantha would be to employ a package wherein each of the first lower bonding pad and the first upper bonding pad have a first shape in which a first axis length is the same as a second axis length one-dimensionally or planarily, and the first lower bonding pad and the first upper bonding pad are disposed in a first center region which is near a center point of the lower chip and the upper chip, each of the second lower bonding pad and the second upper bonding pad have a second shape in which a third axis length differs from a fourth axis length one-dimensionally or planarily, and the second lower bonding pad and the second upper bonding pad are disposed in a first edge region which is near a corner point of the lower chip and the upper chip, and the third axis length is greater than the first axis length, and in the second lower bonding pad and the second upper bonding pad disposed in the first edge region, the third axis length is arranged in a direction perpendicular to a radial direction from the center point. The rationale for this obvious modification is that such a pad layout is optimal for a semiconductor chip that is prone to fatigue ([0034]) and for rotational alignment-error tolerance.
Regarding Claim 2, Jayantha, as applied to claim 1, teaches the semiconductor package of claim 1, wherein the first shape is a circular shape, and the second shape is an oval shape (see claim 1 rejection).
Regarding Claim 3, the same reasoning & evidence applied to the rejection claim 18 applies to this claim.
Regarding Claim 4, although drawings are not presumed to be to scale, Jayantha, as applied to claim 1, graphically suggests the semiconductor package of claim 1, wherein a ratio of the fourth axis length to the third axis length is 1:1.5 to 1:15 (feature 26 measures at 11/15 ratio).
Regarding Claim 5, Liao teaches the semiconductor package of claim 1, wherein the second lower bonding pad of the first edge region is partially staggered with respect to the second upper bonding pad of the first edge region (pad 153 is shown with a central vertical axis that is staggered from the central vertical axis of 343).
Regarding Claim 6, Jayantha, as applied to claim 1, teaches the semiconductor package of claim 5, wherein one of the second lower bonding pad and the second upper bonding pad of the first edge region is rotated clockwise or counterclockwise with respect to the center point (feature 26 is rotated slightly compared with the center point).
Regarding Claim 7, Jayantha, as applied to claim 1, teaches the semiconductor package of claim 5, wherein one of the second lower bonding pad and the second upper bonding pad of the first edge region is offset in an X direction or a Y direction with respect to the center point (feature 26 is offset slightly compared with the center point in the X direction).
Regarding Claim 8, Jayantha, as applied to claim 1, teaches the semiconductor package of claim 1, wherein the second lower bonding pad and the second upper bonding pad of the first edge region are vertically and partially staggered (the rows of the array of features 26 are staggered and it is normal in semiconductors that all pad features are imperfectly aligned at the atomic level, i.e. vertically and partially staggered).
Regarding Claim 9, Liao teaches the semiconductor package of claim 1, wherein the first lower bonding pad and the first upper bonding pad of the first center region are bonded to each other to form a first hybrid bonding portion,
the second lower bonding pad and the second upper bonding pad of the first edge region are bonded to each other to form a second hybrid bonding portion, and
the lower bonding insulation layer and the upper bonding insulation layer are bonded to each other to form a third hybrid bonding portion (the connection is between the conductive and the insulative layers; see more details beginning at [0090]).
Regarding Claim 10, Jayantha, as applied to claim 1, teaches the semiconductor package of claim 1, wherein the lower chip further includes a third lower bonding pad and the upper chip further includes a third upper bonding pad (Figs. 3-4 show that the central portion is surrounded by edge regions with elongated shaped bonding pads, so the top-left portion of the edge region could be considered the third bonding area with the pads as recited),
each of the third lower bonding pad and the third upper bonding pad have the second shape (oval) in which the third axis length differs from the fourth axis length one-dimensionally or planarily (minor axis is smaller than the major axis), the third lower bonding pad and the third upper bonding pad being disposed in a second edge region (top-left portion of the edge region) which is adjacent to edges of the lower chip and the upper chip, and
in the third lower bonding pad and the third upper bonding pad of the second edge region, the third axis length is arranged in an X direction or a Y direction from the center point (these pads are offset in the X and Y directions from the center point of the chips).
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Regarding Claim 12, Jayantha, as applied to claim 1, teaches the semiconductor package of claim 1, wherein the lower chip and the upper chip further comprise a second center region (see slightly larger circle that includes circular pads) in which a fifth lower bonding pad and a fifth upper bonding pad, each having the first shape in which the first axis length is the same as the second axis length are disposed (circular pads), the second center region being disposed at a perimeter of the first center region and between the first center region and the first edge region (shown), and
the lower chip and the upper chip further comprise a fourth edge region (similar to the other edge regions, but this one is the bottom-left corner) in which a sixth lower bonding pad and a sixth upper bonding pad, each having the second shape in which the third axis length differs from the fourth axis length are disposed, and the sixth lower bonding pad and the sixth upper bonding pad are disposed at a perimeter of the second center region (the oval pads in the bottom-left).
Regarding Claim 13, Liao (US # 20230395427) teaches a semiconductor package comprising:
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a lower chip (100) including a lower bonding insulation layer (143), a first lower bonding pad (151), and a second lower bonding pad (153); and
an upper chip (300) disposed on the lower chip, the upper chip including an upper bonding insulation layer (333), a first upper bonding pad (343 on left), and a second upper bonding pad (343 on left) respectively hybrid-bonded to the lower bonding insulation layer, the first lower bonding pad, and the second lower bonding pad ([0089] teaches a hybrid bonding process where a “front surface 300F S of the second chip 300 may be bonded onto the front surface 100F S of the first chip 100”).
Although Liao discloses much of the claimed invention, it does not explicitly teach the particular bonding pad shapes and arrangement between the chips, specifically wherein the first lower bonding pad and the first upper bonding pad each have a circular shape and are one-simensionally or planarily arranged in a first center region that is disposed near a center point of the lower chip and the upper chip, the second lower bonding pad and the second upper bonding pad each having an oval shape are one-dimensionally or planarily arranged in a perpendicular direction, which is perpendicular to a radial direction from the center point, the second lower bonding pad and the second upper bonding pad being disposed in a first edge region that is disposed near corner points of the lower chip and the upper chip, and a long-axis length of the oval shape is greater than a diameter of the circular shape, and the second lower bonding pad and the second upper bonding pad of the first edge region are arranged to be one-dimensionally or planarily staggered, and partially staggered in the perpendicular direction perpendicular to the radial direction from the center point.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
For example, Jayantha (US # 20080217384) is in the same or analogous field, and it teaches a package wherein each of a first lower bonding pad (20) and a first upper bonding pad (22) have a first shape (circular) in which a first axis length (a first diameter of a circular pad) is the same as a second axis length (any other diameter of the circular pad) one-dimensionally or
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planarily, and the first lower bonding pad and the first upper bonding pad are disposed in a first center region (see the region containing feature 20 in annotated Fig. 4A) which is near a center point (that is the central portion, as shown in Fig. 3A) of the lower chip and the upper chip,
each of the second lower bonding pad (feature 26 is the same as the other pair of pads, but elliptical shaped; see [0032]) and the second upper bonding pad have a second shape (elliptical) in which a third axis length differs from a fourth axis length (Fig. 4B shows major and minor axes) one-dimensionally or planarily, and the second lower bonding pad and the second upper bonding pad are disposed in a first edge region (these elliptical bonding pads are shown the upper-right corner of the bonding area) which is near a corner point (shown) of the lower chip and the upper chip, and the third axis length is greater than the first axis length (major axis is longer, as shown in Fig. 4B), and
in the second lower bonding pad and the second upper bonding pad disposed in the first edge region, the third axis length is arranged in a direction perpendicular to a radial direction from the center point (the major axis of features 26 appear to be tangential to a radial vector pointing from the center of the bonding pad center point).
A person having ordinary skill in the art would have recognized that modifying the pad configuration of Liao with the pad configuration suggested by Jayantha would be obvious. Specifically, the modification suggested by Jayantha would be to employ a package wherein each of the first lower bonding pad and the first upper bonding pad have a first shape in which a first axis length is the same as a second axis length one-dimensionally or planarily, and the first lower bonding pad and the first upper bonding pad are disposed in a first center region which is near a center point of the lower chip and the upper chip, each of the second lower bonding pad and the second upper bonding pad have a second shape in which a third axis length differs from a fourth axis length one-dimensionally or planarily, and the second lower bonding pad and the second upper bonding pad are disposed in a first edge region which is near a corner point of the lower chip and the upper chip, and the third axis length is greater than the first axis length, and in the second lower bonding pad and the second upper bonding pad disposed in the first edge region, the third axis length is arranged in a direction perpendicular to a radial direction from the center point. The rationale for this obvious modification is that such a pad layout is optimal for a semiconductor chip that is prone to fatigue ([0034]) and for rotational alignment error tolerance.
Regarding Claim 14, Liao teaches the semiconductor package of claim 1, wherein wherein the first lower bonding pad and the first upper bonding pad of the first center region are vertically aligned and disposed (pad 151 is shown with a central vertical axis that is aligned with the central vertical axis of 343 directly above it), and
the second lower bonding pad of the first edge region is partially staggered with respect to the second upper bonding pad of the first edge region (pad 153 is shown with a central vertical axis that is staggered from the central vertical axis of 343).
Regarding Claim 15, this claim is rejected for essentially the same reasons as claim 10.
Regarding Claim 16, this claim is rejected for essentially the same reasons as claim 11.
Regarding Claim 17, this claim is rejected for essentially the same reasons as claim 12.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Liao (US # 20230395427) in view of Jayantha (US # 20080217384) and further in view of Kuo (US # 20220415836).
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Regarding Claim 18, Liao (US # 20230395427) teaches a semiconductor package comprising:
a lower chip (100) including a lower bonding insulation layer (143), a first lower bonding pad (151), and a second lower bonding pad (153); and
an upper chip (300) disposed on the lower chip, the upper chip including an upper bonding insulation layer (333), a first upper bonding pad (343 on left), and a second upper bonding pad (343 on left) respectively hybrid-bonded to the lower bonding insulation layer, the first lower bonding pad, and the second lower bonding pad ([0089] teaches a hybrid bonding process where a “front surface 300F S of the second chip 300 may be bonded onto the front surface 100F S of the first chip 100”).
Although Liao discloses much of the claimed invention, it does not explicitly teach the particular bonding pad shapes and arrangement between the chips, specifically wherein the first lower bonding pad and the first upper bonding pad each having a tetragonal shape are one-dimensionally or planarily arranged in a first center region that is disposed near a center point of the lower chip and the upper chip,
the second lower bonding pad and the second upper bonding pad each having a rectangular shape are one-dimensionally or planarily arranged in a perpendicular direction, which is perpendicular to a radial direction from the center point, the second lower bonding pad and the second upper bonding pad being disposed in a first edge region that is disposed near corner points of the lower chip and the upper chip, and a long-axis length of the rectangular shape is greater than an axis length of the tetragonal shape, and
the second lower bonding pad and the second upper bonding pad of the first edge region are arranged to be one-dimensionally or planarily staggered, and partially staggered in the perpendicular direction perpendicular to the radial direction from the center point.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
For example, Jayantha (US # 20080217384) is in the same or analogous field, and it teaches a package wherein each of a first lower bonding pad (20) and a first upper bonding pad (22) have a first shape (circular) in which a first axis length (a first diameter of a circular pad) is the same as a second axis length (any other diameter of the circular pad) one-dimensionally or planarily, and the first
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lower bonding pad and the first upper bonding pad are disposed in a first center region (see the region containing feature 20 in annotated Fig. 4A) which is near a center point (that is the central portion, as shown in Fig. 3A) of the lower chip and the upper chip,
each of the second lower bonding pad (feature 26 is the same as the other pair of pads, but elliptical shaped; see [0032]) and the second upper bonding pad have a second shape (elliptical) in which a third axis length differs from a fourth axis length (Fig. 4B shows major and minor axes) one-dimensionally or planarily, and the second lower bonding pad and the second upper bonding pad are disposed in a first edge region (these elliptical bonding pads are shown the upper-right corner of the bonding area) which is near a corner point (shown) of the lower chip and the upper chip, and the third axis length is greater than the first axis length (major axis is longer, as shown in Fig. 4B), and
in the second lower bonding pad and the second upper bonding pad disposed in the first edge region, the third axis length is arranged in a direction perpendicular to a radial direction from the center point (the major axis of features 26 appear to be tangential to a radial vector pointing from the center of the bonding pad center point).
A person having ordinary skill in the art would have recognized that modifying the pad configuration of Liao with the pad configuration suggested by Jayantha would be obvious. Specifically, the modification suggested by Jayantha would be to employ a package wherein each of the first lower bonding pad and the first upper bonding pad have a first shape in which a first axis length is the same as a second axis length one-dimensionally or planarily, and the first lower bonding pad and the first upper bonding pad are disposed in a first center region which is near a center point of the lower chip and the upper chip, each of the second lower bonding pad and the second upper bonding pad have a second shape in which a third axis length differs from a fourth axis length one-dimensionally or planarily, and the second lower bonding pad and the second upper bonding pad are disposed in a first edge region which is near a corner point of the lower chip and the upper chip, and the third axis length is greater than the first axis length, and in the second lower bonding pad and the second upper bonding pad disposed in the first edge region, the third axis length is arranged in a direction perpendicular to a radial direction from the center point. The rationale for this obvious modification is that such a pad layout is optimal for a semiconductor chip that is prone to fatigue ([0034]) and for rotational alignment error tolerance.
Although Liao in view of Jayantha discloses much of the claimed invention, it does not explicitly teach the particular shapes for the bonding pads, specifically wherein the first shape is a tetragonal shape, and wherein the second shape is a rectangular shape.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
Consider a third reference, Kuo (US # 20220415836), which is in the same or analogous field, and it teaches a die pad configuration comprising a variety of shapes for the bonding pads, including having a tetragonal shape and or a rectangular shape ([0064] examiner considers a square pad to be tetragonal).
A person having ordinary skill in the art would have recognized that modifying the pad shapes of Liao in view of Jayantha with the square/tetragonal suggested by the variety of shape teaching of Kuo would be obvious. Specifically, the modification suggested by Kuo would be to employ a package wherein the first shape is a tetragonal shape, and wherein the second shape is a rectangular shape. Semiconductor designers choose rectangular pads when area efficiency, alignment, and routing integration are critical, especially with high-density interconnects. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of square and rectangular shaped pads are well known in the art (see MPEP 2144.01).
Regarding Claim 19, this claim is rejected for essentially the same reasons as claim 11.
Regarding Claim 20, this claim is rejected for essentially the same reasons as claim 12.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Liao (US # 20230395427) in view of Jayantha (US # 20080217384) and further in view of Yu (US # 20190067169).
Regarding Claim 11, Jayantha, as applied to claim 1, teaches the semiconductor package of claim 1, wherein the lower chip and the upper chip further comprise a third edge region (bottom-right corner of the bonding area) in which a fourth lower bonding pad and a fourth upper bonding pad each having the second shape (oval) in which the third axis length differs from the fourth axis length are disposed, the third edge region being disposed at a perimeter of the first center region and between the first center region and the first edge region (pretty much the same as the other edge regions, just a different corner).
Although Liao in view of Jayantha discloses much of the claimed invention, it does not explicitly teach the third axis length of the fourth lower bonding pad and the fourth upper bonding pad increases progressively toward the first edge region in the radial direction from the third edge region.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
For example, Yu (US # 20190067169) is in the same or analogous field, and it teaches the dimensions of bonding pads increasing progressively toward the peripheral edges region in the radial direction (see Fig. 9A, where 1741 is the largest and radially the furthest offset, and 1742 and 1743 are progressively smaller nearer the center; see also [0027]).
A person having ordinary skill in the art would have recognized that modifying the pad configuration of Liao in view of Jayantha with the pad sizing suggested by Yu would be obvious. Specifically, the modification suggested by Yu would be to employ a package wherein the third axis length of the fourth lower bonding pad and the fourth upper bonding pad increases progressively toward the first edge region in the radial direction from the third edge region. The rationale for this obvious modification is that progressively increasing the dimensions provides enhanced reliability ([0028]).
Conclusion
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899