DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The amended title overcomes the objection.
The objection to FIGS. 2I-2L is overcome by the replacements for these drawings.
The objection to FIG. 1B was not addressed by changing the drawings or by argument.
The amended claims overcome the indefiniteness rejections.
With respect to the enablement rejections, the applicant states on page 12 of the response that “the claims are apparatus claims drawn to the claimed structure, rather than to a method. Accordingly, Applicant respectfully submits that FIGS. 1A and 1B and their associated description support the limitations in claim 1, as apparently acknowledged by the Office.” It is not clear what is meant by “support” here; if the applicant is stating that claim 1 is not new matter, that is true. If the applicant is asserting that claim FIGS. 1A and 1B enable claim 1, the examiner disagrees, as these figures do not teach how to make the claimed structure.
On pages 12-14, the applicant cites the portion of the specification that states that the surface is roughened before laser cutting, that “[b]ecause the surface treatment process for increasing the surface roughness and reducing the permeability of a portion, on which the cutting process is to be performed, has been performed before the laser cutting process is performed, the laser cutting process may manufacture the semiconductor package 1000 having reduced generation of defects such as a crack. In addition, the laser cutting process may cut a kerf target at a narrow kerf width, and thus the productivity thereof may be improved.” The applicant then argues that “the laser LS will not pass through the surface 101 having the roughness treatment as well as the surface at the scribe lane SL that does not have the roughness treatment. Thus, for example, the laser LS will pass all the way through the chip 100, the molding layer 510 and the second carrier substrate 820 to separate the chips at the scribe line SL, but will not cut all the way through the molding layer 510 in the portions having the surface roughness. (Applicant notes that the cutting region CR1 in FIG. 2L is merely illustrative of the sense that the laser LS in the region whether the roughness treatment is applied will cut less deep than at the scribe lane SL where the roughness treatment is not applied.) In practice, one of ordinary skill would understand that, due to discussion of the surface roughness above, the laser LS would not penetrate all the way through the molding layer 510, thus leaving the wider portion illustrated in FIG. 1A, as illustrated by way of example below [from FIG. 2L]”. Emphasis added here. The applicant thus appears to argue that those in the art would understand that the center portion is not roughened, but the other parts of the scribe line are roughened, and thus a deeper cut is made there. This is not disclosed in the applicant’s specification. The long citation to the specification in the applicant’s arguments does not anywhere set this forth. Further complicating the matter is that the illustrated method does not actually produce the claimed structure with a jog in the sidewall of the molding. The applicant’s statement that those in the art would understand from the specification how to produce the claimed structure does not appear to the examiner to be true, as it is neither stated nor illustrated in the method figures. An adequately enabled patent application is not a mystery novel that leaves clues along the way that a clever reader can potentially put together with enough guessing. “Although the knowledge of one skilled in the art is indeed relevant, the novel aspect of an invention must be enabled in the patent.” Automotive Tech. V. BMW OF N. Am., 501 F.3d 1274, 1283 (Fed. Cir. 2007, emphasis added). It would be inappropriate to grant patent exclusivity for an invention that is not explicitly enabled.
See the art rejections below.
Drawings
The drawings are objected to due to the following: The specification states at [0071]: “In the semiconductor package 2000 as illustrated in FIG. 1B, the portion 510b having not undergone the surface treatment process may be formed flat, but the portion 510a having undergone the surface treatment process may not be flat but have a rough surface.” There is no package 2000 indicated in FIG. 1B.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4, 6-10 and 18-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 1 recites a molding layer over a chip stack, “wherein the molding layer comprises: a first sidewall from a lower end of the first semiconductor chip to a first height in a first direction perpendicular to the first surface of the first semiconductor chip; a second sidewall from the first height to a second height in the first direction; and a flat surface that extends from the first height in a second direction that is parallel with the first surface of the first semiconductor chip.” Claim 18 has a similar recitation. This arrangement with two sidewalls connected by a flat surface can be seen in FIG. 1A. There is no explanation of how to form such a structure. The method shown in FIGS. 2A-2L forms a device without such a flat surface in the molding layer. After the carrier 820 is removed ([0060]), the sidewalls of the molding layer are flat. There is no explanation of how the two different sidewalls that are at different positions are formed. Thus those in the art, reading the present specification, would not be enabled to produce this feature.
The remaining claims are rejected based on their dependencies.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites a singulated device, including a resulting sidewall from singulation. Claim 6, which depends from claim 1, recites that at least a portion of the second surface of the first semiconductor chip corresponds to a scribe lane portion of a semiconductor chip periphery. This would appear to indicate a device before singulation. Thus there is uncertainty as to the scope of claim 6, as it can not encompass a device both before and after singulation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Moon US 2017/0154872 A1, in view of Kim, US 2012/0168964 A1.
Claim 1: Moon discloses
a first semiconductor chip (110) including a first surface (upper surface, FIG. 3) and a second surface (bottom) opposite to the first surface;
at least one second semiconductor chip (120) stacked on the first surface of the first semiconductor chip;
and a molding layer (190) contacting the first surface of the first semiconductor chip and a sidewall of the at least one second semiconductor chip,
wherein the molding layer comprises:
a first sidewall (192) from a lower end of the first semiconductor chip (115) to a first height in a first direction perpendicular to the first surface of the first semiconductor chip;
a second sidewall (193) from the first height to a second height with respect to the lower end of the first semiconductor chip in the first direction;
and a flat surface (191) that extends from the first height in a second direction that is parallel with the first surface of the first semiconductor chip.
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Claim 1 also recites that “at least a portion of the second surface of the first semiconductor chip is not flat.” The term “semiconductor chip” describes a structure that includes a semiconductor material as well as other layers formed in and on the semiconductor material, including metal connection layers. See e.g. Kim at [0061]: “Each of the chip dies may include one or more third connection pads 72.” It was well known for such chips, such as Kim 70, to have a non-flat surface from pads 72:
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It was common in the art for semiconductor chips to have various layers and structures that created non-flat surfaces. Moon discloses that the bottom surface of chip 110 has external connectors 140, which were commonly pads together with solder balls, such as Kim discloses. It would have been obvious to have had such in Moon, which, as Kim illustrates, would lead to a non-flat surface.
Claim 2: the second height is located at a level higher than the first height with respect to the lower end of the first semiconductor chip (FIG. 3).
Claim 3: the second height corresponds to a height of an upper surface of the molding layer (FIG. 3).
Claim 4: the flat surface perpendicularly contacts an uppermost end of the first sidewall, and perpendicularly contacts a lowermost end of the second sidewall (FIG. 3). The examiner understands “perpendicularly contacts” to mean that the flat surface and the sidewall are perpendicular to each other where they contact.
Claim 9: the first semiconductor chip comprises a plurality of first through electrodes (113), and the at least one second semiconductor chip comprises a plurality of second through electrodes (124) that are electrically connected to the plurality of first through electrodes, respectively. “Through electrode” is interpreted here to mean an electrode which is electrically connected to the other side of the chip.
Claim 6: at least a portion of the second surface of the first semiconductor chip corresponds to a scribe lane portion of a semiconductor chip periphery: “a first semiconductor wafer 5110F having an edge boundary region 5111R corresponding to a scribe lane between first semiconductor die regions 5110C may be provided” [0086]. The scribe lane corresponds to the path that the scribing device will take through the device. The lane corresponds to a path through the entire chip, including both sides.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Kim and Lei, US 2014/0346641 A1.
Claim 7 recites that the at least a portion of the second surface of the first semiconductor chip has been treated by a surface treatment performed by a dicing blade or a grinder. This is a product-by-process claim, which only requires the resulting structure. Lei FIG. 4A, 410A discloses a roughening, which would be the result of blade or grinder treatment. It would have been obvious as a known dicing technique in the art ([0042].
Claim 8: Lei discloses that a first portion of the second surface of the first semiconductor chip is not flat and a second portion of the second surface of the first semiconductor chip molding layer is flat (FIG. 4A, 410A). Lei does not disclose that the first portion has a surface roughness 1000 times or more than a surface roughness of the second portion. However, this would have been a result-effective variable determined by the width of the laser ([0042]), and thus obvious.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Kim and Wolter, US 2008/0042261 A1. Moon discloses at [0046] that “The mold layer 190 may be an insulation layer such as a silica material or an epoxy material.” Both of these materials can be light transmitting; however, Moon does not disclose whether they are light transmitting in this case. Wolter discloses a die stack 280 encapsulated by molding layer 590 (FIG. 7), and discloses at [0055] that “some applications, such as those utilizing sensor arrays, may have transparent or partially transparent molds or encapsulants.” It would have been obvious to have had the molding layer of Moon be a light transmitting film for use in applications, such as sensors, that require light transmission.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Kim and Arrington, US 2021/0272885 A1. Moon discloses that
the first semiconductor device (100) comprises a first semiconductor chip (110) including a first surface (115) and a second surface opposite to the first surface, at least one second semiconductor chip mounted on the first semiconductor chip, and a molding layer covering the first surface of the first semiconductor chip and a sidewall of the at least one second semiconductor chip,
wherein the molding layer comprises a first sidewall from a lower end of the first semiconductor chip to a first height in a first direction that is perpendicular to the first surface of the first semiconductor chip, a second sidewall from the first height to a second height in the first direction, and a flat surface that extends at the first height in a second direction that is parallel with the first surface of the first semiconductor chip.
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Claim 18 also recites that “at least a portion of the second surface of the first semiconductor chip is not flat.” The term “semiconductor chip” describes a structure that includes a semiconductor material as well as other layers formed in and on the semiconductor material, including metal connection layers. See e.g. Kim at [0061]: “Each of the chip dies may include one or more third connection pads 72.” It was well known for such chips, such as Kim 70, to have a non-flat surface from pads 72:
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It was common in the art for semiconductor chips to have various layers and structures that created non-flat surfaces. Moon discloses that the bottom surface of chip 110 has external connectors 140, which were commonly pads together with solder balls, such as Kim discloses. It would have been obvious to have had such in Moon, which, as Kim illustrates, would lead to a non-flat surface.
Moon does not show the semiconductor device packaged with an interposer. However, this was known in the art. See Arrington, FIG. 1B, which discloses
a package substrate (105);
an interposer (110) on the package substrate;
a first semiconductor device (120B) mounted on the interposer;
a second semiconductor device (120A) mounted on the interposer and spaced apart from the first semiconductor device, the second semiconductor device being electrically connected to the first semiconductor device via the interposer;
“the interposer may comprise conductive features to provide routing over the interposer 110. For example, the routing may connect a first die 120A to a second die 120B.”
and a package molding layer (122) arranged on the interposer, and covering a sidewall of the first semiconductor device and a sidewall of the second semiconductor device.
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It would have been obvious to have used such a packaging with the device of Moon as a known way to incorporate such a device into a package with other devices.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Kim, Arrington and Lin, US 2016/0276307 A1. Lin does not disclose that
wherein a sidewall of the package molding layer is connected to a sidewall of the interposer. However, this was common in the art. See Lin, FIGS 3b-3d, which shows an interposer 150 with molding 180 singulated by cutting, which forms coplanar (and thus connected) sidewalls of the interposer and the molding layer. It would have been obvious to have such a configuration in Arrington as the result of a known and common way of forming multiple interposers with attached chips at once.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Kim, Arrington and Wolter. Moon discloses at [0046] that “The mold layer 190 may be an insulation layer such as a silica material or an epoxy material.” Both of these materials can be light transmitting; however, Moon does not disclose whether they are light transmitting in this case. Wolter discloses a die stack 280 encapsulated by molding layer 590 (FIG. 7), and discloses at [0055] that “some applications, such as those utilizing sensor arrays, may have transparent or partially transparent molds or encapsulants.” It would have been obvious to have had the molding layer of Moon be a light transmitting layer as known in the art, and for use in applications, such as sensors, that require light transmission.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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