DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Pursuant to the election without traverse on March 26, 2026, unelected claims 11-17 are withdrawn from consideration.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner proposes: CHIP STACK WITH MOLDING HAVING A STEP IN ITS SIDEWALL
Drawings
The drawings are objected to for the following reasons:
FIGS. 2I-2L show element 510 as a part of 820; paragraph [0059] sets forth that “Referring to FIG. 2H, onto the upper surface of the molding layer 510 and the upper surface of the fourth semiconductor chip 400, which have been planarized, a second carrier substrate 820 may be attached.” Molding layer 510 appears to be correctly identified in FIG. 2h, but not in FIGS. 2I-2L.
The specification states at [0071]: “In the semiconductor package 2000 as illustrated in FIG. 1B, the portion 510b having not undergone the surface treatment process may be formed flat, but the portion 510a having undergone the surface treatment process may not be flat but have a rough surface.” There is no package 2000 indicated in FIG. 1B.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-10 and 18-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 1 recites a molding layer over a chip stack, “wherein the molding layer comprises: a first sidewall from a lower end of the first semiconductor chip to a first height in a first direction perpendicular to the first surface of the first semiconductor chip; a second sidewall from the first height to a second height in the first direction; and a flat surface that extends from the first height in a second direction that is parallel with the first surface of the first semiconductor chip.” Claim 18 has a similar recitation. This arrangement with two sidewalls connected by a flat surface can be seen in FIG. 1A. There is no explanation of how to form such a structure. The method shown in FIGS. 2A-2L forms a device without such a flat surface in the molding layer. After the carrier 820 is removed ([0060]), the sidewalls of the molding layer are flat. There is no explanation of how the two different sidewalls that are at different positions are formed. Thus those in the art, reading the present specification, would not be enabled to produce this feature.
Claims 5-8 recite the rough or “not flat” surface of the molding layer. The specification at [0047] states that there are rough and not rough portions of the molding layer, but in the manufacturing method of the applicant, only semiconductor layer 120 is roughed (ST, FIG. 2J). Thus there is no explanation of the process of roughening the surface of the molding layer. Specifically with respect to claim 8, there is no indication as to how there would be a rough and not rough portion of the surface of the molding layer.
The remaining claims are rejected based on their dependencies.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a first sidewall from a lower end of the first semiconductor chip to a first height in a first direction perpendicular to the first surface of the first semiconductor chip; a second sidewall from the first height to a second height in the first direction”. Claim 18 has a similar recitation. Claim 2 recites that “the second height is located at a level higher than the first height.” The lower end LE is shown in FIG. 1A; it is the top of chip 110 in the figure. This is only the lower end of the chip if the device is viewed inverted from how it is seen in FIG. 1A. However, the device must be as seen in FIG. 1A for the second height H2 to be higher than the first height H2. The relative heights must be based on a consistent orientation of the device. As the orientations are not consistent, it creates uncertainty as to the relative positions of the elements.
The remaining claims are rejected based on their dependencies.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 9 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Moon, US 2017/0154872 A1.
Claim 1: Moon discloses
a first semiconductor chip (110) including a first surface (upper surface, FIG. 3) and a second surface (bottom) opposite to the first surface;
at least one second semiconductor chip (120) stacked on the first surface of the first semiconductor chip;
and a molding layer (190) contacting the first surface of the first semiconductor chip and a sidewall of the at least one second semiconductor chip,
wherein the molding layer comprises:
a first sidewall (192) from a lower end of the first semiconductor chip (115) to a first height in a first direction perpendicular to the first surface of the first semiconductor chip;
a second sidewall (193) from the first height to a second height in the first direction;
and a flat surface (191) that extends from the first height in a second direction that is parallel with the first surface of the first semiconductor chip.
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Claim 2: the second height is located at a level higher than the first height (FIG. 3).
Claim 3: the second height corresponds to a height of an upper surface of the molding layer (FIG. 3).
Claim 4: the flat surface perpendicularly contacts an uppermost end of the first sidewall, and perpendicularly contacts a lowermost end of the second sidewall (FIG. 3). The examiner understands “perpendicularly contacts” to mean that the flat surface and the sidewall are perpendicular to each other where they contact.
Claim 9: the first semiconductor chip comprises a plurality of first through electrodes (113), and the at least one second semiconductor chip comprises a plurality of second through electrodes (124) that are electrically connected to the plurality of first through electrodes, respectively. “Through electrode” is interpreted here to mean an electrode which is electrically connected to the other side of the chip.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Wolter, US 2008/0042261 A1. Moon discloses at [0046] that “The mold layer 190 may be an insulation layer such as a silica material or an epoxy material.” Both of these materials can be light transmitting; however, Moon does not disclose whether they are light transmitting in this case. Wolter discloses a die stack 280 encapsulated by molding layer 590 (FIG. 7), and discloses at [0055] that “some applications, such as those utilizing sensor arrays, may have transparent or partially transparent molds or encapsulants.” It would have been obvious to have had the molding layer of Moon be a light transmitting film for use in applications, such as sensors, that require light transmission.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Arrington, US 2021/0272885 A1. Moon discloses that
the first semiconductor device (100) comprises a first semiconductor chip (110) including a first surface (115) and a second surface opposite to the first surface, at least one second semiconductor chip mounted on the first semiconductor chip, and a molding layer covering the first surface of the first semiconductor chip and a sidewall of the at least one second semiconductor chip,
wherein the molding layer comprises a first sidewall from a lower end of the first semiconductor chip to a first height in a first direction that is perpendicular to the first surface of the first semiconductor chip, a second sidewall from the first height to a second height in the first direction, and a flat surface that extends at the first height in a second direction that is parallel with the first surface of the first semiconductor chip.
Moon does not show the semiconductor device packaged with an interposer. However, this was known in the art. See Arrington, FIG. 1B, which discloses
a package substrate (105);
an interposer (110) on the package substrate;
a first semiconductor device (120B) mounted on the interposer;
a second semiconductor device (120A) mounted on the interposer and spaced apart from the first semiconductor device, the second semiconductor device being electrically connected to the first semiconductor device via the interposer;
“the interposer may comprise conductive features to provide routing over the interposer 110. For example, the routing may connect a first die 120A to a second die 120B.”
and a package molding layer (122) arranged on the interposer, and covering a sidewall of the first semiconductor device and a sidewall of the second semiconductor device.
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It would have been obvious to have used such a packaging with the device of Moon as a known way to incorporate such a device into a package with other devices.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Arrington and Lin, US 2016/0276307 A1. Lin does not disclose that
wherein a sidewall of the package molding layer is connected to a sidewall of the interposer. However, this was common in the art. See Lin, FIGS 3b-3d, which shows an interposer 150 with molding 180 singulated by cutting, which forms coplanar (and thus connected) sidewalls of the interposer and the molding layer. It would have been obvious to have such a configuration in Arrington as the result of a known and common way of forming multiple interposers with attached chips at once.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Arrington and Wolter. Moon discloses at [0046] that “The mold layer 190 may be an insulation layer such as a silica material or an epoxy material.” Both of these materials can be light transmitting; however, Moon does not disclose whether they are light transmitting in this case. Wolter discloses a die stack 280 encapsulated by molding layer 590 (FIG. 7), and discloses at [0055] that “some applications, such as those utilizing sensor arrays, may have transparent or partially transparent molds or encapsulants.” It would have been obvious to have had the molding layer of Moon be a light transmitting layer as known in the art, and for use in applications, such as sensors, that require light transmission.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Kawato, US 20150262975 A1, which shows a molding layer 14 with a similar side arrangement (FIG. 6B).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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