DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 07 Nov 2023 for application number 18/387,702. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and Claims.
Claims 1-20 are presented for examination. Elected claims 1-20 are examined below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Device Embodiment I. corresponding to claims 1-20 in the reply filed on 12 Mar 2026 is acknowledged. The traversal is on the ground(s) that unduly extensive and burdensome search would not be required. This is not found persuasive because, as can be seen in Figs. 1-2 and 10A-C, the configuration and number of conductive patterns, dielectric layers, and insulating layers are clearly different. Therefore, searching for both structures would require serious search and examination burden.
The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07 Nov 2023 and 12 Jun 2026 were filed before the mailing of this Office Action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-17 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. [hereinafter as Lee] (US 2018/0144873 A1).
In reference to claim 1, Lee teaches An integrated circuit device comprising:
a substrate [substrate 10; Fig. 2, para 0023];
a lower insulating film [bottommost dielectric layer 23; Fig. 2, para 0024] on the substrate [10], the lower insulating film [bottommost 23] comprising a device; and
a capacitor structure [body 20; Figs. 1-2, para 0022] on the lower insulating film [bottommost 23],
wherein the capacitor structure [20] comprises:
a plurality of first conductive patterns [first electrode layer 21; Fig. 2, para 0039] sequentially stacked on the lower insulating film [bottommost 23] and spaced apart from each other;
a plurality of second conductive patterns [second electrode layer 22; Fig. 2, para 0039] on the plurality of first conductive patterns [21] and spaced apart from each other, wherein each second conductive pattern [22] of the plurality of second conductive patterns [22] is on a corresponding first conductive pattern [21] of the plurality of first conductive patterns [21];
a first via [first via 31; Fig. 2, para 0064] at a first side of the capacitor structure [20], wherein the first via [31] physically contacts and is electrically connected to the plurality of first conductive patterns [21], and is not electrically connected to the plurality of second conductive patterns [22]; and
a second via [second via 32; Fig. 2, para 0064] at a second side of the capacitor structure [20], wherein the second side is opposite to the first side and faces the first side, and wherein the second via [32] physically contacts and is electrically connected to the plurality of second conductive patterns [22], and is not electrically connected to the plurality of first conductive patterns [31].
In reference to claim 2, Lee teaches The integrated circuit device of claim 1, wherein the first via [31] is not in physical contact with the plurality of second conductive patterns [22], and wherein the second via [32] does not physically contact the plurality of first conductive patterns [21].
In reference to claim 3, Lee teaches The integrated circuit device of claim 1, wherein the capacitor structure further includes a plurality of insulating spacers [insulating layer 27; Fig. 2, para 0081] at side walls of the plurality of first conductive patterns [21] and side walls of the plurality of second conductive patterns [22],
wherein each insulating spacer [27] of the plurality of insulating spacers [27] comprises:
a first side wall [first side wall; see annotated Fig. 2 below] contacting at least one conductive pattern of the plurality of first conductive patterns [21] and the plurality of second conductive patterns [22]; and
a second side wall [second side wall; see annotated Fig. 2 below] contacting one via from among the first via [31] and the second via [32], wherein the second side wall is opposite to the first side wall.
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In reference to claim 4, Lee teaches The integrated circuit device of claim 3, wherein the plurality of insulating spacers [27] comprises a first insulating spacer [first insulating spacer; see annotated Fig. 2 above] contacting the first via [31] and a second insulating spacer [second insulating spacer; see annotated Fig. 2 above] contacting the second via [32], and wherein a level of a top surface of the first insulating spacer [first insulating spacer] different from a level of a top surface of the second insulating spacer [second insulating spacer].
In reference to claim 5, Lee teaches The integrated circuit device of claim 1, wherein a horizontal cross-sectional area of each of the first via [31] and the second via [32] non-linearly decreases in a direction toward the substrate [10].
In reference to claim 6, Lee teaches The integrated circuit device of claim 1, wherein a first side wall [first side wall; see annotated Fig. 2 above] of each of the first via [31] and the second via [32] faces the plurality of first conductive patterns [21] and the plurality of second conductive patterns [22], and has a stair shape [27 have step-like arrangement].
In reference to claim 7, Lee teaches The integrated circuit device of claim 6, wherein a second side wall [second side wall; see annotated Fig. 2 above] of each of the first via [31] and the second via [32] declines in a direction toward the plurality of first conductive patterns [21] and the plurality of second conductive patterns [22], and wherein the second side wall [second side wall] is opposite to the first side wall [second side wall] and faces away from the first side wall [first side wall].
In reference to claim 8, Lee teaches The integrated circuit device of claim 1, wherein the capacitor structure further comprises a dielectric film [dielectric layers 23; Fig. 2, para 0022] between a first conductive pattern [21] of the plurality of first conductive patterns and a second conductive pattern [22] of the plurality of second conductive patterns, wherein a conductive pattern from among the first conductive pattern [21] and the second conductive pattern [22] is on the dielectric film [23], and wherein an area of a top surface of the dielectric film [23] is substantially equal to an area of a bottom surface of the conductive pattern [21/22].
In reference to claim 9, Lee teaches The integrated circuit device of claim 1, wherein the capacitor structure further comprises: a first dielectric film [23, specifically “1DF”; see annotated Fig. 2 above, para 0022] on a first conductive pattern [21] of the plurality of first conductive patterns, a second conductive pattern [22] of the plurality of second conductive patterns, wherein the second conductive pattern [22] is on the first dielectric film [23]; and a second dielectric film [23, specifically “2DF”; see annotated Fig. 2 above, para 0022] on the second conductive pattern [22], wherein a top surface of the first conductive pattern [21] comprises a first portion contacting the first via [31] and a second portion contacting the first dielectric film [1DF], and wherein a top surface of the second conductive pattern [22] comprises a third portion contacting the second via [32] and a fourth portion contacting the second dielectric film [2DF].
In reference to claim 10, Lee teaches The integrated circuit device of claim 1, further comprising: a first wiring [first electrode pad 51; Fig. 2, para 0075] horizontally extending on the first via [31], the first wiring [51] contacting the first via [31] and having a first horizontal cross-sectional area which is wider than the first via [51 is wider than portions of 31]; and a second wiring [second electrode pad 52; Fig. 2, para 0075] horizontally extending on the second via [32], the second wiring [52] contacting the second via [32] and having a second horizontal cross-sectional area which is wider than the second via [52 is wider than portions of 32], wherein the first wiring [51] overlaps a portion of each of the plurality of first conductive patterns [21], and the second wiring [52] overlaps a portion of each of the plurality of second conductive patterns [22].
In reference to claim 11, Lee teaches An integrated circuit device comprising:
a substrate [substrate 10; Fig. 2, para 0023];
a lower insulating film [bottommost dielectric layer 23; Fig. 2, para 0024] on the substrate [10], the lower insulating film [bottommost 23] comprising a device; and
a capacitor structure [body 20; Figs. 1-2, para 0022] on the lower insulating film [bottommost 23],
wherein the capacitor structure comprises:
a first conductive pattern [first electrode layer 21, specifically “1CP”; see annotated Fig. 2 above, para 0039] on the lower insulating film;
a second conductive pattern [second electrode layer 22, specifically “2CP”; see annotated Fig. 2 above, para 0039] on the first conductive pattern [1CP];
a third conductive pattern [first electrode layer 21, specifically “3CP”; see annotated Fig. 2 above, para 0039] on the second conductive pattern [2CP];
a fourth conductive pattern [second electrode layer 22, specifically “4CP”; see annotated Fig. 2 above, para 0039] on the third conductive pattern [3CP];
a first via [first via 31; Fig. 2, para 0064] at a first side of the capacitor structure, wherein the first via [31] being physically contacts and is electrically connected to the first conductive pattern [1CP] and the third conductive pattern [3CP], and is not electrically connected to the second conductive pattern [2CP] and the fourth conductive pattern [4CP]; and
a second via [second via 32; Fig. 2, para 0064] at a second side of the capacitor structure, wherein the second side is opposite to the first side and faces the first side, and wherein the second via [32] physically contacts and is electrically connected to the second conductive pattern [2CP] and the fourth conductive pattern [4CP] and is not electrically connected to the first conductive pattern [1CP] and the third conductive pattern [3CP].
In reference to claim 12, Lee teaches The integrated circuit device of claim 11, wherein the first via [31] does not physically contact the second conductive pattern [2CP] and the fourth conductive [4CP] pattern, and the second via [32] does not physically contact the first conductive pattern [1CP] and the third conductive pattern [3CP].
In reference to claim 13, Lee teaches The integrated circuit device of claim 11, wherein the capacitor structure further comprises a plurality of insulating spacers [insulating layer 27; Fig. 2, para 0081] at a side wall of at least one of the first conductive pattern [1CP], the second conductive pattern [2CP], the third conductive pattern [3CP], and the fourth conductive pattern [4CP], wherein each insulating spacer [27] of the plurality of insulating spacers comprises: a first side wall contacting the at least one of the first conductive pattern [1CP], the second conductive pattern [2CP], the third conductive pattern [3CP], and the fourth conductive pattern [4CP], and a second side wall contacting one via from among the first via [31] and the second via [32], wherein the second side wall is opposite to the first side wall.
In reference to claim 14, Lee teaches The integrated circuit device of claim 11, wherein a horizontal cross-sectional area of each of the first via [31] and the second via [32] non-linearly decreases in a direction toward the substrate [10].
In reference to claim 15, Lee teaches The integrated circuit device of claim 11, wherein the capacitor structure further comprises: a first dielectric film [dielectric layers 23, specifically “1DF”; see annotated Fig. 2 above, para 0022] between the first conductive pattern [1CP] and the second conductive pattern [2CP]; a second dielectric film [23, specifically “2DF”; see annotated Fig. 2 above, para 0022] between the second conductive pattern [2CP] and the third conductive pattern [3CP]; and a third dielectric film [23, specifically “3DF”; see annotated Fig. 2 above, para 0022] between the third conductive pattern [3CP] and the fourth conductive pattern [4CP], wherein an area of a top surface of the first dielectric film [1DF] is substantially equal to an area of a bottom surface of the second conductive pattern [2CP], wherein an area of a top surface of the second dielectric film [2DF] is substantially equal to an area of a bottom surface of the third conductive pattern [3CP], and wherein an area of a top surface of the third dielectric film [3DF] is substantially equal to an area of a bottom surface of the fourth conductive pattern [4CP].
In reference to claim 16, Lee teaches The integrated circuit device of claim 11, further comprising: a first wiring [first electrode pad 51; Fig. 2, para 0075] horizontally extending on the first via [31], the first wiring [51] contacting the first via [31] and having a first horizontal cross-sectional area which is wider than the first via [51 is wider than portions of 31]; and a second wiring [second electrode pad 52; Fig. 2, para 0075] horizontally extending on the second via [32], the second wiring [52] contacting the second via [32] and having a second horizontal cross-sectional area which is wider than the second via [32], wherein the first wiring [51] overlaps a portion of the first conductive pattern [1CP] and a portion of the third conductive pattern [3CP], and the second wiring [52] overlaps a portion of the second conductive pattern [2CP] and a portion of the fourth conductive pattern [4CP].
In reference to claim 17, Lee teaches The integrated circuit device of claim 11, wherein an area of a top surface of the first conductive pattern [1CP] is larger than an area of a top surface of the second conductive pattern [2CP], wherein the area of the top surface of the second conductive pattern [2CP] is larger than [there is a top surface of 2CP which is larger than area of top surface of 3CP] an area of a top surface of the third conductive pattern [3CP], and wherein the area of the top surface of the third conductive pattern [3CP] is larger than [there is a top surface of 3CP which is larger than area of top surface of 4CP] an area of a top surface of the fourth conductive pattern [4CP].
In reference to claim 19, Lee teaches An integrated circuit device comprising:
a substrate [substrate 10; Fig. 2, para 0023];
a lower insulating film [bottommost dielectric layer 23; Fig. 2, para 0024] on the substrate [10], the lower insulating film [bottommost 23] comprising a device; and
a capacitor structure [body 20; Figs. 1-2, para 0022] on the lower insulating film [bottommost 23],
wherein the capacitor structure comprises:
a plurality of first conductive patterns [first electrode layer 21; Fig. 2, para 0039] sequentially stacked on the lower insulating film [bottommost 23] and spaced apart from each other;
a plurality of second conductive patterns [second electrode layer 22; Fig. 2, para 0039] on the plurality of first conductive patterns [21] and spaced apart from each other, wherein each second conductive pattern [22] of the plurality of second conductive patterns [22] is on a corresponding first conductive pattern [21] of the plurality of first conductive patterns [21];
a first via [first via 31; Fig. 2, para 0064] at a first side of the capacitor structure, wherein the first via [31] physically contacts and is electrically connected to the plurality of first conductive patterns [21], and does not physically contact and is insulated from the plurality of second conductive patterns [22]; and
a second via [second via 32; Fig. 2, para 0064] at a second side of the capacitor structure, wherein the second side is opposite to the first side and faces the first, and wherein the second via [32] physically contacts and is electrically connected to the plurality of second conductive patterns [22], and does not physically contact and is insulated from the plurality of first conductive patterns [21],
wherein a horizontal cross-sectional area of each of the first via [31] and the second via [32] non-linearly decreases in a direction toward the substrate [10],
wherein a first side wall [first side wall; see annotated Fig. 2 above] of each of the first via [31] and the second via [32] faces the plurality of first conductive patterns [21] and the plurality of second conductive patterns [22] and has a stair shape,
wherein a second side wall [second side wall; see annotated Fig. 2 above] of each of the first via [31] and the second via [32] declines in a direction toward the plurality of first conductive patterns [21] and the plurality of second conductive patterns [22], and
wherein the second side wall [second side wall] is opposite to the first side wall [first side wall] and faces away from the first side wall [first side wall].
In reference to claim 20, Lee teaches The integrated circuit device of claim 19, wherein the capacitor structure further includes:
a plurality of insulating spacers [insulating layer 27; Fig. 2, para 0081] at side walls of the plurality of first conductive patterns [21] and side walls of the plurality of second conductive patterns [22]; and
a dielectric film [dielectric layers 23; Fig. 2, para 0022] between a first conductive pattern [21, specifically “1CP”; see annotated Fig. 2 above] of the plurality of first conductive patterns [21] and a second conductive pattern [22, specifically “2CP”; see annotated Fig. 2 above] of the plurality of second conductive patterns [22],
wherein each insulating spacer [27] of the plurality of insulating spacers comprises:
a first spacer side wall [“first side wall” of 27; see annotated Fig. 2 above] contacting at least one conductive pattern of the plurality of first conductive patterns [21] and the plurality of second conductive patterns [22],
a second spacer side wall [“second side wall” of 27; see annotated Fig. 2 above] contacting one via from among the first via [31] and the second via [32], wherein the second spacer side wall [“second side wall” of 27] is opposite to the first spacer side wall [“first side wall” of 27],
wherein a conductive pattern [21/22] from among the first conductive pattern [21] and the second conductive pattern [22] is on the dielectric film [23], and
wherein an area of a top surface of the dielectric film [23] is substantially equal to an area of a bottom surface of the conductive pattern [21/22].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Chen et al. [hereinafter as Chen] (US 11,302,627 B1).
In reference to claim 18, Lee teaches the invention of claim 11.
However Lee does not explicitly teach The integrated circuit device of claim 11, wherein each of the first conductive pattern, the second conductive pattern, the third conductive pattern, and the fourth conductive pattern comprises at least one from among cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), a titanium nitride (TiN) film, a titanium silicon nitride (TiSiN) film, a titanium aluminum nitride (TiAlN) film, a tantalum nitride (TaN) film, a tantalum silicon nitride (TaSiN) film, a tantalum aluminum nitride (TaAlN) film, a tungsten nitride film (WN) film.
Chen teaches The integrated circuit device of claim 11, wherein each of the first conductive pattern, the second conductive pattern, the third conductive pattern, and the fourth conductive pattern comprises at least one from among cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), a titanium nitride (TiN) film, a titanium silicon nitride (TiSiN) film, a titanium aluminum nitride (TiAlN) film, a tantalum nitride (TaN) film, a tantalum silicon nitride (TaSiN) film, a tantalum aluminum nitride (TaAlN) film, a tungsten nitride film (WN) film [Fig. 1A, col. 6, lines 20-21 disclose that conductive layers 106 may be W, Co, Cu, Al, etc.].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Lee and Chen before the effective filing date of the claimed invention, to include the conductive materials as disclosed by Chen into the semiconductor device of Lee in order to obtain a semiconductor device that has conductive patterns composed of materials such as W and Co.
One of ordinary skill in the art would be motivated to obtain a semiconductor device that has conductive patterns composed of materials such as W and Co to provide the predictable result of providing optimal performance due to the high-aspect-ratio structural integrity, excellent electromigration resistance, and thermal and mechanical robustness of materials such as W and Co.
Examiner’s Note
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure as follows. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR § 1.111(0).
Shin et al. (US-20180040422-A1) discloses a stacked capacitor with vias and insulating layers [Fig. 2].
Conclusion
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/ANDREW CHUNG/
Examiner, Art Unit 2898
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