DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claims 1-11, 14-21, and 24 stand rejected under Section 103. Claim 17 stands objected to for an informality. The specification stands objected to for informalities. During an interview held March 3, 2026, Examiner Hall noted further informalities in claims 16, 18, and 19. Claims 12, 13, 22, 23, and 25-40 were previously canceled.
Applicants amended claims 1, 3, 5, 8, 14, 16-19, and 24, and provided amendments to the specification. Applicants argue that the application is in condition for allowance.
Turning first to the specification: Applicants’ amendments address the previously noted specification objections and are accepted and entered. No new matter has been added. The previously noted specification objections are withdrawn.
Claim objections: Applicants’ amendments address the informalities identified in the Non-Final Office Action, as well as the additional informalities identified during the March 3, 2026 interview. These amendments are accepted and entered. No new matter has been added. The previously noted claim objections are withdrawn.
Section 103 rejections: Applicants have amended independent claims 1, 14, and 24 to require that an uppermost surface of the first through via contacts a lowermost surface of the first pad (claim 1); an uppermost surface of one of the through vias contacts a lowermost surface of one of the second pads (claim 14); and “an uppermost surface of one of the through vias contact a lowermost surface of one of the second pads” (claim 24). Jin, the primary reference, discloses a pad that is formed in a recess surrounding the through via, resulting in a ring shape. Thus, for Jin, the uppermost surface of the through via cannot contact the lowermost surface of the pad. For the secondary reference, Lee, the through via is inside a lower, central recess of the pad. Lee, like Jin, includes a protection layer which surrounds the pad and upper portion of the through via. Thus, Jin could be modified to include the Lee pad-through via arrangement. This would result in an upper surface of the through via being in contact with a lower surface of the pad, the difference being upper surface vs. uppermost surface and lower surface vs. lowermost surface. Applicants’ arguments are unclear as to the patentable significance of the uppermost surface over an upper surface, or the patentable significance of the lowermost surface over a lower surface. Because the uppermost surface is not patentably significant over an upper surface and because the lowermost surface is not patentably significant over a lower surface, the rejections of the independent claims are maintained.
In the alternative, these claims are rejected in view of Suh, U.S. Pat. Pub. No. 2021/0125955, Figures 1A and 2A. Suh discloses a through via (360), which vertically penetrates a semiconductor substrate (base (310)) and protrudes from the inactive surface of the semiconductor substrate (310); a protection layer (350, 440, 430) that covers the inactive surface of the semiconductor substrate (310) and buried the through via (360); a pad (420) that penetrates at least a portion of the protection layer (350, 440, 430) and is coupled to the through via (360); wherein an uppermost surface of the through via (360) contacts a lowermost surface of the pad (420). Suh specification ¶¶ 20-54.
Applicants also argue that claim 7 is allowable because the secondary art, Naik, does not disclose that the liner layer extends from between the first semiconductor substrate and the first dielectric layer to between a lateral surface of the through via and the first dielectric layer. Applicants’ points are well made and well taken. The rejections of claim 7 and its dependent claims as well as claim 18 and its dependent claim are withdrawn.
Updated searches yielded no further prior art that anticipates or renders obvious the claims, or that could be used with previously cited prior art to render obvious the claims.
Claim Objections
Claim 24 is objected to because of the following informalities:
Claim 24, second to last line of the claim: Change “contact” to “contacts” for subject-verb agreement.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 10, 11, 14-17, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Jin, U.S. Pat. Pub. No. 2023/0010936, Figures 5-6B and 1-3 and further in view of Lee, U.S. Pat. Pub. No. 2016/0155686, Figures 1C, 2C, or in the alternative, further in view of Suh, U.S. Pat. Pub. No. 2021/0125955, Figures 1A and 2A.
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Lee Figures 1C, 2C:
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Regarding claim 1: Jin Figures 5-6B disclose a semiconductor package, comprising: a first structure (upper middle chip (300)); and a second structure (lower middle chip (300)), wherein the first structure (upper middle chip (300)) comprises: a first semiconductor substrate that (310) has an active surface (319) on which a first semiconductor device is configured to be provided, and an inactive surface (317) opposite to the active surface (319); a first through via (330) that vertically penetrates the first semiconductor substrate (310) and protrudes from the inactive surface (317) of the first semiconductor substrate (310); a first protection layer (320, corresponding to pad insulating layer (120) in Jin Figures 1-3, Jin specification ¶ 68) that covers the inactive surface (317) of the first semiconductor substrate (310) and surrounds the first through via (330); and a first pad (340) that penetrates at least a portion of the first protection layer (320) and is coupled to the first through via (330), wherein the first protection layer (320) comprises: a first dielectric layer (321, corresponding to first insulating layer (121) in Jin Figures 1-3, id.) that is on the inactive surface (317) of the first semiconductor substrate (310); a second dielectric layer (325, corresponding to third insulating layer (125) in Jin Figures 1-3, id.) on the first dielectric layer (321); and a silicon nitride insulating layer (323, corresponding to second insulating layer (123) in Jin Figures 1-3, id.) between the first dielectric layer (321) and the second dielectric layer (325) and in contact with a lateral surface of the first pad (340), wherein the second structure (lower middle chip (300)) comprises a second pad (371), wherein the first structure (upper middle chip (300)) and the second structure (lower middle chip (300)) are bonded to each other, and wherein the first pad (340) and the second pad (371) are in contact with each other. Jin specification ¶¶ 64-73, 24-49. Jin does not disclose that the a first protection layer that covers the inactive surface of the first semiconductor substrate and buries the first through via. Jin also does not disclose that the silicon nitride insulating layer is an etch stop layer. Lastly, Jin does not disclose that an uppermost surface of the first through via (330) contacts a lowermost surface of the first pad (340).
Lee Figures 1C and 2C, directed to similar subject matter, discloses a first structure (10C) comprises: a first semiconductor substrate (11) that has an active surface (S1) on which a first semiconductor device (15) is configured to be provided, and an inactive surface (S2) opposite to the active surface (S1); a first through via (50) that vertically penetrates the first semiconductor substrate (11) and protrudes from the inactive surface (S2) of the first semiconductor substrate (11); a first protection layer (71, 72, 73, 74: 75, 76) that covers the inactive surface (S2) of the first semiconductor substrate (11) and buries the first through via (50); and a first pad (90) that penetrates at least a portion of the first protection layer (71, 72, 73, 74: 75, 76) and is coupled to the first through via (50), wherein the first protection layer (71, 72, 73, 74: 75, 76) comprises: a first dielectric layer (71) that is on the inactive surface (S2) of the first semiconductor substrate (11); a second dielectric layer (73) on the first dielectric layer (71); and an etch stop layer (72) (made of silicon nitride, Lee specification ¶ 64) between the first dielectric layer (71) and the second dielectric layer (73) and in contact with a lateral surface of the first pad (90), wherein an upper surface of the first through via (50) contacts a lower surface of the first pad (90). Lee specification ¶¶ 41-44, 60-65. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Jin to include the Lee design because the modification would have involved the substitution of an equivalent known for the same purpose.
As for the difference between the difference being upper surface vs. uppermost surface and lower surface vs. lowermost surface, applicants’ arguments are unclear as to the patentable significance of the uppermost surface over an upper surface, or the patentable significance of the lowermost surface over a lower surface. Because the uppermost surface is not patentably significant over an upper surface and because the lowermost surface is not patentably significant over a lower surface, claim 1 is rejected as a patentably insignificant shape variation over the prior art..
In the alternative, Suh Figures 1A and 2A disclose a through via (360), which vertically penetrates a semiconductor substrate (base (310)) and protrudes from the inactive surface of the semiconductor substrate (310); a protection layer (350, 440, 430) that covers the inactive surface of the semiconductor substrate (310) and buried the through via (360); a pad (420) that penetrates at least a portion of the protection layer (350, 440, 430) and is coupled to the through via (360); wherein an uppermost surface of the through via (360) contacts a lowermost surface of the pad (420). Suh specification ¶¶ 20-54. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Suh design because the modification would have involved the substitution of an equivalent known for the same purpose. This renders obvious claim 1.
Regarding claim 2, which depends from claim 1: The combination discloses wherein the etch stop layer (Lee 72) separates the first dielectric layer (Lee 71) from the second dielectric layer (Lee 73). See Lee Figure 1C, 2C.
Regarding claim 3, which depends from claim 1: The combination discloses a distance from the etch stop layer (Lee 72) to the first semiconductor substrate (Lee 11) is greater than a distance from the lowermost surface of the first pad (Lee 90) to the first semiconductor substrate (Lee 11). See id.
Regarding claim 4, which depends from claim 1: The combination discloses the first through via (Lee 50) vertically penetrates at least a portion of the first dielectric layer (Lee 71), and wherein the first pad (Lee 90) vertically penetrates the second dielectric layer (Lee 73) and the etch stop layer (Lee 72). See id.
Regarding claim 5, which depends from claim 1: The combination discloses a distance between a contact interface, between the uppermost surface of the first through via (Lee 50, as modified by Suh) and the lowermost surface of the first pad (Lee 90, as modified by Suh), and the first semiconductor substrate (Lee 11) is smaller than a distance between a top surface of the first dielectric layer (Lee 71) and the first semiconductor substrate (Lee 11).
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Regarding claim 6, which depends from claim 1: The combination discloses the first through via (50) comprises: a conductive layer (53) that has a pillar shape; and a via barrier layer (52) that surrounds a circumferential surface of the conductive layer (53), and wherein the first pad (90) is in contact with a top surface of the conductive layer (53) and a top surface of the via barrier layer (52). See Lee Figure 2C; Lee specification ¶ 61. See also Jin Figures 1-3.
Regarding claim 10, which depends from claim 1: The combination discloses a top surface of the first pad (340) and a top surface of the first protection layer (320) are flat. See Jin Figure 6B (Jin Figure 1, upside down); Jin specification ¶¶ 45, 55, 61.
Regarding claim 11, which depends from claim 1: The combination discloses the first dielectric layer (Jin 121) and the second dielectric layer (Jin 123) comprise silicon oxide (SiO), and wherein the etch stop layer (Jin 122) comprises silicon nitride (SiN). Jin specification ¶ 31.
Regarding claim 14: Jin Figures 5, 6A, 6B and 1-3 disclose a semiconductor package (1000), comprising: a substrate (200); semiconductor chips (300) on the substrate (200); and a molding layer (810) on the substrate (200), the molding layer (810) surrounding the semiconductor chips (300), wherein each of the semiconductor chips (300) comprises: a semiconductor substrate (310); first pads (371) on an active surface (319) of the semiconductor substrate (310); a dielectric pattern (373) that surrounds the first pads (371) and exposes one surface of the first pads (371); second pads (340) on an inactive surface (317) of the semiconductor substrate (310); a protection layer (320) that surrounds the second pads (340) and exposes one surface of the second pads (340); and through vias (330) that vertically penetrate the semiconductor substrate (310) and are connected to the second pads (340), wherein the protection layer (320) comprises a first dielectric layer (321, corresponding to first insulating layer (121) in Jin Figures 1-3, Jin specification ¶ 68), a silicon nitride layer (323, corresponding to second insulating layer (123) in Jin Figures 1-3, id.), and a second dielectric layer (325, corresponding to third insulating layer (125) in Jin Figures 1-3, id.) that are sequentially stacked, the first dielectric layer (321) and the second dielectric layer (325) being spaced apart from each other across the silicon nitride layer (323), and wherein one of the semiconductor chips (300) is directly bonded to another one of the semiconductor chips (300), and the first pads (371) of the one of the semiconductor chips (300) are in contact with the second pads (340) of the other one of the semiconductor chips (300). Jin specification ¶¶ 64-73, 24-49. Jin does not disclose an etch stop layer, wherein a distance from the etch stop layer to the semiconductor substrate is greater than a distance from lowermost surfaces of the second pads to the semiconductor substrate. Jin also does not disclose that an uppermost surface of one of the through vias contacts a lowermost surface of one of the second pads.
Lee Figures 1C and 2C disclose a semiconductor chip (10C) comprising a semiconductor substrate (11); a first pad (85) on an active surface (S1) of the semiconductor substrate (11); a dielectric pattern (61, 62, 63) that surrounds the first pad (85) and exposes one surface of the first pad (85); a second pad (90) on an inactive surface (S2) of the semiconductor substrate (11); a protection layer (71, 72, 73, 74: 75, 76) that surrounds the second pad (90) and exposes one surface of the second pad (90); and a through via (50) that vertically penetrates the semiconductor substrate (11) and is connected to the second pad (90), wherein the protection layer (71, 72, 73, 74: 75, 76) comprises a first dielectric layer (71), an etch stop layer (72) (made of silicon nitride, Lee specification ¶ 64), and a second dielectric layer (73) that are sequentially stacked, the first dielectric layer (71) and the second dielectric layer (73) being spaced apart from each other across the etch stop layer (72), wherein a distance from the etch stop layer (72) to the semiconductor substrate (11) is greater than a distance from a lowermost surface of the second pad (90) to the semiconductor substrate (11), wherein an upper surface of the through via (50) contacts a lower surface of the second pad (90). Lee specification ¶¶ 41-44, 60-65. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Jin to include the Lee design because the modification would have involved the substitution of an equivalent known for the same purpose.
As for the difference between the difference being upper surface vs. uppermost surface and lower surface vs. lowermost surface, applicants’ arguments are unclear as to the patentable significance of the uppermost surface over an upper surface, or the patentable significance of the lowermost surface over a lower surface. Because the uppermost surface is not patentably significant over an upper surface and because the lowermost surface is not patentably significant over a lower surface, claim 14 is rejected as a patentably insignificant shape variation over the prior art.
In the alternative, Suh Figures 1A and 2A disclose a through via (360), which vertically penetrates a semiconductor substrate (base (310)) and protrudes from the inactive surface of the semiconductor substrate (310); a protection layer (350, 440, 430) that covers the inactive surface of the semiconductor substrate (310) and buried the through via (360); a pad (420) that penetrates at least a portion of the protection layer (350, 440, 430) and is coupled to the through via (360); wherein an uppermost surface of the through via (360) contacts a lowermost surface of the pad (420). Suh specification ¶¶ 20-54. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Suh design because the modification would have involved the substitution of an equivalent known for the same purpose. This renders obvious claim 14.
Regarding claim 15, which depends from claim 14: The combination discloses the etch stop layer (Lee 72) is in contact with lateral surfaces of the second pads (Lee 90; Jin 340). See Lee Figure 2C.
Regarding claim 16, which depends from claim 14: The combination discloses the through vias (50) vertically penetrate at least a portion of the first dielectric layer (71), wherein the second pads (90) vertically penetrate the second dielectric layer (73) and the etch stop layer (73), and wherein a distance between a contact interface, between the uppermost surface of the one of the through vias (Lee 50, as modified by Suh) and the lowermost surface of the one of the second pads (Lee 90, as modified by Suh), and the semiconductor substrate (11) is smaller than a distance between a top surface of the first dielectric layer (71) and the semiconductor substrate (11).
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Regarding claim 17, which depends from claim 14: The combination discloses each of the through vias (50) comprises: a conductive layer (53) that has a pillar shape; and a via barrier layer (52) that surrounds a circumferential surface of the conductive layer (53), wherein the one of the second pads (90) is in contact with a top surface of the conductive layer (53) and a top surface of the via barrier layer (52). See Lee Figure 2C; Lee specification ¶ 61. See also Jin Figures 1-3.
Regarding claim 21, which depends from claim 14: The combination discloses top surfaces of the second pads (340) and a top surface of the protection layer (320) are flat. See Jin Figure 6B (Jin Figure 1, upside down); Jin specification ¶¶ 45, 55, 61.
Claims 9, 20, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Jin, and further in view of Lee and Naik, U.S. Pat. Pub. No. 2008/0102638, Figures 1, 3A.
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Regarding claim 9, which depends from claim 1: The combination does not disclose the first protection layer further comprises a polish stop layer that covers a top surface of the second dielectric layer that faces away from the first semiconductor substrate, wherein a top surface of the polish stop layer is coplanar with a top surface of the first pad.
Naik Figures 1 and 3A disclose a first protection layer that comprises a polish stop layer (122) that covers a top surface of the second dielectric layer (second dielectric layer is the upper dielectric layer in stack (150) that comprises two dielectric layers with an etch stop layer between them) that faces away from the first semiconductor substrate (100). Naik specification ¶¶ 7-9, 41, 50-52. One having ordinary skill in the art at a time before effective filing date would be motivated to modify the combination to use the Naik polish stop layer because the modification would protect the lower dielectric layers during a polishing step. Once combined, the combination discloses a top surface of the polish stop layer is coplanar with a top surface of the first pad because Jin is designed such that the first protection layer is coplanar with the first pad. See Jin Figure 6B. See also Jin specification ¶¶ 45, 55, 61.
Regarding claim 20, which depends from claim 14: The combination does not disclose the protection layer further comprises a polish stop layer that covers a top surface of the second dielectric layer that faces away from the semiconductor substrate, wherein a top surface of the polish stop layer is coplanar with top surfaces of the second pads.
Naik Figures 1 and 3A disclose a protection layer that comprises a polish stop layer (122) that covers a top surface of the second dielectric layer (second dielectric layer is the upper dielectric layer in stack (150) that comprises two dielectric layers with an etch stop layer between them) that faces away from the semiconductor substrate (100). Naik specification ¶¶ 7-9, 41, 50-52. One having ordinary skill in the art at a time before effective filing date would be motivated to modify the combination to use the Naik polish stop layer because the modification would protect the lower dielectric layers during a polishing step. Once combined, the combination discloses a top surface of the polish stop layer is coplanar with a top surface of one of the second pads because Jin is designed such that the protection layer is coplanar with the second pad. See Jin Figure 6B. See also Jin specification ¶¶ 45, 55, 61.
Regarding claim 24: Jin Figures 5-6B and 1-3 disclose a semiconductor package (1000), comprising: a substrate (200); semiconductor chips (300) stacked on the substrate (200); and a molding layer (810) on the substrate (200), the molding layer (810) surrounding the semiconductor chips (300), wherein each of the semiconductor chips (300) comprises: a semiconductor substrate (310); first pads on an active surface (319) of the semiconductor substrate (300); a dielectric pattern (373) that surrounds the first pads (371) and exposes one surface of the first pads (371); a protection layer (320) that is on an inactive surface (317) of the semiconductor substrate (310) and comprises a first dielectric layer (321, corresponding to first insulating layer (121) in Jin Figures 1-3, Jin specification ¶ 68), a silicon nitride insulating layer (323, corresponding to second insulating layer (123) in Jin Figures 1-3, id.), a second dielectric layer (325, corresponding to third insulating layer (125) in Jin Figures 1-3, id.); second pads (340) that are in the protection layer (320) and have one surface exposed by the protection layer (320); and through vias (330) that vertically penetrate the semiconductor substrate (310) and are connected to the second pads (340), wherein the silicon nitride layer (323) is in contact with the second pads (340), and wherein one of the semiconductor chips (310) is directly bonded to another one of the semiconductor chips (310), and the first pads (371) of the one of the semiconductor chips (300) are in contact with the second pads (340) of the other one of the semiconductor chips (300). Jin specification ¶¶ 64-73, 24-49. Jin does not disclose that the silicon nitride insulating layer is an etch stop layer. Jin does not disclose a polish stop layer on the third insulating layer. Lastly, Jin does not disclose that an uppermost surface of one of the through vias contacts a lowermost surface of one of the second pads.
Lee Figures 1C and 2C disclose a semiconductor chip (10C) comprising: a semiconductor substrate (11); a first pad (85) on an active surface (S1) of the semiconductor substrate (11); a dielectric pattern (61, 62, 63) that surrounds the first pad (85) and exposes one surface of the first pad (85); a protection layer (71, 72, 73, 74: 75, 76) that is on an inactive surface (S2) of the semiconductor substrate (11) and comprises a first dielectric layer (71), an etch stop layer (72) (made of silicon nitride, Lee specification ¶ 64), a second dielectric layer (73); a second pad (90) that is in the protection layer (71, 72, 73, 74: 75, 76) and has one surface exposed by the protection layer (71, 72, 73, 74: 75, 76); and through vias (50) that vertically penetrate the semiconductor substrate (11) and are connected to the second pad (90), wherein the etch stop layer (72) is in contact with the second pad (90), wherein an upper surface of the through via (50) contacts a lower surface of the second pad (90). Lee specification ¶¶ 41-44, 60-65. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Jin to include the Lee design because the modification would have involved the substitution of an equivalent known for the same purpose.
Naik Figures 1 and 3A disclose a first protection layer that comprises a polish stop layer (122) that covers a top surface of the second dielectric layer (second dielectric layer is the upper dielectric layer in stack (150) that comprises two dielectric layers with an etch stop layer between them) that faces away from the first semiconductor substrate (100). Naik specification ¶¶ 7-9, 41, 50-52. One having ordinary skill in the art at a time before effective filing date would be motivated to modify the combination to use the Naik polish stop layer because the modification would protect the lower dielectric layers during a polishing step. Once combined, the combination discloses a protection layer that is on an inactive surface of the semiconductor substrate and comprises a first dielectric layer, an etch stop layer, a second dielectric layer, and a polish stop layer that are sequentially stacked.
As for the difference between the difference being upper surface vs. uppermost surface and lower surface vs. lowermost surface, applicants’ arguments are unclear as to the patentable significance of the uppermost surface over an upper surface, or the patentable significance of the lowermost surface over a lower surface. Because the uppermost surface is not patentably significant over an upper surface and because the lowermost surface is not patentably significant over a lower surface, claim 24 is rejected as a patentably insignificant shape variation over the prior art.
In the alternative, Suh Figures 1A and 2A disclose a through via (360), which vertically penetrates a semiconductor substrate (base (310)) and protrudes from the inactive surface of the semiconductor substrate (310); a protection layer (350, 440, 430) that covers the inactive surface of the semiconductor substrate (310) and buried the through via (360); a pad (420) that penetrates at least a portion of the protection layer (350, 440, 430) and is coupled to the through via (360); wherein an uppermost surface of the through via (360) contacts a lowermost surface of the pad (420). Suh specification ¶¶ 20-54. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Suh design because the modification would have involved the substitution of an equivalent known for the same purpose. This renders obvious claim 24.
Allowable Subject Matter
Claims 7, 8, 18, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With regard to claim 7: The claim has been found allowable because the prior art of record does not disclose “the first protection layer further comprises a liner layer that covers a bottom surface of the first dielectric layer that faces towards the first semiconductor substrate, wherein the liner layer extends from between the first semiconductor substrate and the first dielectric layer to between a lateral surface of the through via and the first dielectric layer”, in combination with the remaining limitations of the claim.
With regard to claim 8: The claim has been found allowable due to its dependency from claim 7 above.
With regard to claim 18: The claim has been found allowable because the prior art of record does not disclose “wherein the protection layer further comprises a liner layer that covers a bottom surface of the first dielectric layer that faces towards the semiconductor substrate, wherein the liner layer extends from between the semiconductor substrate and the first dielectric layer to between a lateral surface of the one of the through vias and the first dielectric layer”, in combination with the remaining limitations of the claim.
With regard to claim 19: The claim has been found allowable due to its dependency from claim 18 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Victoria K. Hall/ Primary Examiner, Art Unit 2897
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