DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 05/11/2026 Claims 1-20 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 01/26/2024.
Oath/Declaration
The oath or declaration filed on 11/07/2023 is acceptable.
Election/Restrictions
Applicant’s election, without traverse, species III directed to an embodiment as depicted in FIGS. [6A-6C], claims 1-20, in the “Response to Election / Restriction Filed” filed on 05/11/2026 is acknowledged.
However, the feature of claim 2 “a channel layer; a ferroelectric layer having ferroelectricity and encircled by the channel layer in a horizontal plane; and a gate encircled by the ferroelectric layer in the horizontal plane” does not read elected species III, directed to an embodiment as depicted in FIGS. [6A-6C]. Therefore, claim 2 is withdrawn. Claims 3-4 are withdrawn based on the dependency of claim 2.
However, the feature of claim 9 “wherein one contact structure of an intermediate stack of transistors comprises: a conductive via vertically extending in the dielectric stack above the intermediate stack of transistors; a dielectric layer laterally surrounding the conductive via to isolate the contact structure from terminal lines of upper layers transistors above the intermediate stack of transistors; and an enlarged conductive end laterally in electrical contact with a corresponding terminal line of the intermediate stack of transistors” does not read elected species III, directed to an embodiment as depicted in FIGS. [6A-6C]. Therefore, claim 9 is withdrawn.
However, the feature of claim 11 “a plurality of layers of transistors stacked in a vertical direction, each layer of transistors comprising: a first array of transistors sharing a first common first-type terminal line; a second array of transistors sharing a second common first-type terminal line, wherein the first array of transistors and the second array of transistors share a common second-type terminal line; and a plurality of contact structures each coupled with the first common first-type terminal line, the second common first-type terminal line, or the common second-type terminal line, wherein each of the plurality of contact structures electrically coupled with an intermediate stack of transistors penetrates through a dielectric stack above the intermediate stack of transistors” does not read elected species III, directed to an embodiment as depicted in FIGS. [6A-6C]. Therefore, claim 11 is withdrawn. Claims 12-20 are withdrawn based on the dependency of claim 11. This office action considers claims 1-20 are thus pending for prosecution.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding Claim 6, The instant claims recite limitation “the first-type terminal is a drain terminal; the second-type terminal is a source terminal” is not clear because the first-type terminal line or first- type terminal contact, is a drain terminal is not defined. Similarly, the second-type terminal is a source terminal is not clear because the second-type terminal line or second type terminal contact, is a source terminal is not defined Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yokoyama (US 2022/0130830 A1; hereafter Yokoyama).
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Regarding claim 1. Yokoyama discloses a semiconductor structure (Fig 2), comprising:
a plurality of layers of transistors (Fig 2, stacked layers of transistors 230, Para [ 0029-0035]) stacked in a vertical direction (Fig 2, stacked layers of transistors 230, Para [ 0029-0035]), each layer of transistors comprising:
a first array of transistors (Fig 2, array transistors 230, Para [ 0029-0035]) sharing a first common first-type terminal line (Fig 2, 207-1, Para [ 0029-0035]);
a second array of transistors (Fig 2, another array transistors 230, Para [ 0029-0035]) sharing a second common first-type terminal line (Fig 2, 207-2, Para [ 0029-0035]), wherein the first array of transistors (Fig 2, array transistors 230) and the second array of transistors (Fig 2, another array transistors 230, Para [ 0029-0035]) share a common second-type terminal line (Fig 2, 203-1, Para [ 0029-0035]); and
a plurality of contact structures (Fig 2, 203-2, Para [ 0029-0035]) comprising:
a first common first-type terminal contact structure (Fig 2, left 203-2, Para [ 0029-0035]) coupled with the first common first-type terminal line (Fig 2, 207-1, Para [ 0029-0035]) in a first first-type terminal contact region (Fig 2, 207-1, Para [ 0029-0035]) located on a first lateral side of the first array of transistors (Fig 2, array transistors 230, Para [ 0029-0035]) away from the second array of transistors (Fig 2, another array transistors 230, Para [ 0029-0035]),
a second common first-type terminal contact structure (Fig 2, right 203-2, Para [ 0029-0035]) coupled with the second common first-type terminal line (Fig 2, 207-2, Para [ 0029-0035]) in a second first-type terminal contact region (Fig 2, 207-2, Para [ 0029-0035]) located on a second lateral side of the second array of transistors (Fig 2, another array transistors 230, Para [ 0029-0035]) away from the first array of transistors (array transistors 230, Para [ 0029-0035]), and
a common second-type terminal contact structure (Fig 2,body contact, 295, Para [ 0038]) coupled with the common second-type terminal line in a common second-type terminal contact region (right 203-2) located between (at least at a portion body contact, 295, Para [ 0038]) the first array of transistors (Fig 2, array transistors 230, Para [ 0029-0035]) and the second array of transistors (Fig 2, another array transistors 230, Para [ 0029-0035]).
Regarding claim 7. Yokoyama discloses the semiconductor structure of claim 1, Yokoyama further discloses wherein: each of the plurality of contact structures (Fig 2, [203-2], Para [ 0029-0035]) is located in a dielectric stack in the first first-type terminal contact region, or the second first-type terminal contact region (207-2, Para [ 0029-0035]), or the common second-type terminal contact region (body contact, 295, Para [ 0038]).
Regarding claim 8. Yokoyama discloses the semiconductor structure of claim 7, Yokoyama further discloses wherein:
the first common first-type terminal lines (207-1, Para [ 0029-0035]) of the plurality of layers of transistors (Fig 2, stacked layers of transistors 230, Para [ 0029-0035]) overlap in the vertical direction (207-1, Para [ 0029-0035]); the second common first-type terminal lines (207-2, Para [ 0029-0035]) of the plurality of layers of transistors (Fig 2, stacked layers of transistors 230, Para [ 0029-0035]) overlap in the vertical direction; and the common second-type terminal lines (203-1, Para [ 0029-0035]) of the plurality of layers of transistors (Fig 2, stacked layers of transistors 230, Para [ 0029-0035]) overlap in the vertical direction ( Fig 2).
Allowable Subject Matter
Claims 5 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 5. The semiconductor structure of claim 1, wherein: the first common first-type terminal line comprises a first U-shape portion located between adjacent rows of the first array of transistors and with a first opening opposite towards the second array of transistors; and the second common first-type terminal line comprises a second U-shape portion located between adjacent rows of the second array of transistors and with a second opening opposite towards the first array of transistors.
Regarding claim 10. The semiconductor structure of claim 8, further comprising: a first isolation wall between the first first-type terminal contact region and the first array of transistors to isolate the first common first-type terminal lines from the common second-type terminal lines; and a second isolation wall between the second first-type terminal contact region and the second array of transistors to isolate the second common first-type terminal lines from the common second- type terminal lines.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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