Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6 and 12-15 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Kim et. Al. (US 20220399368 A1 hereinafter Kim).
Regarding claim 1, Kim teaches in Figs. 2 and 8 with associated text A semiconductor structure, comprising: a stack structure ST including a plurality of dielectric layers 120 and conductive layers 130 alternatively stacked in a vertical direction (Fig. 2, [0044]); an array of channel structures (CH2 only are interpreted to be the array of channel structures) each vertically penetrating the stack structure, each channel structure including a functional layer (145A or 145B) and a channel layer (140A or 140B) (Figs. 2 and 8, [0048] and [0050]); and a plurality of isolation structures SS extending in parallel along a first lateral direction and vertically in an upper portion of the stack structure, each isolation structure being in contact with the channel layers of two adjacent rows of channel structures (Figs. 2 and 8, [0083] and [0050]), wherein each odd row of the array of channel structures is located on a first side of its adjacent one of the plurality of isolation structures, and each even row of the array of channel structures is located on a second side of its adjacent one of the plurality of isolation structures opposite the first side (see annotated Fig. below the claim wouldn’t necessarily require that no other channels are formed between each neighboring set of odd and even rows).
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Regarding claim 2, Kim teaches each isolation structure partially covers the two adjacent rows of channel structures in a lower portion of the stack structure (Fig. 2).
Regarding claim 3, Kim teaches the plurality of isolation structures comprises: a
plurality of first isolation structures each separating the conductive layers of the upper portion of the stack structure into sub-blocks (Figs. 2 and 8).
Regarding claim 4, Kim teaches the isolation structure is in contact with curved side surfaces of the channel layers of the two adjacent rows of channel structures in the upper portion of the stack structure (SS contacts curved inner sidewall of 140B where it protrudes from 149B’, Fig. 4A, [0067]).
Regarding claim 5, Kim teaches the isolation structure is in contact with filling structures (149A or 149B) of the two adjacent rows of channel structures in the upper portion of the stack structure (Fig. 8).
Regarding claim 6, Kim teaches a column of channel structures extending along a second lateral direction and located on a same side of the first isolation structures are connected to a common bit line 180 (Fig. 2, [0060]).
Regarding claim 12, Kim teaches a lateral cross section of the functional layer of the channel structure in the upper portion of the stack structure has a partial ring shape; and two lateral ends of the partial ring-shaped functional layer are in contact with the isolation structure (Fig. 8).
Regarding claim 13, Kim teaches a lateral cross section of the channel layer of the channel structure in the upper portion of the stack structure has a partial ring shape; and two lateral ends of the partial ring-shaped channel layer are in contact with the isolation structure (Fig. 8).
Regarding claim 14, Kim teaches the partial ring shape is larger than a one third ring (Fig. 8).
Regarding claim 15, Kim teaches a depth of the isolation structure is greater than a total thickness of one top pair of the dielectric layers and the conductive layers, and less than a total thickness of seven top pairs of the dielectric layers and the conductive layers (Fig. 2).
Claim(s) 21-25 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Sakaguchi (US 20220399368 A1).
Regarding claim 21, Sakaguchi teaches in Figs. 4, 6 and 23A with associated text a semiconductor structure, comprising: a stack structure 22 including a plurality of dielectric layers 14 and conductive layers (SGS-SGDL2) alternatively stacked in a vertical direction (Fig. 4, [0059]-[0060]); an array of channel structures (16-20) each vertically penetrating the stack structure, each channel structure including a functional layer (17-19) and a channel layer (16 16a in Fig. 23a) (Figs. 6 and 23a [0076]-[0077]); and a plurality of isolation structures 25 extending in parallel along a first lateral direction and vertically in an upper portion of the stack structure, each isolation structure being in contact with the channel layers of two adjacent rows of channel structures (Figs. 6 and 23a, [0048]), wherein the isolation structure is in contact with outer arc surfaces of the channel layers of the two adjacent rows of channel structures in the upper portion of the stack structure (Fig. 23A).
Regarding claim 22, Sakaguchi teaches each odd row of the array of channel structures is located on a first side of its adjacent one of the plurality of isolation structures, and each even row of the array of channel structures is located on a second side of its adjacent one of the plurality of isolation structures opposite the first side (here the array of channel structures is interpred to be the array that only includes channel 16c and 16a and not those including 16b see Fig. 6).
Regarding claim 23, Sakaguchi teaches each isolation structure partially covers the two adjacent rows of channel structures in a lower portion of the stack structure (Fig. 4).
Regarding claim 25, Sakaguchi teaches a lateral cross section of the functional layer of the channel structure (lateral cross-section at SGDL1 for example) in the upper portion (for example DWL0-SGDL2) of the stack structure has a partial ring shape (Fig. 23A); and a lateral cross section of the channel layer of the channel structure (lateral cross-section at SGDL1 for exampleDWL0 for example) in the upper portion of the stack structure has a complete ring shape (the channel is not cut at DWL0 so that it has a . complete ring shape)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 3 and further in view of Tobioka et. Al. (US 20240178130 A1 hereinafter Tobioka).
Regarding claim 7, Kim teaches the semiconductor structure of claim 3.
Kim does not specify the plurality of isolation structures further comprises: a plurality of second isolation structures each extending along the first lateral direction without separating the conductive layers of the upper portion of the stack structure, wherein the plurality of first and second isolation structures are alternatively arranged along a second lateral direction.
Tobioka discloses in Figs. 20A-20C with associated text a plurality of isolation structures (76 and 176) further comprises: a plurality of second isolation structures 176 each extending along the first lateral direction without separating the conductive layers of the upper portion of the stack structure (176 only extends part way along direction hd1 so that it does not separate the conductive layers [0290])), wherein the plurality of first and second isolation structures are alternatively arranged along a second lateral direction (Fig. 20B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a plurality of second isolation structures similar to those taught by Tibiola in the semiconductor structure of Kim because according to Tibiola by using such a structure electrical contacts can be provided to the electrically conductive layers 46 without forming any stepped surfaces or staircase regions [0354].
Regarding claim 8, Kim in view of Tibiola teaches the plurality of second isolation structures each including a plurality of second isolation segments discontinuously extended along the first lateral direction (Tibiola Fig. 20B, [0290]).
Regarding claim 9, Kim in view of Tibiola teaches a first subset of a column of channel structures extending along a second lateral direction and in contact with the first isolation structures are connected to a first common bit line 86; and a second subset of the column of channel structures in contact with the second isolation structures are connected to a second common bit line (other bit line 86) (by using the second isolation structures of Tibiola in the device with the channel structures of Kim the device would have a second subset of the column of channel structures in contact with the second isolation structures are connected to a second common bit line).
Regarding claim 10, Kim in view of Tibiola teaches the array of channel structures comprises dummy channel structures in contact with corners of the second isolation segments (Tibiola [0299]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 3 and further in view of Wang et. Al. (US 20200227411 A1 hereinafter Wang).
Regarding claim 11, Kim teaches the semiconductor structure of claim 1, a plurality of gate line structures MS extending in parallel along the first lateral direction (Fig. 8) and vertically penetrating the stack structure (Fig. 2).
Kim does not specify a first number of the isolation structures between adjacent gate line structures plus one is a half of a second number of the rows of channel structures between the adjacent gate line structure.
Wang discloses in Figs. 23B and 25 with associated text a first number of the isolation structures (inner structures 346) between adjacent gate line structures (outermost structures 346) (3) plus one (4) is a half of a second number of the rows of channel structures 350 (8) (Fig. 23B [0152]) between the adjacent gate line structure (Fig. 25, [0156]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use an arrangement similar to that taught by Wang in the semiconductor structure of Kim because according to Wang such a structure is suitable for providing a 3D NAND flash memory [0158] It would have been obvious to one of ordinary skill in the art, in view of the teachings of Kim and Wang, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known arrangements of isolation, cate line and channel structures with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S., 82 USPQ2d 1385 (2007).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Sakaguchi as applied to claim 21 and further in view of Wang et. Al. (US 20200227411 A1 hereinafter Wang).
Regarding claim 11, Sakaguchi teaches the semiconductor structure of claim 1.
Sakaguchi does not specify a first number of the isolation structures between adjacent gate line structures plus one is a half of a second number of the rows of channel structures between the adjacent gate line structure.
Wang discloses in Figs. 23B and 25 with associated text a plurality of gate line structures (outermost structures 346) extending in parallel along the first lateral direction (Fig. 23B) and vertically penetrating the stack structure (Fig. 23B) a first number of the isolation structures (inner structures 346) between adjacent gate line structures plus one (4) is a half of a second number of the rows of channel structures 350 (8) (Fig. 23B [0152]) between the adjacent gate line structure (Fig. 25, [0156]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use an arrangement similar to that taught by Wang in the semiconductor structure of Sakaguchi because according to Wang such a structure is suitable for providing a 3D NAND flash memory [0158] It would have been obvious to one of ordinary skill in the art, in view of the teachings of Kim and Wang, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known arrangements of isolation, cate line and channel structures with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S., 82 USPQ2d 1385 (2007).
Response to Arguments
Applicant's arguments filed 08/07/2026 have been fully considered but they are not persuasive. Regarding the arguments on pages 7-9 Kim teaches an array of channel structures (CH2 only are interpreted to be the array of channel structures) (Figs. 2 and 8, [0048] and [0050]), wherein each odd row of the array of channel structures is located on a first side of its adjacent one of the plurality of isolation structures, and each even row of the array of channel structures is located on a second side of its adjacent one of the plurality of isolation structures opposite the first side (see annotated Fig. above the claim wouldn’t necessarily require that no other channels are formed between each neighboring set of odd and even rows).
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm.
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/AARON J GRAY/Examiner, Art Unit 2897
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