DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on applications filed in France and the United Kingdom on November 8, 2022, December 9, 2022, and July , 25, 2023 respectively. It is noted, however, that applicant has not filed a certified copy of the applications FR 2211641, FR 2213093, and UK 2311415.0 as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites … “a silicon on insulator, SOI, wafer comprising a silicon substrate and an active layer separated by a buried oxide, BOX, layer, wherein said SOI substrate is a high resistance, HR, SOI substrate comprising a silicon handle wafer having a resistivity greater than 1 kΩ-cm.” The claim first describes the silicon on insulator, SOI, wafer comprising a silicon substrate and an active layer separated by a buries oxide. The claim then later recites that a SOI substrate comprises a silicon handle wafer having a specified resistivity. The additional recitation of the substrate comprising a silicon handle wafer renders the claim confusing since the SOI wafer has already been described as a silicon substrate. The recitation of the handle wafer is confusing and unnecessary.
Claim 1 also recites … “a thick metal layer.” The term is a relative term which renders the claim indefinite. The specification and dependent claims specify the actual dimensions of the thick metal layer, but the initial recitation in claim 1 is undefined. In the claim, one of ordinary skill could assign any dimension as “thick” for the metal layer. Furthermore, how is the metal layer thick, as compared to any other layer?
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 16, as far as understood, are rejected under 35 U.S.C. 103 as being unpatentable over Preisler et al. (US Pub. 2019/0109055 A1) in view of Mahnkopf (WO 2019/094952 A1).
In re claim 1, Preisler et al. shows (figs. 1 and 7) a switch LNA module comprising: a silicon on insulator, SOI, wafer (101) comprising a silicon substrate [0027] and an active layer (207) separated by a buried oxide, BOX layer (103), wherein said SOI substrate is a high resistance, HR SOI substrate [0025] comprising a silicon handle wafer having a resistivity greater than 1 kΩ-cm [0027]; a switch comprising a plurality of SOI transistors [0024]; a low noise amplifier, LNA, located in said SOI wafer and connected to an output of said switch ([0024]; fig. 7, switch 711 connects to LNA 1213), wherein said LNA comprises a bipolar transistor ([0024]; HBT is a heterojunction bipolar transistor) is thicker than other metal layers) is used for connecting the device regions and therefore enabling the use of an advantageous quality factor (Q) inductor. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the module of Preisler by forming the bipolar transistor in the bulk region of an SOI substrate as taught by Mahnkopf to improve planarity between regions having different types of devices. Mahnkopf further modifies Preisler by forming a thick metal layer, connecting the device regions to facilitate using an inductor having a good quality factor.
In re claim 2, Preisler et al. shows (figs. 1 and 7) wherein said bipolar transistor is a SiGe transistor [0024].
In re claim 3, Preisler et al. shows (figs. 1 and 7) that said silicon handle wafer has a resistivity greater than 3 kΩ-cm [0027].
In re claim 4, Mahnkopf shows (fig. 11) a plurality of passive components formed in or on said SOI wafer over said BOX layer, wherein said passive components are formed from and/or are connected by the thick metal layer and a second, at leastpartly overlapping the thick metal layer (1167; pg. 19, lines 1-26).
In re claim 5, Mahnkopf shows (fig. 11) each thick metal layer has a thickness in the range of 2 µm to 4 µm (1167; pg. 19, lines 1-26.
In re claim 16, Preisler et al. shows (fig. 7) an apparatus (700) for telecommunications comprising the switch LNA module according to claim 1, wherein the switch (711, 712) of the switch LNA module (1213, 714) is arranged in said apparatus to switch between a receiver mode (RX 735) and a transmitter mode (TX 734) of said apparatus.
Claims 6-15, as far as understood, are rejected under 35 U.S.C. 103 as being unpatentable over Preisler et al. (US Pub. 2019/0109055 A1) in view of Mahnkopf (WO 2019/094952 A1) as applied to claim 1 above, and further in view of Jain et al. (US Pub. 2019/0081597 A1).
In re claim 6, the combined references of Preisler and Mahnkopf disclose all of the elements of the claims except said LNA comprises a cascode structure comprising said bipolar transistor being a common emitter of said cascode structure. Jain et al. discloses [0003, 0036] that a conventional LNAs are constructed with a cascode structure, in various configurations. One convention configuration of the cascode structure comprises the bipolar transistor being a common emitter. Therfore it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the switch LNA device of Preisler and Mahnkopf by including a cascode structure because Jain teaches that the cascode is typically used in conjunction with the LNA to complete the module.
In re claim 7, Jain et al. discloses [0003, 0036] said LNA comprises a second bipolar transistor being a common base of said cascode structure.
In re claim 8, Jain et al. discloses [0003, 0019, 0036] a SOI transistor, wherein said cascode structure comprises said SOI transistor being a common gate of said cascode structure.
In re claim 9, Jain et al. discloses [0003, 0019, 0023, 0036] said SOI transistor is a complementary metal-oxide semiconductor (CMOS) transistor.
In re claim 10, the combined references of Preisler, Mahnkopf, and Jain disclose all of the elements of the claims including the LNA comprising a first stage amplifying circuit (Preisler, fig. 7; 1213) and a second stage amplifying circuit (Preisler, fig. 7; 714), wherein said first stage amplifying circuit comprises said bipolar transistor Preisler, [0024]) and wherein said second stage amplifying circuit comprises a cascode structure (Jain; [003]).
In re claim 11, Jain et al. discloses [0003, 0036] said cascode structure comprises a first SOI transistor being a common source of said cascode structure and a second SOI transistor being a common gate of said cascode structure.
In re claim 12, the combined references of Preisler, Mahnkopf, and Jain disclose all of the elements of the claims except said cascode structure comprises a second bipolar transistor in a bulk region of said SOI wafer, wherein said second bipolar transistor is a common emitter of said cascode structure, and a SOI transistor being a common gate of said cascode structure (Jain; [0003,0036]).The references do not specifically disclose the second bipolar transistor per say. However, It would have been obvious to one of ordinary skill in the art to use three, four, etc., bipolar transistors since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04 VI. (B).
In re claim 13, the combined references of Preisler, Mahnkopf, and Jain disclose all of the elements of the claims including said first stage amplifying circuit comprises a second cascode structure comprising said bipolar transistor being a common emitter of said second cascode structure (Jain; [0003,0036]) .
In re claim 14, the combined references of Preisler, Mahnkopf, and Jain disclose all of the elements of the claims including said second cascode structure comprises a second bipolar transistor located in a bulk region of said SOI wafer, wherein said second bipolar transistor is a common base of said cascode structure (Jain; [0003,0019, 0023, 0036]).
In re claim 15, the combined references of Preisler, Mahnkopf, and Jain disclose all of the elements of the claims including said second cascode structure comprises an SOI transistor being a common gate of said cascode structure (Jain; [0003,0036]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jain (US Pub. 2022/0122968 A1), Seshita (US Pub. 2020/0403580 A1), Yu (CN-113472383 A), Paul Abhijieet (WO-2020018847 A1), and Yu (CN-215601303-U also disclose various elements of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm.
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/MATTHEW E WARREN/Primary Examiner, Art Unit 2815