Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Lin et al. (US 2022/0406774).
Regarding claim 1, Lin et al. disclose a lower pattern layer (16) including a first semiconductor material[0016, GaAs or Germanium or silicon]; a first conductivity-type doped pattern layer (24/30) disposed on the lower pattern layer (16) and including a semiconductor material doped with a first conductivity-type impurity[0021, 0025]; a source/drain pattern (92) disposed on the first conductivity-type doped pattern layer (24/30) and including a semiconductor material doped with a second conductivity-type impurity different from the first conductivity-type impurity[0043]; a channel pattern (54) including semiconductor patterns connected between the source/drain patterns (92), stacked apart from each other, and including a second semiconductor material (SiGe, silicon carbon) different from the first semiconductor material (channels 54 come from 53 [0041]); and a gate pattern (102) disposed on the first conductivity-type doped pattern layer (24/30) and between the source/drain patterns (92), and surrounding the channel pattern (54/52).
Regarding claim 2, Lin et al. disclose germanium, silicon [0016].
Regarding claim 3, Lin et al. disclose silicon [0016].
Regarding claim 4, Lin et al. disclose silicon germanium [0041].
Regarding claim 5, Lin et al. disclose the first conductivity- type impurity is an n-type impurity (10N)[0038], and the second conductivity-type impurity is a p-type impurity (24)[0021].
Regarding claim 6, Lin et al. disclose the n-type impurity includes phosphorus (P) [0020] and wherein the p-type impurity includes boron (B)[0021].
Regarding claim 7, Lin et al. disclose the first conductivity- type impurity is a p-type impurity (10P)[0038], and the second conductivity-type impurity is an n-type impurity (30).
Regarding claim 8, Lin et al. disclose the n-type impurity includes phosphorus (P) [0038] and wherein the p-type impurity includes boron (B)[0053].
Regarding claim 9, Lin et al. disclose the first conductivity- type doped pattern layer (16)(doped portion of substrate 10) is an epitaxial layer (i.e. has the same crystal structure as the substate).
Regarding claim 10, Lin et al. disclose wherein the gate pattern has a main gate portion (102) disposed on the semiconductor patterns and sub-gate portions (54A, 54B)( 52A, 52B) disposed between the semiconductor patterns, and wherein the semiconductor device further includes an inner gate spacer (90) disposed between the sub-gate portions of the gate pattern and the source/drain pattern (fig. 27B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2022/0406774) in view of Wang et al. (US 2023/0164971).
Lin et al. disclose a lower pattern layer (16) including a first semiconductor material; a first conductivity-type doped pattern layer (24/30) disposed on the lower pattern layer and including a semiconductor material doped with a first conductivity-type impurity; a source/drain pattern (92) disposed on the first conductivity-type doped pattern layer and including a semiconductor material doped with a second conductivity-type impurity different from the first conductivity-type impurity[0068,0069]; a channel pattern (55, 54A-C) [0011, 0044, 0068, 0069] including semiconductor patterns connected between the source/drain patterns, stacked apart from each other, and including a second semiconductor material (SiGe, silicon carbon)[0041] different from the first semiconductor material (channels 54 come from 53 [0041]); a gate pattern (102) disposed on the first conductivity-type doped pattern layer and between the source/drain patterns, and surrounding the channel pattern (fig. 1).
Lin et al. fails to explicitly disclose a lower contact electrode disposed under the source/drain pattern and connected to the source/drain pattern by penetrating the lower pattern layer and the first conductivity-type doped pattern layer.
Wang et al. disclose a lower contact electrode (716) disposed under the source/drain pattern (714) and connected to the source/drain pattern (fig. 8).
The combination of Lin and Wang would result in the contact electrode (Wang 716) penetrating the lower pattern layer (16, Lin) and the first conductivity-type doped pattern layer (24/30, Lin).
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (ie forming a backside contact to the source and drain), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable at the time the invention was filed (would allow one to electrically contact the source/drain from the backside).
Regarding claim 12, Wang et al. disclose the source/drain pattern includes a first source/drain (right 714 in fig. 8 rotated clockwise 90 degrees) structure and a second source/drain (left 714 in fig. 8 rotated clockwise 90 degrees) structure spaced apart from each other, and wherein the semiconductor device further includes a first upper contact electrode (806) disposed on the first source/drain structure and connected to the first source/drain structure.
Regarding claim 13, Wang et al. disclose the lower contact electrode (716) is disposed under the second source/drain structure (left 714 in fig. 8 rotated clockwise 90 degrees) and connected to the second source/drain structure.
Regarding claim 14 , Lin et al. disclose the semiconductor device further includes a second upper contact electrode (114) disposed on the gate pattern and connected to the gate pattern (fig. 30B).
Regarding claim 15 , Lin et al and Wang et al. disclose the semiconductor device further includes a lower interconnection structure (M0, Wang, fig. 8) disposed under the lower pattern layer (Lin, 16).
Regarding claim 16 , Lin et al. disclose the semiconductor device further includes an upper interconnection structure (114) on a gate pattern (102) (fig. 32B).
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2022/0406774) in view of Wang et al. (US 2023/0164971).
Lin et al. disclose a first conductivity-type doped pattern layer (24/30) including a semiconductor material doped with a first conductivity-type impurity; a source/drain pattern (92) disposed on the first conductivity-type doped pattern layer and including a semiconductor material doped with a second conductivity-type impurity different from the first conductivity-type impurity[0068,0069]; a channel pattern (55, 54A-C) [0011, 0044, 0068, 0069] including semiconductor patterns connected between the source/drain patterns, stacked apart from each other, and including a second semiconductor material (SiGe, silicon carbon)[0041] different from the first semiconductor material (channels 54 come from 53 [0041]); a gate pattern (102) disposed on the first conductivity-type doped pattern layer and between the source/drain patterns, and surrounding the channel pattern (fig. 1).
Lin et al. fails to explicitly disclose a lower contact electrode disposed under the source/drain pattern and connected to the source/drain pattern by penetrating the lower pattern layer and the first conductivity-type doped pattern layer.
Wang et al. disclose a lower contact electrode (716) disposed under the source/drain pattern (714) and connected to the source/drain pattern (fig. 8).
The combination of Lin and Wang would result in the contact electrode (Wang 716) penetrating the lower pattern layer (16, Lin) and the first conductivity-type doped pattern layer (24/30, Lin).
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (ie forming a backside contact to the source and drain), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable at the time the invention was filed (would allow one to electrically contact the source/drain from the backside).
Regarding claim 19, Wang et al. disclose the source/drain pattern includes a first source/drain (right 714 in fig. 8 rotated clockwise 90 degrees) structure and a second source/drain (left 714 in fig. 8 rotated clockwise 90 degrees) structure spaced apart from each other, and wherein the semiconductor device further includes a first upper contact electrode (806) disposed on the first source/drain structure and connected to the first source/drain structure.
Allowable Subject Matter
Claims 17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY K SMITH whose telephone number is (571)272-1884. The examiner can normally be reached Monday-Friday, 10am-6pm.
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/BRADLEY SMITH/Primary Examiner, Art Unit 2817
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