Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-17 have been considered but are moot because the new ground of rejection below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The examiner is not clear if the Ge, Si and C compound in claim 1 is the invention or the potential Si99C1 (when Ge=0, i.e. a compound without Germanium) is the claimed compound.
Claim 3 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The examiner is not clear what the lower bound of “greater than about 0 at % … of the carbon” would encompass. The specification [0198] discloses “carbon (C) may be included in an amount about 0.1 at %”. The examiner is not clear if the lower bound would encompass 0.0001 or .000000001 at%. (The examiner submits the lower bound .000000001 at% C in Silicon would be considered silicon and will be treated as silicon with respect to the prior art.)
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 3 and 21 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 1 discloses the first semiconductor material includes silicon (Si), germanium (Ge), and carbon (C), whereas claim 3 could just be SiC (when Ge is equal to 0 at%) . Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-10 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Lin et al. (US 2022/0406774).
Regarding claim 1, Lin et al. disclose a lower pattern layer (16) including a first semiconductor material[0016, GaAs or Germanium or silicon]; a first conductivity-type doped pattern layer (24/30) disposed on the lower pattern layer (16) and including a semiconductor material doped with a first conductivity-type impurity[0021, 0025]; a source/drain pattern (92) disposed on the first conductivity-type doped pattern layer (24/30) and including a semiconductor material doped with a second conductivity-type impurity different from the first conductivity-type impurity[0043]; a channel pattern (54) including semiconductor patterns connected between the source/drain patterns (92), stacked apart from each other, and including a second semiconductor material (SiGe, silicon carbon) different from the first semiconductor material (channels 54 come from 53 [0041]); and a gate pattern (102) disposed on the first conductivity-type doped pattern layer (24/30) and between the source/drain patterns (92), and surrounding the channel pattern (54/52) wherein the first semiconductor material includes silicon (Si), germanium (Ge), and carbon (C) [0016, “silicon; germanium;… silicon carbide…silicon-germanium… or combinations thereof” ].
Regarding claim 3, Lin et al. disclose silicon [0016].
Regarding claim 4, Lin et al. disclose silicon germanium [0041].
Regarding claim 5, Lin et al. disclose the first conductivity- type impurity is an n-type impurity (10N)[0038], and the second conductivity-type impurity is a p-type impurity (24)[0021].
Regarding claim 6, Lin et al. disclose the n-type impurity includes phosphorus (P) [0020] and wherein the p-type impurity includes boron (B)[0021].
Regarding claim 7, Lin et al. disclose the first conductivity- type impurity is a p-type impurity (10P)[0038], and the second conductivity-type impurity is an n-type impurity (30).
Regarding claim 8, Lin et al. disclose the n-type impurity includes phosphorus (P) [0038] and wherein the p-type impurity includes boron (B)[0053].
Regarding claim 9, Lin et al. disclose the first conductivity- type doped pattern layer (16)(doped portion of substrate 10) is an epitaxial layer (i.e. has the same crystal structure as the substate).
Regarding claim 10, Lin et al. disclose wherein the gate pattern has a main gate portion (102) disposed on the semiconductor patterns and sub-gate portions (54A, 54B)( 52A, 52B) disposed between the semiconductor patterns, and wherein the semiconductor device further includes an inner gate spacer (90) disposed between the sub-gate portions of the gate pattern and the source/drain pattern (fig. 27B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-16 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2022/0406774) in view of Wang et al. (US 2023/0164971).
Lin et al. disclose a lower pattern layer (16) including a first semiconductor material; a first conductivity-type doped pattern layer (24/30) disposed on the lower pattern layer and including a semiconductor material doped with a first conductivity-type impurity; a source/drain pattern (92) disposed on the first conductivity-type doped pattern layer and including a semiconductor material doped with a second conductivity-type impurity different from the first conductivity-type impurity[0068,0069]; a channel pattern (55, 54A-C) [0011, 0044, 0068, 0069] including semiconductor patterns connected between the source/drain patterns, stacked apart from each other, and including a second semiconductor material (SiGe, silicon carbon)[0041] different from the first semiconductor material (channels 54 come from 53 [0041]); a gate pattern (102) disposed on the first conductivity-type doped pattern layer and between the source/drain patterns, and surrounding the channel pattern (fig. 1) wherein the first semiconductor material includes silicon (Si), germanium (Ge), and carbon (C) [0016, “silicon; germanium;… silicon carbide…silicon-germanium… or combinations thereof” ].
Lin et al. fails to explicitly disclose a lower contact electrode disposed under the source/drain pattern and connected to the source/drain pattern by penetrating the lower pattern layer and the first conductivity-type doped pattern layer.
Wang et al. disclose a lower contact electrode (716) disposed under the source/drain pattern (714) and connected to the source/drain pattern (fig. 8).
The combination of Lin and Wang would result in the contact electrode (Wang 716) penetrating the lower pattern layer (16, Lin) and the first conductivity-type doped pattern layer (24/30, Lin).
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (ie forming a backside contact to the source and drain), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable at the time the invention was filed (would allow one to electrically contact the source/drain from the backside).
Regarding claim 12, Wang et al. disclose the source/drain pattern includes a first source/drain (right 714 in fig. 8 rotated clockwise 90 degrees) structure and a second source/drain (left 714 in fig. 8 rotated clockwise 90 degrees) structure spaced apart from each other, and wherein the semiconductor device further includes a first upper contact electrode (806) disposed on the first source/drain structure and connected to the first source/drain structure.
Regarding claim 13, Wang et al. disclose the lower contact electrode (716) is disposed under the second source/drain structure (left 714 in fig. 8 rotated clockwise 90 degrees) and connected to the second source/drain structure.
Regarding claim 14 , Lin et al. disclose the semiconductor device further includes a second upper contact electrode (114) disposed on the gate pattern and connected to the gate pattern (fig. 30B).
Regarding claim 15 , Lin et al and Wang et al. disclose the semiconductor device further includes a lower interconnection structure (M0, Wang, fig. 8) disposed under the lower pattern layer (Lin, 16).
Regarding claim 16 , Lin et al. disclose the semiconductor device further includes an upper interconnection structure (114) on a gate pattern (102) (fig. 32B).
Regarding claim 21, Lin et al. disclose silicon [0016].
Allowable Subject Matter
Claims 18, 19, and 22 are allowed.
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY K SMITH whose telephone number is (571)272-1884. The examiner can normally be reached Monday-Friday, 10am-6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRADLEY SMITH/Primary Examiner, Art Unit 2817
Prosecution Insights