DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 6/23/2026 is acknowledged.
Applicant amended claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 11, 12, 15, 16, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su et al. (US 2021/0336019) (hereafter Su).
Regarding claim 1, Su discloses a semiconductor device comprising:
a first complementary metal oxide semiconductor (CMOS) cell 100a (Fig. 1, paragraph 0027; and see paragraph 0017, wherein “complementary metal-oxide semiconductor (CMOS) transistors”) including a first pair (transistors with left 104 of 100a and right 104 of 100a in Fig. 1) of complementary nanosheet field effect transistors (see paragraph 0017, wherein “the semiconductor transistor devices may have one or more channel regions, such as semiconductor fins, nanosheets, nanowires, nanodots, etc”) comprising a first shared gate structure (104 of 100a in Fig. 1, paragraph 0019);
a second CMOS cell 100b (Fig. 1, paragraph 0027) including a second pair (transistors with left 104 of 100b and right 104 of 100b in Fig. 1) of complementary nanosheet field effect transistors comprising a second shared gate structure (104 of 100b in Fig. 1, paragraph 0019);
a first dielectric material pillar (160, 130, and 132 in Fig. 5) having a first height (vertical length from bottom surface of 160 to top surface of 136 in Fig. 5) separating the first shared gate structure (104 of 100a in Fig. 5) of the first CMOS cell from the second shared gate structure (104 of 100b in Fig. 5) of the second CMOS cell;
a second dielectric material pillar (118, 127, and 126 in Fig. 2) having a second height (vertical length of 127 in Fig. 5) that is less than the first height (vertical length from bottom surface of 160 to top surface of 136 in Fig. 5), wherein the second dielectric material pillar (118, 127, and 126 in Fig. 2) is located between (see Figs. 1 and 2) the complementary nanosheet field effect transistors of both the first pair (transistors with left 104 of 100a and right 104 of 100a in Fig. 1) of complementary nanosheet field effect transistors and the second pair (transistors with left 104 of 100b and right 104 of 100b in Fig. 1) of complementary nanosheet field effect transistors;
and the second shared gate structure (104 of 100b in Fig. 5) directly contacts a sidewall and a topmost surface of the second dielectric material pillar (126 and 127 in Fig. 5), and further wherein a bottommost surface of both the first dielectric material pillar (160, 130, and 132 in Fig. 5) and the second dielectric material pillar (126 and 127 in Fig. 5) is located in a same horizontal plane;
a hard mask cap 134 (Fig. 1, paragraph 0036) located above each of the complementary nanosheet field effect transistors of both the first pair (transistors with left 104 of 100a and right 104 of 100a in Fig. 1) of complementary nanosheet field effect transistors and the second pair (transistors with left 104 of 100b and right 104 of 100b in Fig. 1) of complementary nanosheet field effect transistors, wherein the hard mask cap 134 (Fig. 1, paragraph 0025) has outermost edges that are substantially vertically aligned (see Fig. 2, wherein 134 and 102 is vertically aligned) to outermost edges of each semiconductor channel material nanosheet 102 (Fig. 1, paragraph 0019) of the complementary nanosheet field effect transistors of the first pair (transistors with left 104 of 100a and right 104 of 100a in Fig. 1) of complementary nanosheet field effect transistors and the second pair (transistors with left 104 of 100b and right 104 of 100b in Fig. 1) of complementary nanosheet field effect transistors in a direction (Z direction in Fig. 1) perpendicular to both the first shared gate structure (104 of 100a in Fig. 1) and the second shared gate structure (104 of 100b in Fig. 1), and the hard mask cap 134 (Fig. 1) extends horizontally (see Fig. 1, wherein 104 extends beyond of 102 in Y direction) beyond each semiconductor channel material nanosheet 102 (Fig. 1) of the complementary nanosheet field effect transistors of the first pair (transistors with left 104 of 100a and right 104 of 100a in Fig. 1) of complementary nanosheet field effect transistors and the second pair (transistors with left 104 of 100b and right 104 of 100b in Fig. 1) of complementary nanosheet field effect transistors in a direction (Y direction in Fig. 1) parallel to the both the first shared gate structure (104 of 100a in Fig. 1) and the second shared gate structure (104 of 100b in Fig. 1); and
a dielectric material cap 136 (Fig. 1, paragraph 0027) extending outward from each of the outermost edges of the hard mask cap 134 (Fig. 1) in the direction (Y direction in Fig. 1) parallel to the both the first shared gate structure (104 of 100a in Fig. 1) and the second shared gate structure (104 of 100b in Fig. 1).
Regarding claim 2, Su further discloses the semiconductor device of Claim 1, wherein the dielectric material cap 136 (Fig. 1) has a topmost surface that is substantially coplanar with a topmost surface of the hard mask cap 134 (Fig. 1) and a bottommost surface that is vertically offset, and located above, a bottommost surface of the hard mask cap 134 (Fig. 1).
Regarding claim 3, Su further discloses the semiconductor device of Claim 1, wherein the dielectric material cap 136 (Fig. 1) has a first sidewall contacting one of the outermost sidewalls of the hard mask cap 134 (Fig. 1) and a second sidewall contacting a sidewall of the first dielectric material pillar (160, 130 (element number is not shown in Fig. 1 but see Fig. 5), and 132 in Fig. 1) that separates the first CMOS cell 100a (Fig. 1) from the second CMOS cell 100b (Fig. 1).
Regarding claim 4, Su further discloses the semiconductor device of Claim 1, wherein each of the first shared gate structure (104 of 100a in Fig. 1), the second shared gate structure (104 of 100b in Fig. 1), the first dielectric material pillar (160, 130, and 132 in Fig. 5) and the second dielectric material pillar (126 and 127 in Fig. 5) is located directly on a surface of a backside interlayer dielectric (ILD) material 212 (Fig. 29B, paragraph 0021) of a backside ILD structure 212 (Fig. 29B).
Regarding claim 5, Su further discloses the semiconductor device of Claim 1, wherein each complementary nanosheet field effect transistor of the first pair (transistors with left 104 of 100a and right 104 of 100a in Fig. 1) of complementary nanosheet field effect transistors and the second pair (transistors with left 104 of 100b and right 104 of 100b in Fig. 1) of complementary nanosheet field effect transistors has a first type source/drain (S/D) region 106 (Fig. 29B) and a second type S/D region 108 (Fig. 29B).
Regarding claim 11, Su further discloses the semiconductor device of Claim 5, further comprising a frontside back-end-on-the-line (BEOL) structure 218 (Fig. 29B, paragraph 0021) electrically connected to the first type S/D region 106 (Fig. 29B) by a frontside source/drain contact structure 120 (Fig. 29B, paragraph 0021).
Regarding claim 12, Su further discloses the semiconductor device of Claim 11, further comprising a frontside gate contact structure 110 (Fig. 29B, paragraph 0053) electrically connecting each of the first shared gate structure (104 of 100a in Fig. 1) and the second shared gate structure (104 of 100b in Fig. 1) to the frontside BEOL structure 116 (Fig. 29B).
Regarding claim 15, Su further discloses the semiconductor device of Claim 5, further comprising a VSS power rail 122 (Fig. 2, paragraph 0021) electrically connected to the second type S/D region 108 (Fig. 2) by a backside frontside source/drain contact structure 120 (Fig. 2, paragraph 0021).
Regarding claim 16, Su further discloses the semiconductor device of Claim 15, further comprising a backside interconnect structure 216 (Fig. 2, paragraph 0021) located on a surface of the backside VSS power rail 122 (Fig. 2, paragraph 0021).
Regarding claim 18, Su further discloses the semiconductor device of Claim 5, wherein in the direction (Y direction in Fig. 1) parallel to the both the first shared gate structure (104 of 100a in Fig. 1) and the second shared gate structure (104 of 100b in Fig. 1) an outermost edge of each of the first inner spacers (128 contacting 106 in Fig. 2, paragraph 0025) are substantially vertically aligned to one of the outermost edges of the hard mask cap 134 (Fig. 2) and an outermost edge of each of the second inner spacers (128 contacting 108 in Fig. 2, paragraph 0025) are substantially vertically aligned to another of the outermost edges of the hard mask cap 134 (Fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Su as applied to claim 5 above, and further in view of Wu et al. (US 2023/0335620) (hereafter Wu).
Regarding claim 6, Su further discloses the semiconductor device of Claim 5, further comprising first inner spacers (128 contacting 106 in Fig. 2, paragraph 0025) located adjacent to the first type S/D region 106 (Fig. 2, paragraph 0025), and second inner spacers (128 contacting 108 in Fig. 2, paragraph 0025) located adjacent to the second type S/D region 108 (Fig. 2, paragraph 0025).
Su does not disclose the first inner spacers are composed of a first spacer dielectric material having a first dielectric constant and the second inner spacers are composed of a second spacer dielectric material having a second dielectric constant which differs from the first dielectric constant.
Wu discloses the first inner spacers (left 232 in Fig. 16, paragraph 0024) are composed of a first spacer dielectric material (see paragraph 0024, wherein “first dielectric constant between about 5 and about 8”) having a first dielectric constant and the second inner spacers are composed of a second spacer dielectric material (right 234 in Fig. 16, paragraph 0025, wherein “second dielectric constant between about 1.5 and about 4”) having a second dielectric constant which differs from the first dielectric constant.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Su to form the first inner spacers are composed of a first spacer dielectric material having a first dielectric constant and the second inner spacers are composed of a second spacer dielectric material having a second dielectric constant which differs from the first dielectric constant, as taught by Wu, since the dielectric constant (Wu, paragraph 0013) of the inner layer is smaller than that of the outer layer, the removal of the portion of the outer layer may reduce parasitic capacitance and improve device performance.
Regarding claim 7, Su in view Wu discloses the semiconductor device of Claim 6, however Su does not disclose the second dielectric constant is less than the first dielectric constant.
Wu discloses the second dielectric constant (paragraph 0025, wherein “second dielectric constant between about 1.5 and about 4”) is less than the first dielectric constant (see paragraph 0024, wherein “first dielectric constant between about 5 and about 8”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Su to form the second dielectric constant is less than the first dielectric constant, as taught by Wu, since the dielectric constant (Wu, paragraph 0013) of the inner layer is smaller than that of the outer layer, the removal of the portion of the outer layer may reduce parasitic capacitance and improve device performance.
Regarding claim 8, Su further discloses the semiconductor device of Claim 7, wherein the first type S/D region 106 (Fig. 1, paragraph 0019) is a drain region, and the second type S/D region 108 (Fig. 1, paragraph 0019) is a source region.
Regarding claim 9, Su further discloses the semiconductor device of Claim 7, wherein the dielectric material cap 136 (Fig. 1, paragraph 0027) is composed of the second spacer dielectric material (see paragraph 0043, wherein “dielectric material such as, for example, silicon oxynitride, silicon carbon nitride, silicon oxygen carbide, silicon oxygen carbon nitride, silicon nitride or some other suitable material”).
Regarding claim 10, Su further discloses the semiconductor device of Claim 7, wherein the dielectric material cap 136 (Fig. 1, paragraph 0027) is composed of the first spacer dielectric material (see paragraph 0043, wherein “dielectric material such as, for example, silicon oxynitride, silicon carbon nitride, silicon oxygen carbide, silicon oxygen carbon nitride, silicon nitride or some other suitable material”).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Su as applied to claim 16 above, and further in view of Yang et al. (US 2022/0058327) (hereafter Yang).
Regarding claim 17, Su discloses the semiconductor device of Claim 16, however Su does not disclose a backside VDD power rail spaced apart from the backside VSS power rail and located on the backside interconnect structure.
Yang discloses a backside VDD power rail (PM1 in Fig. 5B, paragraph 0171) spaced apart from the backside VSS power rail (PM1 in Fig. 5B, paragraph 0171) and located on the backside interconnect structure (CT_B in Fig. 5B, paragraph 0068).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Su to form a backside VDD power rail spaced apart from the backside VSS power rail and located on the backside interconnect structure, as taught by Yang, since each of the plurality of first and second power supply lines PM1 and PM2 (Yang, Fig. 2, paragraph 0050) may supply different voltages to the standard cells SC1, SC2, SC1′, and SC2′ (Yang, Fig. 2, paragraph 0050) disposed therebetween.
Allowable Subject Matter
1. Claims 13, 14, 19, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
2. Claim 13 would be allowable because a closest prior art, Su et al. (US 2021/0336019), discloses a frontside gate contact structure 110 (Fig. 29B, paragraph 0053) electrically connecting each of the first shared gate structure (104 of 100a in Fig. 1) and the second shared gate structure (104 of 100b in Fig. 1) to the frontside BEOL structure 116 (Fig. 29B); a second dielectric material pillar (118, 127, and 126 in Fig. 2) having a second height (vertical length of 127 in Fig. 5) that is less than the first height (vertical length from bottom surface of 160 to top surface of 136 in Fig. 5), wherein the second dielectric material pillar (118, 127, and 126 in Fig. 2) is located between (see Figs. 1 and 2) the complementary nanosheet field effect transistors of both the first pair (transistors with left 104 of 100a and right 104 of 100a in Fig. 1) of complementary nanosheet field effect transistors and the second pair (transistors with left 104 of 100b and right 104 of 100b in Fig. 1) of complementary nanosheet field effect transistors; and a dielectric material cap 136 (Fig. 1, paragraph 0027) extending outward from each of the outermost edges of the hard mask cap 134 (Fig. 1) in the direction (Y direction in Fig. 1) parallel to the both the first shared gate structure (104 of 100a in Fig. 1) and the second shared gate structure (104 of 100b in Fig. 1) but fails to disclose the frontside gate contact structure is located above the second dielectric material pillar and is in contact with at least a portion of the topmost surface of the dielectric material cap. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor device comprising: the frontside gate contact structure is located above the second dielectric material pillar and is in contact with at least a portion of the topmost surface of the dielectric material cap in combination with other elements of the base claims 12, 11, 5, and 1. The other claims each depend from one of these claims, and each would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims for the same reasons as the claim from which it depends. Claim 14 depends on claim 13.
In addition, claim 19 would be allowable because a closest prior art, Su et al. (US 2021/0336019), discloses a first dielectric material pillar (160, 130, and 132 in Fig. 5) having a first height (vertical length from bottom surface of 160 to top surface of 136 in Fig. 5) separating the first shared gate structure (104 of 100a in Fig. 5) of the first CMOS cell from the second shared gate structure (104 of 100b in Fig. 5) of the second CMOS cell; and a dielectric material cap 136 (Fig. 1, paragraph 0027) extending outward from each of the outermost edges of the hard mask cap 134 (Fig. 1) in the direction (Y direction in Fig. 1) parallel to the both the first shared gate structure (104 of 100a in Fig. 1) and the second shared gate structure (104 of 100b in Fig. 1) but fails to disclose the first dielectric material pillar has a topmost surface that is substantially coplanar with a topmost surface of the dielectric material cap and a topmost surface of the hard mask cap. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor device comprising: the first dielectric material pillar has a topmost surface that is substantially coplanar with a topmost surface of the dielectric material cap and a topmost surface of the hard mask cap in combination with other elements of the base claim 1. The other claims each depend from one of these claims, and each would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims for the same reasons as the claim from which it depends. Claim 20 depends on claim 19.
Response to Arguments
1. Applicant's arguments filed 6/23/2026 have been fully considered.
2. The applicant argues (REMARKS, third paragraph in page 10) that “Applicant respectfully submits that the purported second shared gate structure 104 of Su does not directly contact a sidewall and a topmost surface of the purported second dielectric material pillar 220, nor is a bottommost surface of both the purported first dielectric material pillar 132 and the purported second dielectric material pillar 200 located in a same horizontal plane.” However,
Su et al. (US 2021/0336019) disclose the second shared gate structure (104 of 100b in Fig. 5) directly contacts a sidewall and a topmost surface of the second dielectric material pillar (126 and 127 in Fig. 5), and further wherein a bottommost surface of both the first dielectric material pillar (160, 130, and 132 in Fig. 5) and the second dielectric material pillar (126 and 127 in Fig. 5) is located in a same horizontal plane.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAMONT B KOO whose telephone number is (571)272-0984. The examiner can normally be reached 7:00 AM - 3:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Prosecution Insights