DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Invention I , Species IA ( Fig. 1 and 4, Claims 1- 7, 9, 10, 19 and 20) in the reply filed on 03/03/2026 is acknowledged. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim s 1 -7, 9, 10, 19 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites “ wherein at least one side surface of the gate stack in the vertical direction is a (100) crystal plane or a (110) crystal plane; and/or wherein the body region adopts any one of following two structures: the body region comprises a second filling layer, wherein the second filling layer is a first insulation layer or a stress layer and the stress layer is used to apply a stress to the vertical channel; or the body region comprises a second gate conductor layer and a third filling layer, wherein the third filling layer is used to isolate the second gate conductor layer from the source/drain region and at least one of the first filling layer and the third filling layer is a storage functional layer. “ There Examiner notes that “and /or” between wherein clauses makes it impossible to determine what metes and bounds of the claim are. Further, “or” within the second wherein clause compound the ambiguity. For the purposes of examination, the Examiner will treat Claim language after “and/or” as optional. Claim 1 recites the limitation "the body region " in line 7 . There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the Examiner will treat “ the body region FILLIN "Enter appropriate information" \* MERGEFORMAT " as —the at least one body region—. Claims 2-7, 9, 10, 19 and 20 are rejected as being dependent on Claim 1. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 -3, 19 and 20 is/are rejected under 35 U.S.C. 102(A1) as being anticipated by Rabkin et al. (US 9,685,484 B1) . Regarding Claim 1, Rabkin (Fig. 1, 6) discloses a NOR-type memory device, comprising: a plurality of gate stacks extending vertically on a substrate (“substrate”) , wherein the gate stack (14, 12/ 618,610) comprises a first gate conductor layer ( 14 ) and a first filling layer ( 12 ) ; at least one device layer ( 10, 8/ 604, 614, 606) surrounding a periphery of the gate stack (14, 12/ 618,610) and extending along a sidewall of the gate stack, wherein the device layer comprises at least two source/drain regions (“ The active area may include a portion of a source or drain region of a transistor ”) and at least one body region (regions between source or drain) provided in a vertical direction, the source/drain regions and the body region are provided alternatively (Fig. 1, 6) , and a memory cell (MC1-MC6) is defined at an intersection of the gate stack and the body region (Fig. 1, 6) ; and a vertical channel (10) provided on a side of the device layer close to the gate stack, wherein the vertical channel is a single crystal channel and in contact with the first filling layer; wherein at least one side surface of the gate stack in the vertical direction is a (100) crystal plane or a (110) crystal plane; and/or wherein the body region adopts any one of following two structures: the body region comprises a second filling layer, wherein the second filling layer is a first insulation layer or a stress layer and the stress layer is used to apply a stress to the vertical channel; or the body region comprises a second gate conductor layer and a third filling layer, wherein the third filling layer is used to isolate the second gate conductor layer from the source/drain region and at least one of the first filling layer and the third filling layer is a storage functional layer. Regarding Claim 2 , Rabkin discloses the NOR-type memory device according to claim 1, wherein a material of the first insulation layer comprises silicon oxide (“ gate dielectric 12 is formed by oxidizing outer portions of the crystalline silicon ”) , aluminum oxide, hafnium oxide, zirconia, and silicon oxynitride; wherein a material of the stress layer comprises silicon carbide, silicon germanium, and silicon nitride. Regarding Claim 3 , Rabkin discloses the NOR-type memory device according to claim 1, wherein the storage functional layer comprises a tunneling layer, a charge capture layer, and a barrier layer stacked sequentially; wherein the barrier layer is provided on a side close to the first gate conductor layer and/or the second gate conductor layer; wherein a material of the barrier layer comprises at least one of aluminum oxide and silicon oxide, a material of the charge capture layer comprises hafnium oxide, zirconia, and silicon nitride, and a material of the tunneling layer comprises aluminum oxide, silicon oxide, and silicon oxynitride. The Examiner notes that Claim language after “and/or” as optional. See rejection of Claim 1 . Regarding Claim 19 , Rabkin discloses the electronic device, comprising the NOR-type memory device according to claim 1. (Fig. 2) Regarding Claim 20 , Rabkin discloses the electronic device according to claim 19, wherein the electronic device comprises: a smart phone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device, and a mobile power supply. (Fig. 2) Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 4 -6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rabkin et al. (US 9,685,484 B1) in view of Harari (US 2019/0244971 A1). Regarding Claim 4 , Rabkin discloses the NOR-type memory device according to claim 1, further comprising: Rabkin does not explicitly disclose a first leading electrode and a second leading electrode; wherein the first leading electrode is electrically connected to the source/drain region, and the second leading electrode is electrically connected to the second gate conductor layer. Harari (Fig. 3) discloses a first leading electrode (355) and a second leading electrode (354) ; wherein the first leading electrode is electrically connected to the source/drain region (Fig. 33) , and the second leading electrode is electrically connected to the second gate conductor layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the NOR-type memory device in Rabkin in view of Harari such that a first leading electrode a nd a second leading electrode; wherein the first leading electrode is electrically connected to the source/drain region, and the second leading electrode is electrically connected to the second gate conductor layer in order to the vertical NOR memory array circuit architecture with shared local source line [0035-0037] Regarding Claim 5 , Rabkin in view of Harari discloses the NOR-type memory device according to claim 4, further comprising: a plurality of surface electrodes (313 GSL, 354 GBL) ; wherein the plurality of surface electrodes are electrically connected to the first leading electrode (355) and the second leading electrode (354) , respectively. Regarding Claim 6 , Rabkin discloses the NOR-type memory device according to claim 1, wherein a material of the vertical channel comprises monocrystalline silicon, silicon carbide, a III-V group compound (“ crystalline silicon 10 bit line (or channel) is a single crystal of silicon ) , and graphene . when the vertical channel is an N-type metal oxide semiconductor, a doping element comprises boron. Rabkin does not explicitly disclose the material of the vertical channel is an in-situ doped material; wherein when the vertical channel is a P-type metal oxide semiconductor, a doping element comprises sulfur and arsenic; wherein when the vertical channel is an N-type metal oxide semiconductor, a doping element comprises boron. Harari (Fig. 5) discloses a material of a vertical channel is an in-situ doped material ( P.sup .− channel materia ) [0048] It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the NOR-type memory device in Rabkin in view of Harari such that the material of the vertical channel is an in-situ doped material in order to the vertical NOR memory array circuit architecture [0035-0037] Examiner notes that claim language ” when the vertical channel is a P-type metal oxide semiconductor , a doping element comprises sulfur and arsenic; wherein when the vertical channel is an N-type metal oxide semiconductor , a doping element comprises boron.” is optional. “ Claim scope is not limited by claim language that suggests or makes optional but does not require steps to be performed, or by claim language that does not limit a claim to a particular structure.“ (See MPEP 21 11.04 ) . Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rabkin et al. (US 9,685,484 B1) . Regarding Claim 7 , Rabkin discloses the NOR-type memory device according to claim 1 . a thickness of the vertical channel (10) Rabkin does not explicitly disclose a thickness of the vertical channel is between 1 nm and 100 nm. However, t here is no evidence showing the criticality of the claimed thickness. The semiconductor art well recognizes that a thickness of the vertical channel controls parameters critical for device performance, including reduce leakage , improve speed , threshold voltage reduction and allowing devices to continue shrinking in accordance with Moore's Law. A thickness of the vertical channel is therefore an art recognized result affecting parameter Therefore, i t would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the NOR-type memory device in Rabkin such that a thickness of the vertical channel is between 1 nm and 100 nm. The specific claimed relative thicknesses of the germanium material, absent any criticality, are only considered to be the "optimum" thicknesses that a person having ordinary skill in the art would have been able to determine using routine experimentation based, among other things, on the desired r educe leakage and improve speed , minimize short-channel effects etc. (see Boesch , 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT DMITRIY YEMELYANOV whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7920 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 9a.m.-6p.m . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Matthew Landau can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-1731 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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