DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Pursuant to the election without traverse on April 16, 2026, claims 3, 5, 15, and 16 are withdrawn from consideration.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner proposes MEMORY DEVICE WITH MULTI-PART CONTACT CONNECTED TO THE CAPACITOR
Paragraph [0051] has the “second ohmic contact pattern 37,5”, which appears to be an error.
Drawings
The drawings are objected to because the lines A-A’, B-B’, C-C’, and E-E’, referenced in paragraph 19 of the specification, are not clearly visible.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, 6, 7, 9-14, and 17-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Kim, US 2022/0085026 A1.
Claim 1: Kim discloses
a substrate (100);
an active pattern array including active patterns (105) on the substrate;
a first contact structure (215, 245) on a central portion of each of the active patterns;
at least one bit line structure (325) on the first contact structure;
a second contact structure (425) on an end portion of each of the active patterns;
at least one third contact structure (475) on the second contact structure;
and a capacitor (550) electrically connected to the at least one third contact structure,
wherein:
the active pattern array includes active pattern rows spaced apart from each other in a second direction (vertical, FIG. 1) substantially parallel to an upper surface of the substrate,
each of the active pattern rows includes the active patterns spaced apart from each other in a first direction (horizontal, FIG. 1) substantially parallel to the upper surface of the substrate and substantially orthogonal to the second direction,
each of the active patterns extends in a third direction having an acute angle with the first direction and the second direction,
the active patterns in each of the active pattern rows are aligned in the first direction,
and the second contact structure has a rectangular shape in a plan view (FIG. 16).
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Claim 2: the second contact structure includes polysilicon doped with impurities ([0041]).
Claim 4: the at least one third contact structure (475) has a lower portion and an upper portion, the lower portion having a first width, and the upper portion having a second width greater than the first width (FIG. 2).
Claim 6: Kim discloses a spacer (385, 397, 405, 445) surrounding a sidewall of the second contact structure and including silicon oxide ([0035]).
Claim 7: Kim discloses an isolation pattern (110) covering sidewalls of the active patterns, wherein the at least one bit line structure extends in the second direction on the active patterns and the isolation pattern (FIG. 1).
Claim 9: Kim discloses gate structures (160), each of the gate structures extending in the first direction (FIG. 1) through upper portions of the active patterns and the isolation pattern, wherein the first contact structure is on an upper surface of a portion of each of the active patterns between the gate structures (FIG. 2).
Claim 10: the at least one bit line structure includes a plurality of bit line structures spaced apart from each other in the first direction (FIG. 1), the at least one third contact structure includes a plurality of third contact structures, and the semiconductor device further includes a fence pattern (500) on the substrate, the fence pattern extending in the first direction and separating the third contact structures adjacent to each other in the second direction (FIG. 2).
Claim 11: Kim discloses
a substrate (11);
an active pattern (105) on the substrate;
a first contact structure (215, 245) on a central portion of the active pattern;
a bit line structure (325) on the first contact structure;
a second contact structure (425) on an end portion of the active pattern;
a third contact structure (475) on the second contact structure;
a spacer (385, 397, 405, 445) surrounding the third contact structure and having a lower portion and an upper portion, a thickness of the upper portion being smaller than a thickness of the lower portion (FIG. 18);
a landing pad (top of 475) on the third contact structure;
and a capacitor (550) on the landing pad.
Claim 12: the second contact structure includes polysilicon doped with impurities ([0041]), and the third contact structure includes a metal ([0046]).
Claim 13: the third contact structure has a lower portion and an upper portion, the lower portion having a first width, and the upper portion having a second width greater than the first width (FIG. 2).
Claim 14: the spacer includes an oxide ([0035]).
Claim 17: Kim discloses
a substrate (11);
an active pattern array including active patterns (105) on the substrate;
an isolation pattern (110) on the substrate, the isolation pattern covering sidewalls of the active patterns;
gate structures (160) spaced apart from each other in a second direction (vertical, FIG. 1) substantially parallel to an upper surface of the substrate (FIG. 1), each of the gate structures extending through upper portions of the active patterns and the isolation pattern in a first direction (horizontal, FIG. 1) substantially parallel to the upper surface of the substrate and substantially orthogonal to the second direction (FIGS. 1 and 2);
bit line structures (325) on central portions of the active patterns and the isolation pattern (FIG. 2), each of the bit line structures extending in the second direction, and the bit line structures being spaced apart from each other in the first direction (FIG. 1);
a first contact structure (215, 245) on an end portion of each of the active patterns;
a second contact structure (425) on the first contact structure;
and a capacitor (550) electrically connected to the second contact structure,
wherein:
the active pattern array includes active pattern rows spaced apart from each other in the second direction,
each of the active pattern rows includes the active patterns spaced apart from each other in the first direction,
each of the active patterns extends in a third direction having an acute angle with the first direction and the second direction,
the active patterns in each of the active pattern rows are aligned in the first direction,
and the second contact structure has a rectangular shape in a plan view (FIG. 16).
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Claim 18: Kim discloses a third contact structure (475) on the second contact structure, wherein the third contact structure has a lower portion and an upper portion, the lower portion having a first width, and the upper portion having a second width greater than the first width (FIG. 2).
Claim 19: Kim discloses a spacer (385, 397, 405, 445) surrounding a sidewall of the second contact structure and including silicon oxide ([0035]).
Claim 20: the spacer includes a lower portion and an upper portion, a thickness of the upper portion is smaller than a thickness of a lower portion (FIG. 2).
Claims 1, 2, 4, 6, 11, and 13 are rejected under 102(a)(2) as being anticipated by Hwang, US 2015/0255466 A1.
Claim 1: Hwang discloses
a substrate (101);
an active pattern array including active patterns (103) on the substrate;
a first contact structure (108, FIG. 2B) on a central portion of each of the active patterns;
at least one bit line structure (109) on the first contact structure;
a second contact structure (120, 32, FIG. 2A) on an end portion of each of the active patterns;
at least one third contact (121) structure on the second contact structure;
and a capacitor (123, [0031]) electrically connected to the at least one third contact structure,
wherein:
the active pattern array includes active pattern rows spaced apart from each other in a second direction (horizontal, FIG. 1A) substantially parallel to an upper surface of the substrate,
each of the active pattern rows includes the active patterns spaced apart from each other in a first direction (vertical, FIG. 1A) substantially parallel to the upper surface of the substrate and substantially orthogonal to the second direction,
each of the active patterns extends in a third direction (B-B’, FIG. 1A) having an acute angle with the first direction and the second direction,
the active patterns in each of the active pattern rows are aligned in the first direction (FIG. 1A),
and the second contact structure has a rectangular shape in a plan view (FIG. 1A).
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Claim 2: the second contact structure includes polysilicon doped with impurities. “Each of the second conductive plugs 32 may include a polysilicon layer. The polysilicon layer may be doped with an impurity through a doping process, such as an implantation process.” [0068].
Claim 4: the at least one third contact structure has a lower portion and an upper portion, the lower portion having a first width, and the upper portion having a second width greater than the first width.
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Claim 6: Hwang discloses a spacer (60) surrounding a sidewall of the second contact structure and including silicon oxide ([0051]).
Claim 11: Hwang discloses:
a substrate (101);
an active pattern (103) on the substrate;
a first contact structure (108) on a central portion of the active pattern;
a bit line structure (109) on the first contact structure;
a second contact structure (120) on an end portion of the active pattern;
a third contact structure (121) on the second contact structure;
a spacer (SP2) surrounding the third contact structure and having a lower portion and an upper portion, a thickness of the upper portion being smaller than a thickness of the lower portion (FIG. 2A);
a landing pad (top of 121) on the third contact structure;
and a capacitor (123) on the landing pad.
Claim 13: the third contact structure has a lower portion and an upper portion, the lower portion having a first width, and the upper portion having a second width greater than the first width (FIG. 2A).
Claims 11, 13, and 14 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Choi, US 2022/0181329 A1.
Claim 11: Choi discloses
a substrate (21);
an active pattern (CA) on the substrate;
a first contact structure (DC) on a central portion of the active pattern;
a bit line structure (BL) on the first contact structure;
a second contact structure (BC) on an end portion of the active pattern;
a third contact structure (71) on the second contact structure;
a spacer (61) surrounding the third contact structure and having a lower portion and an upper portion, a thickness of the upper (tapered) portion being smaller than a thickness of the lower portion (FIG. 1);
a landing pad (protruding portion of 71) on the third contact structure;
and a capacitor (95) on the landing pad.
Claim 13: the third contact structure has a lower portion and an upper portion, the lower portion having a first width, and the upper portion having a second width greater than the first width (FIG. 1).
Claim 14: the spacer includes an oxide ([0052]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Choi, US 2022/0181329 A1, in view of Kim.
Claim 1: Choi discloses
a substrate (21);
an active pattern array (CA) including active patterns on the substrate;
a first contact structure (DC) on a central portion of each of the active patterns;
at least one bit line structure (BL) on the first contact structure;
a second contact structure (BC) on an end portion of each of the active patterns;
at least one third contact structure (71) on the second contact structure;
and a capacitor (95) electrically connected to the at least one third contact structure,
wherein: the active pattern array includes active pattern rows spaced apart from each other in a second direction (horizontal, FIG. 2) substantially parallel to an upper surface of the substrate, each of the active pattern rows includes the active patterns spaced apart from each other in a first direction (vertical, FIG. 2) substantially parallel to the upper surface of the substrate and substantially orthogonal to the second direction, each of the active patterns extends in a third direction having an acute angle with the first direction and the second direction, the active patterns in each of the active pattern rows are aligned in the first direction (FIG. 2).
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Claim 1 also recites that the second contact structure has a rectangular shape in a plan view. Choi does not disclose this, but it was well-known in the art. See Kim, second contact structure 425, FIG. 16. Changes in shape are not typically a source of patentable distinction absent unexpected results. MPEP 2144.04.
Claim 4: the at least one third contact structure has a lower portion and an upper portion, the lower portion having a first width, and the upper portion having a second width greater than the first width (FIG. 1).
Claim 6: Choi discloses a spacer (60) surrounding a sidewall of the second contact structure and including silicon oxide ([0051]).
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The examiner did not find the claimed series of three buffer layers in the location and having the materials claimed, in light of the overall claimed device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Wang, US 20190019795 A1, which discloses rows of active regions (FIG. 1)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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