Detailed Action Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Election Applicant's election with traverse of Invention I in the reply filed on 24 February, 2 is acknowledged. The traversal is on the ground(s) that the subject matter of these inventions is sufficiently related that a search for the subject matter of any one of these inventions would encompass a search for the subject matter of the remaining invention, and moreover that prior art applicable to one invention would likely be applicable to the other invention. This is not found persuasive because the elected invention could be made with a process separate from that described in the instant application FILLIN "Enter claim indentification information" \* MERGEFORMAT , as described in the requirement for election/restriction. The requirement is still deemed proper and is therefore made FINAL. Claims 19-30 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 24 February, 2026. Claim Rejections 35 U.S.C § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim s 1 -2, 4 -8 and 10 -11, 14- 15 and 17 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Koike (US Pub 20110198748), hereinafter referred to as Koike. Regarding claim 1, Koike teaches a semiconductor package structure (Koike, 10, Fig 1, para. 19), comprising: a semiconductor substrate (Koike, 11, Fig. 1, para. 19); a conductive pad on the semiconductor substrate (Koike 15, Fig. 1, para. 20); a passivation layer on the semiconductor substrate and the conductive pad (Koike, 16, Fig. 1, para. 20), wherein the passivation layer exposes a portion of a top surface of the conductive pad (see Fig. 1 below); a conductive adhesive layer on the conductive pad (Koike, 20, Fig. 1, paras. 21, 26); a dielectric layer on the passivation layer and the conductive adhesive layer (Koike 21, Fig. 1, para. 21), wherein the dielectric layer exposes a portion of a top surface of the conductive adhesive layer (Koike, see Fig. 1 below); a redistribution layer (RDL) structure (Koike, 22, 30, 31, Fig. 1, para. 21 ) on the dielectric layer and electrically connected to the conductive pad through the conductive adhesive layer (Koike, see Fig. 1 below); and a bump structure over the redistribution layer (RDL) structure (Koike, 40, 41, 42, Fig. 1, para. 21 ) . Regarding claim 2, Koike teaches the semiconductor package structure as claimed in claim 1, wherein the exposed top surface of the conductive adhesive layer (Koike, 20, Fig. 1) is in direct contact with the redistribution layer (RDL) structure (Koike, 22, See Fig. 1 above , 22 is the bottom portion of the RDL structure ) . Regarding claim 4, Koike teaches the semiconductor package structure as claimed in claim 1, wherein the passivation layer (Koike, 16, Fig. 1) has a first opening that exposes the portion of the top surface of the conductive pad (Koike, 16, Fig. 1) , Regarding claim 5, Koike teaches the semiconductor package structure as claimed in claim 4, wherein the dielectric layer (Koike, 21, Fig. 1) has a second opening that exposes the portion of the top surface of the conductive adhesive layer (Koike, 20, Fig. 1), and the redistribution layer (RDL) structure comprises a pillar portion (Koike, 22, Fig. 1) in the second opening. Regarding claim 6, Koike teaches the semiconductor package structure as claimed in claim 5, wherein the first opening is greater than the second opening (Koike, See Fig. 1 above). Regarding claim 7, Koike teaches the semiconductor package structure as claimed in claim 5, wherein a bottom surface of the pillar portion of the redistribution layer (RDL) structure is in direct contact with the top surface of the conductive adhesive layer (Koike, Fig. 1, 22 is in direct contact with 20). Regarding claim 8, Koike teaches the semiconductor package structure as claimed in claim 1, wherein a portion of the redistribution layer (RDL) structure that is in direct contact with the conductive adhesive layer has a first symmetrical line, the conductive adhesive layer has a second symmetrical line, and the first symmetrical line is aligned with the second symmetrical line (Koike, Fig. 1, 22 and 20 have matching horizontal dimensions). Regarding claim 10, Koike teaches the semiconductor package structure as claimed in claim 1, wherein the conductive adhesive layer comprises two or more metal layers (Koike para. 26, the reference states it is preferably a preferably a Cu/Ti laminated film) . Regarding claim 11, Koike teaches the semiconductor package structure as claimed in claim 1, wherein the conductive adhesive layer comprises: a first adhesive film on the conductive pad (Koike, para. 26, Ti film); and a second adhesive film on the first adhesive film (Koike, para. 26 Cu film), wherein the first adhesive film and the second adhesive film include different conductive materials (Koike, para. 26). Regarding claim 14, Koike teaches the semiconductor package structure as claimed in claim 1, wherein the dielectric layer ( Koike, 21, Fig. 1) that is formed over the passivation layer and the conductive adhesive layer has a flat top surface. Regarding claim 15, Koike teaches the semiconductor package structure as claimed in claim 1, wherein the dielectric layer is a first dielectric layer (Koike 21, Fig. 1, para. 21), and the semiconductor package structure further comprises: a second dielectric layer (Koike, 32, Fig. 1, para. 21) over the redistribution layer (RDL) structure, wherein the second dielectric layer exposes a portion of a top surface of the redistribution layer (RDL) structure(Koike, Fig. 1 shows 32 has an opening exposing part of 31, the top portion of the RDL structure) . Regarding claim 17, Koike teaches the semiconductor package structure as claimed in claim 1, wherein the bump structure comprises: an under-bump metallurgy (UBM) layer (Koike, 40, Fig. 1, para. 21) over the redistribution layer (RDL) structure; and a solder portion over the UBM layer (Koike, 42, Fig. 1, para 21, 41), wherein the UBM layer is in direct contact with a top surface of the redistribution layer (RDL) structure (Koike, Fig. 1, 40 is in direct contact with 31), and the solder portion is electrically connected to the semiconductor substrate through the UBM layer, the redistribution layer (RDL) structure, the conductive adhesive layer and the conductive pad (Koike, Fig. 1). Claim Rejections 35 U.S.C § 10 3 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . Claim s 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Koike . Regarding claim 12, Koike teaches the semiconductor package structure as claimed in claim 11, but does not teach wherein an adhesion between the conductive pad and the first adhesive film is stronger than an adhesion between the conductive pad and the redistribution layer (RDL) structure. Koike teach es a Cu/Ti laminated film (Koike, para. 26) for the conductive adhesive layer , but is silent on which layer is in contact with the conductive pad and which is in contact with the RDL structure. Per para. 36 of the specification of the instant application the first adhesive film material is a titanium based material and the second adhesive film is a copper based material. In accordance with MPEP 2112.01 II "Products of identical chemical composition cannot have mutually exclusive properties." In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). A chemical composition and its properties are inseparable. Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the application to perform routine experimentation to determine which order of laminated films produced optimal results, resulting in good electric characteristics of the fabricated semiconductor device (Koike, para. 9). Regarding claim 13, Koike teaches the semiconductor package structure as claimed in claim 11, but does not teach wherein the second adhesive film and the redistribution layer (RDL) structure (Koike, para 28, Cu) include the same material. Koike does teach that the RDL layer is made of copper, (Koike, para s . 28 , 32, 34). Additionally, Koike teaches a Cu/Ti laminated film (Koike, para. 26) for the UMB film (Koike, 20B, Fig. 4, para. 26) , but is silent on which layer is in contact with the conductive pad and which is in contact with the RDL structure. Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the application to perform routine experimentation to determine which order of laminated films produced optimal results, resulting in good electric characteristics of the fabricated semiconductor device (Koike, para. 9). Claims 3, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Koike as applied to claim 1 above, and further in view of Torii et al. ( Torii; Katsuhiro ) , hereinafter referred to as Torii . Regarding claim 3, Koike teaches the semiconductor package structure as claimed in claim 1, but does not teach wherein a contact area between the conductive adhesive layer and the conductive pad is greater than a contact area between the redistribution layer (RDL) structure and the conductive adhesive layer. However, Torii teaches a buffer layer (Torii, 47, Fig. 1, para. 57). This buffer layer comprises a titanium/titanium nitride film (Torii, 47a, Fig. 7, para 72), an aluminum film (Torii, 47b, Fig. 7, para. 72, and a titanium nitride film (Torii, 47c, Fig. 7, para. 72). The contact area between the titanium nitride is significantly larger than the contact area between the titanium nitride film and the RDL structure (Torii, 51, Fig. 4, para. 59) Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Koike with the layer interface of Torii to relax stress caused by expansion and contraction (Torii, para. 57) Regarding claim 9, Koike teaches the semiconductor package structure as claimed in claim 1, but does not teach wherein the conductive adhesive layer includes a wing portion that extends on the passivation layer, and the wing portion of the conductive adhesive layer is disposed between the dielectric layer and the passivation layer. However, Torii teaches a buffer layer (Torii, 47, Fig. 1, para. 57). This buffer layer comprises a titanium/titanium nitride film (Torii, 47a, Fig. 7, para 72), an aluminum film (Torii, 47b, Fig. 7, para. 72, and a titanium nitride film (Torii, 47c, Fig. 7, para. 72). The contact area between the titanium nitride is significantly larger than the contact area between the titanium nitride film and the RDL structure (Torii, 51, Fig. 4, para. 59) Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Koike with the layer interface of Torii to relax stress caused by expansion and contraction (Torii, para. 57) Claim 16, is rejected under 35 U.S.C. 103 as being unpatentable over Koike as applied to claim 15 above, and further in view of Lu . Regarding claim 16, Koike teaches the semiconductor package structure as claimed in claim 15, wherein the redistribution layer (RDL) structure is a first redistribution layer (RDL) structure, but does not teach and the semiconductor package structure further comprises: a second redistribution layer (RDL) structure disposed on the second dielectric layer and electrically connected to the first redistribution layer (RDL) structure, wherein the bump structure is disposed over the second redistribution layer (RDL) structure; and wherein the bump structure is electrically connected to the semiconductor substrate through the second redistribution layer (RDL) structure, the first redistribution layer (RDL) structure, the conductive adhesive layer and the conductive pad. However, Lu teaches a first redistributive layer (Lu, 190, Fig. 1G, para. 54, 55 ), and a second redistribution layer (RDL) structure (Lu, 210, Fig. 1G, para. 64) disposed on the second dielectric layer and electrically connected to the first redistribution layer (RDL) structure (210, Fig. 1G, para. 64), wherein the bump structure (Lu, 250/260, Fig. 1G, para. 66-67) is disposed over the second redistribution layer (RDL) structure . Combining the semiconductor device of Koike with the second RDL of Lu would create a device with an electrical path wherein the bump structure is electrically connected to the semiconductor substrate through the second redistribution layer (RDL) structure, the first redistribution layer (RDL) structure, the conductive adhesive layer and the conductive pad . Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Koike with the second RDL of Lu to “fan-out” the I/O pads to the area outside of the die area so as to accommodate high I/O devices for a given ball pitch requirement (Lu, para. 2). Claim 18, is rejected under 35 U.S.C. 103 as being unpatentable over Koike as applied to claim 1 above, and further in view of Chi et al. (US Pub 20200312732) hereinafter referred to as Chi. Regarding c la im 18, Koike teaches the semiconductor package structure as claimed in claim 1, but does not teach a molding layer surrounding the semiconductor substrate, the passivation layer, the dielectric layer and the conductive adhesive layer. However, Chi taches a protective insulating layer (Chi, 110, Fig. 2B, paras. 43-44) which extends from the substrate (Chi, 100, Fig. 2B) to the same level as the RDL (Chi, 106, Fig. 2B). Combining the protective insulating layer of Chi with the semiconductor device of Koike would provide a molding layer surrounding the semiconductor substrate, the passivation layer, the dielectric layer and the conductive adhesive layer . Therefore it would have been obvious to one having ordinary skill in art before the filing d ate of the invention to combine the protective insulating layer of Chi with the semiconductor device of Koike to provide a molding layer surrounding the semiconductor substrate, the passivation layer, the dielectric layer and the conductive adhesive layer . This would have protected the semiconductor device from the environment thereby preventing the semiconductor die in the subsequently formed semiconductor package structure from damage due to, for example, the stress, the chemicals and/or the moisture ( Chi, para. 43) Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Liu et al. ( US Pub 20170098589 ) teaches a semiconductor device with multiple redistributive layers. Park et al. (US Pub 20210043592 ) teaches a passivation layer with an opening that exposes the conductive pad. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT KIERAN M CUNNINGHAM whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-9654 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Mon-Fri 7:30-5:00 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KIERAN M. CUNNINGHAM/ /Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893