Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections,
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-8, 10, and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over and Jeng et al. (US Pub. 20190006314), hereinafter referred to as Jeng and Lim et al. (US Pub. 20140252641) hereinafter referred to as Lim .
Regarding claim 1, Jeng teaches a semiconductor package structure, comprising:
a semiconductor substrate (Jeng, 100, Fig. 1K, para. 14); a conductive pad on the semiconductor substrate (Jeng, 120, Fig. 1K, para. 20); a passivation layer on the semiconductor substrate and the conductive pad (Jeng, 130, Fig. 1K, para. 21), wherein the passivation layer exposes a portion of a top surface of the conductive pad (Jeng, 120A, Fig. 1J, para. 21); a dielectric layer (Jeng, 350, Fig. 1K, para. 55) on the passivation layer, wherein the dielectric layer exposes a portion of a top surface of the conductive pad; (Jeng, 360, Fig. 1I, para. 57) a redistribution layer (RDL) structure (Jeng, 370, Fig. 1K, para. 54, 59) on the dielectric layer and electrically connected to the conductive pad; and a bump structure (Jeng, 440, 450, Fig. 1K, paras. 63-64) over the redistribution layer (RDL) structure.
Jeng also teaches that the dielectric layer (Jeng, 350, Fig. 1K) extends in the passivation layer (Jeng, 130 Fig. 1K) to adjoin the top surface (Jeng, 120A, Fig. 1K) of the conductive pads (Jeng, 120 Fig. 1K). The junction of the passivation layer and the dielectric layer has sidewall portions and wing portions (Jeng, Fig. 1K, see diagram below).
Jeng does not teach; a conductive adhesive layer on the conductive pad; a dielectric layer on the passivation layer and the conductive adhesive layer; wherein the dielectric layer exposes a portion of a top surface of the conductive adhesive layer; a redistribution layer (RDL) structure on the dielectric layer and electrically connected to the conductive pad through the conductive adhesive layer; wherein the conductive adhesive layer comprises a wing portion, a sidewall portion, and a bottom portion, wherein the portion of the top surface of the conductive adhesive layer exposed by the dielectric layer is a first part of a top surface of the bottom portion, wherein the wing portion extends on the passivation layer, the sidewall portion extends along an inner sidewall of the passivation layer, and an entirety of the wing portion and an entirety of the sidewall portion are disposed between the dielectric layer and the passivation layer and are covered by the dielectric layer, and wherein a second part of the top surface of the bottom portion is covered by the dielectric layer.
However, Lim teaches a semiconductor device with semiconductor die (Lim 124, Fig. 11f, para. 111) conductive pad (Lim, 132, Fig. 11f, para. ) wherein a passivation layer (Lim, 264, Fig. 11f, paras. 113-114) is disposed on the substrate such that an opening is provided in the passivation layer above the conductive pad and an adhesive layer (Lim, 276, Fig. 11f, para. 116) is disposed on the sidewalls and a portion of the top of the passivation layer in a winglike configuration, and on the top portion of the conductive pad. Additionally, Lim teaches wherein the adhesive layer is in direct contact with a conductive layer (Lim, 278, Fig. 11f, para. 118).
Therefore it would be obvious to one having ordinary skill in the art before the filing date of the invention to combine the adhesive layer of Lim on the conductive pad and passivation layer of Jeng, wherein the sidewall and wing portions of the adhesive layer are sandwiched between the passivation layer and dielectric layers of Jeng in order to provide improved adhesion and wetting (Lim, para. 116).
Regarding claim 2, modified Jeng teaches the semiconductor package structure as claimed in claim 1, wherein the exposed top surface of the conductive adhesive layer is in direct contact with the redistribution layer (RDL) structure (Lem: Fig. 11F shows the RDL, 278 in contact with the adhesive layer 276, see Fig. below).
Regarding claim 3, modified Jeng teaches the semiconductor package structure as claimed in claim 1, wherein a contact area between the conductive adhesive layer and the conductive pad is greater than a contact area between the redistribution layer (RDL) structure and the conductive adhesive layer.
The adhesive layer of Lim (Lim, 276, Fig. 11f, para. 116) is disposed in the opening of the passivation layer (Jeng 130, Fig. 1K) of Jeng and has wing portions beyond the sidewall portion. The dielectric layer of Jeng (Jeng, 350, Fig. 1K, para. 55) is then disposed over wing portions, sidewall portions and part of the top portion over the conductive pad (Jeng, Fig. 1K shows the dielectric layer in contact with a portion of the top of the conductive pad). Because the dielectric layer would take up a portion of the top portion of the adhesive layer above the conductive pad, contact area between the conductive adhesive layer and the conductive pad is necessarily greater than the contact area between the RDL structure and the conductive adhesive layer.
Regarding claim 4, modified Jeng teaches the semiconductor package structure as claimed in claim 1, wherein the passivation layer has a first opening that exposes the portion of the top surface of the conductive pad (Jeng, para. 21 and Lim. 268, para. 114, the vias 268, of Lim correspond to the openings mentioned in para. 21 of Jeng ), and the conductive adhesive layer is configured as a liner in the first opening (Lim, para. 116).
Regarding claim 5, modified Jeng teaches the semiconductor package structure as claimed in claim 4, wherein the dielectric layer has a second opening (Jeng, 360, Fig. 1I, para. 57, in Jeng it exposes the top portion of the conductive pad, which will be covered by the conductive adhesive layer of Lim) that exposes the portion of the top surface of the conductive adhesive layer, and the redistribution layer (RDL) (Jeng, 37, Fig. 1J, para. 59, see diagram below) structure comprises a pillar portion in the second opening.
Regarding claim 6, modified Jeng teaches the semiconductor package structure as claimed in claim 5, wherein the first opening is greater than the second opening(Jeng Fig. 1J) Fig. 1J shows the dielectric layer (Jeng, 350, Fig. 1J) occupying a portion of the first opening and the conductive layer (Jeng, Fig. 1J, 370) occupying the second opening (Jeng, 360 Fig. 1J). Because the second opening is in the dielectric and the dielectric is disposed on the sidewalls and a portion of the bottom of the first opening to form the second opening the second opening is necessarily smaller than the first opening.
Regarding claim 7, modified Jeng teaches the semiconductor package structure as claimed in claim 5, wherein a bottom surface of the pillar portion of the redistribution layer (RDL) structure is in direct contact with the top surface of the conductive adhesive layer. Jeng teaches wherein the conductive structure (Jeng, 370, Fig, 1J) is disposed in the opening (Jeng, 360, Fig. 1J) in the dielectric layer (Jeng, 350, Fig. 1J) over the conductive pad (Jeng, 120). Because Lim teaches that the conductive adhesive layer (Lim, 276, Fig.11f) is disposed over the conductive pad (Lim, 132, Fig. 11f) the combination would result in the bottom portion of the pillar portion of the RDL being in contact with the top surface of the conductive adhesive layer.
Regarding claim 8, modified Jeng teaches the semiconductor package structure as claimed in claim 1, wherein a portion of the redistribution layer (RDL) structure that is in direct contact with the conductive adhesive layer has a first symmetrical line, the conductive adhesive layer has a second symmetrical line, and the first symmetrical line is aligned with the second symmetrical line. Lim, Fig. 11f shows that the portion of the conductive adhesive layer (Lim, 276, Fig. 11F) in contact with the conductive layer (Lim, 278, Fig. 11f) are symmetrical with relation to one another and a symmetrical line through one will be aligned with a symmetrical line through the other.
Regarding claim 10, modified Jeng teaches the semiconductor package structure as claimed in claim 1, wherein the conductive adhesive layer comprises two or more metal layers (Lim, para. 116).
Regarding claim 14, modified Jeng teaches the semiconductor package structure as claimed in claim 1, wherein the dielectric layer that is formed over the passivation layer and the conductive adhesive layer has a flat top surface (Jeng, 350, Fig. 1I).
Regarding claim 15, modified Jeng teaches the semiconductor package structure as claimed in claim 1, wherein the dielectric layer is a first dielectric layer, and the semiconductor package structure further comprises: a second dielectric layer (Jeng, 380, Fig. 1K, para. 62 over the redistribution layer (RDL) structure, wherein the second dielectric layer exposes a portion of a top surface of the redistribution layer (RDL) structure (Jeng, Fig. 1K, para. 62, para 62 states that the construction methods are similar and thus the dielectric layer 380 has an opening for the conductive layer 390 to contact conductive layer 370 as shown in Fig. 1K),
Regarding claim 16, modified Jeng teaches the semiconductor package structure as claimed in claim 15, wherein the redistribution layer (RDL) structure is a first redistribution layer (RDL) structure, and the semiconductor package structure further comprises: a second redistribution layer (RDL) structure (Jeng, 390, Fig. 1K, paras. 54, 62) disposed on the second dielectric layer (Jeng, 380, Fig. 1K) and electrically connected to the first redistribution layer (RDL) structure (Jeng, Fig. 1K), wherein the bump structure (Jeng, 440, 450, Fig. 1K, paras. 63-64) is disposed over the second redistribution layer (RDL) structure; and wherein the bump structure is electrically connected to the semiconductor substrate through the second redistribution layer (RDL) structure (Jeng, 390, Fig. 1K, para. 54),the first redistribution layer (RDL) structure (Jeng, 370, Fig. 1K, para. 54), the conductive adhesive layer (Lim, 276, Fig. 11f para. 116) and the conductive pad (Jeng, 120, para. 20).
Regarding claim 17, modified Jeng teaches the semiconductor package structure as claimed in claim 1, wherein the bump structure (Jeng, 440, 450, Fig. 1K, paras. 63-64) comprises: an under-bump metallurgy (UBM) layer (Jeng, 440, Fig. 1K, para. 63) over the redistribution layer (RDL) structure (Jeng, Fig. 1K, the UMB layer, 440 is disposed on RDL layer 410, which is disposed over RDL layers 390 and 370);and a solder portion (Jeng, 450, Fig. 1K, para. 64) over the UBM layer, wherein the UBM layer is in direct contact with a top surface of the redistribution layer (RDL) structure (Jeng, Fig. 1K shows the UBM layer, 440 in direct contact with the top surface of RDL layer 410, which is stacked as the third RDL layer with the first layer being 370, however, Lim, Fig. 11i, shows the bump 288 directly connected to the conductive layer 278, which is directly connected to the conductive adhesive layer 276), and the solder portion is electrically connected to the semiconductor substrate through the UBM layer, the redistribution layer (RDL) structure, the conductive adhesive layer and the conductive pad (Lim, paras. 116,118, 120 para. 116 shows the electrical connection from the semiconductor die, 124 to conductive layer 276 through 132, para. 118 shows the electrical connection from 132 to 278, para. 120 shows that bump 288 is connected to conductive layer 278, thus establish a continuous electrical connection).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Jeng and Lim as applied to claim 1 above, and further in view of Koike (US Pub. 20110198748), hereinafter referred to as Koike.
Regarding claim 11, modified Jeng teaches the semiconductor package structure as claimed in claim 1, but does not teach wherein the conductive adhesive layer comprises: a first adhesive film on the conductive pad; and a second adhesive film on the first adhesive film, wherein the first adhesive film and the second adhesive film include different conductive materials.
Lim does teach wherein the conductive layer (Lim, 376, Fig. 11f) contains one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material (Lim, para. 116).
However, Koike teaches a semiconductor device with a conductive adhesive layer (Koike, 20, Fig. 19, para. 26, it is formed from UMB film 20b, in Fig. 4, para. 26) between an electrode pad (Koike, 15, Fig. 19, para. 20) and the electrically conductive post portion of an RDL structure RDL structure (Koike, 22, Fig. 19, para. 21) wherein the wherein the conductive adhesive layer comprises: a first adhesive film on the conductive pad (Koike, para. 26, Ti film); and a second adhesive film on the first adhesive film (Koike, para. 26 Cu film), wherein the first adhesive film and the second adhesive film include different conductive materials (Koike, para. 26).
Therefore it would have been obvious to one having ordinary skill in the art to have combined the structure of Jeng and Lim with the laminated film of Koike in order to provide sealing on the electrode contact and suppress damage from etching (Koike, para. 43)
Regarding claim 12, modified Jeng teaches the semiconductor package structure as claimed in claim 11, but does not teach wherein an adhesion between the conductive pad and the first adhesive film is stronger than an adhesion between the conductive pad and the redistribution
layer (RDL) structure.
Koike teaches a Cu/Ti laminated film (Koike, para. 26) but is silent on the specific ordering of the layers. It is well established that where the prior art discloses the components of a structure but is silent on their specific arrangement, it would have been obvious to a person of ordinary skill in the art to determine the optimal arrangement through routine experimentation. Therefore, it would have been obvious to optimize the order of the Cu and Ti layers to achieve the strongest adhesion between the conductive pad and the RDL structure, resulting in good electric characteristics (Koike, para. 9).
Therefore it would have been obvious to one having ordinary skill in the art before the
filing date of the application to perform routine experimentation to determine which order of
laminated films produced optimal results, resulting in good electric characteristics of the
fabricated semiconductor device (Koike, para. 9).
Regarding claim 13, Koike teaches the semiconductor package structure as claimed in
claim 11, but does not teach wherein the second adhesive film and the redistribution layer (RDL)
structure (Koike, para 28, Cu) include the same material. Koike does teach that the RDL layer is made of copper, (Koike, , 22, Fig. 19 paras. 28, 32, 34). Additionally, Koike teaches a Cu/Ti laminated film (Koike, para. 26) for the UMB film (Koike, 20B, Fig. 4, para. 26), but is silent on which layer is in contact with the conductive pad and which is in contact with the RDL structure. Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the application to perform routine experimentation to determine which order of laminated films produced optimal results, resulting in good electric characteristics of the fabricated semiconductor device (Koike, para. 9).
Claim 18, is rejected under 35 U.S.C. 103 as being unpatentable over Jeng and Lim as applied to claim 1 above, and further in view of Chi et al. (US Pub 20200312732) hereinafter referred to as Chi.
Regarding claim 18, modified Jeng teaches the semiconductor package structure as claimed in claim 1, but does not teach a molding layer surrounding the semiconductor substrate, the passivation layer, the dielectric layer and the conductive adhesive layer.
However, Chi taches a protective insulating layer (Chi, 110, Fig. 2B, paras. 43-44) which
extends from the substrate (Chi, 100, Fig. 2B) to the same level as the RDL (Chi, 106, Fig. 2B).
Combining the protective insulating layer of Chi with the semiconductor device of Jeng and Lim would provide a molding layer surrounding the semiconductor substrate, the passivation layer, the dielectric layer and the conductive adhesive layer.
Therefore it would have been obvious to one having ordinary skill in art before the filing
date of the invention to combine the protective insulating layer of Chi with the semiconductor
device of Koike to provide a molding layer surrounding the semiconductor substrate, the
passivation layer, the dielectric layer and the conductive adhesive layer. This would have
protected the semiconductor device from the environment thereby preventing the semiconductor
die in the subsequently formed semiconductor package structure from damage due to, for
example, the stress, the chemicals and/or the moisture ( Chi, para. 43).
Response to Arguments
Applicant’s arguments, see page 11 line 6- page 16, line 3, filed 6/28/2026, with respect to the rejections of claims 1, 2, 4-8 10-11, 14-15 and 17 under 35 U.S.C § 102 and 3, 12, 13, 16, and 18 under 35 U.S.C § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, new grounds of rejection is made in view of Jeng, and Lim with respect to claims 1-8, 10 and 14-17, in view of Jeng and Lim, further in view of Koike with respect to claims 11-13 and in view of Jeng and Lim further in view of Chi with respect to 18
Applicant amended claim 1 to include the limitations of cancelled claim 9 and to further include a sidewall portion of the conductive adhesive layer and to further include the dielectric layer overlaps the conductive adhesive layer and is in contact with a second portion of the first top surface of the conductive adhesive layer, which is disposed directly on the conductive pad.
Examiner determined, as described in detail above, that the structure of Jeng, wherein the dielectric layer is in contact with a portion of the conductive pad and structure of Jeng, wherein the adhesive contact layer has a top portion on the conductive pad, a sidewall portion disposed on the passivation layer and wing portions further disposed on the passivation layer. would have been an obvious combination to one of ordinary skill in the art to satisfy these limitations.
Applicant did not further amend any dependent claims.
All dependent features in claims 2-8, 10 and 14-17 were found to be obvious to one of ordinary skill in the art before the filing date of the invention in view of Jeng and Lim.
Dependent claims 11-13 were found to be obvious to one of ordinary skill in the art before the filing date of the invention in view of Jeng and Lim, and further in view of Koike.
Dependent claims 11-13 were directed towards the make-up of the conductive adhesive film. While the conductive adhesive film of Lim could have had multiple layers they were not explicitly described as being of different metals. Koike described a laminated film made up of titanium and copper.
Dependent claim 19 was found to be obvious to one of ordinary skill in the art before the filing date of the invention Jeng and Lim, and further in view of Chi.
Dependent claim 18 is directing to a molding layer surrounding the semiconductor structure, and Chi teaches a protective insulating structure made up of an epoxy molding compound surrounding the structure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US Pub. 20160233187). teaches a semiconductor package with a bump structure that includes an under bump conductive layer.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:30-5:30.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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