DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A claims 1-10 in the reply filed on 01/28/2026 is acknowledged.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2023-0044057, filed on 04/04/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/09/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, and 10 are rejected under U.S.C. 103 as being unpatentable over Tamon; US 7983083 B2; 05/2009 in view of Kim; US 8350307 B2; 08/2009
Claim 1: Tamon discloses a semiconductor device, comprising: a semiconductor substrate ( Fig. 5 semiconductor substrate 2 ) including a cell area ( Fig. 1: memory cell area M ) and a peripheral area ( Fig. 1: peripheral circuit area P ), the peripheral area including a first area ( Fig. 10A Bj+1) and a second area ( Fig. 10A Bj ) adjacent to each other; first transistors ( Col. 8 lines 54-57 As illustrated in FIG. 10A, the peripheral circuit applies a ground voltage (0 V) to the bit line BL (BL.sub.0 to BL.sub.n-1) to which a cell unit UC including a memory cell transistor MT of the write-target is connected) on the first area ( Fig. 10A Bj+1 ); a first wiring layer ( Fig. 6 WL0 ) on the first transistors ( as described above ); a first pad ( Fig. 6 13a on the Bj area ) on the second area ( Fig. 6 Bj ) and on a portion of the first area ( Fig. 6 Bj+1 covered by 13a ); a first contact plug ( Fig. 6 VP1 contacting WL0 contacting in the Bj+1 area ) between the first wiring layer ( Fig. 6 WL0 ) and the first area ( Fig. 6 Bj+1 ); a second contact plug ( Fig. 6 VP1 contacting WL0 in the Bj area ) between the first pad ( Fig. 6 13a connecting WL0 in Bj and Bj+1 ) and the first area ( Fig. 6 Bj+1 ); a second pad ( Fig. 7: 15 connecting WL0 between Bj and Bj+1 ) on the first wiring layer ( Fig. 7: WL0 ); a third contact plug ( Fig. 7: VP2 on WL0 in the Bj+1 area ) between the second pad ( as discussed above ) and the first wiring layer ( Fig. 7: WL0 );
Tamon does not appear to disclose a plurality of first capacitors on the second pad vertically overlapping the first transistors.
However, Kim teaches a plurality of first capacitors ( Fig. 5: top electrodes 428 and 429 of capacitors with bottom electrodes 425 ) on the second pad ( Fig. 5 : gate 424) vertically overlapping the first transistors ( Fig. 5: transistor composed of 422, 423, and GP in the peripheral region ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kim with Tamon to implement a plurality of first capacitors on the second pad vertically overlapping the first transistors because this will minimize chip area and maximize electrical performance.
Claim 4: Tamon and Kim disclose the semiconductor device as claimed in claim 1 ( as discussed above ).
Tamon teaches further comprising a device isolation film ( Fig. 6 dummy area R2 ) on the semiconductor substrate ( Col. 6 lines 39-42 The via-plugs VP1 that extend perpendicularly to the substrate surface are provided at both end portions of the connection portions 13a ) spacing apart the first area ( Fig. 6 Bj+1 ) and the second area ( Fig. 6 Bj ).
Claim 5: Tamon and Kim disclose the semiconductor device as claimed in claim 1 ( as discussed above).
Tamon teaches wherein the second pad ( Fig. 7 #15 ) is on the first area ( Fig. 7 Bj+1 ) and on a portion of the second area ( Fig. 7 Bj).
Claim 6: Tamon and Kim disclose the semiconductor device as claimed in claim 1 ( as discussed above).
Tamon does not appear to disclose plates on the first capacitors and a residual plate on the second area.
However, Kim teaches plates on the first capacitors ( Fig. 5: top electrodes 428 and 429 ) and a residual plate ( Fig. 5: bottom electrode 425 ) on the second area ( Fig. 5: peripheral area ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kim with Tamon to implement plates on the first capacitors and a residual plate on the second area because this increases total capacitance within a restricted, shrinking, or oddly shaped chip area.
Claim 10: Tamon and Kim disclose the semiconductor device as claimed in claim 1 ( as discussed above).
Tamon teaches the first pad ( Fig. 6: 13a on the Bj area 3) and the second pad ( Fig. 7: 15 connecting WL0 between Bj and Bj+1 ) are spaced apart from each other in a third direction perpendicular to an upper surface of the semiconductor substrate ( Fig. 8: first pad 13 on layer LY3 and second pad 15 on layer LY7 ).
Claims 2 and 3 are rejected under U.S.C. 103 as being unpatentable over Tamon; US 7983083 B2; 05/2009 in view of Kim; US 8350307 B2; 08/2009 as it relates to claim 1 and further in view of Zhang et al.; US 2024/0385485 A1; 09/2022
Claim 2: Tamon and Kim disclose the semiconductor device as claimed in claim 1 ( as discussed above)
Neither Tamon nor Kim appear to disclose dummy transistors on the second area.
However, Zhang teaches further comprising dummy transistors (Fig. 4 dummy transistors Dummy TFT ) on the second area ( [0131] the second active area includes a plurality of dummy transistors Dummy TFT).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Zhang with Tamon and Kim to implement dummy transistors on the second area because this ensures uniform etching, lithography, and polishing during manufacturing.
Claim 3: Tamon, Kim, and Zhang discloses the semiconductor device as claimed in claim 2 (as discussed above).
Neither Tamon nor Kim appear to disclose the first pad vertically overlaps the dummy transistors, and the second pad vertically overlaps the first capacitors.
However, Zhang teaches the first pad ( [0131] gates of the dummy transistors Dummy TFT are electrically connected to the grid lines GL ) vertically overlaps the dummy transistors (Fig. 4: dummy transistors Dummy TFT ), and the second pad ( [0185] the first electrode (the first conductive patterns of the second part 2/22) of the second dummy capacitance Dummy C2 can be in direct contact with the common electrode line CML (Common Line)) vertically overlaps the first capacitors (Fig. 4: Dummy C2 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Zhang with Tamon and Kim to implement the first pad vertically overlaps the dummy transistors, and the second pad vertically overlaps the first capacitors because this allows for space optimization and reduced parasitic effects.
Claim 7 is rejected under U.S.C. 103 as being unpatentable over Tamon; US 7983083 B2; 05/2009 in view of Kim; US 8350307 B2; 08/2009 as it relates to claim 1 and further in view of Choi et al.; US 12,575,106 B2; 03/2023
Claim 7: Tamon and Kim disclose the semiconductor device as claimed in claim 1 ( as discussed above).
Neither Tamon nor Kim appear to disclose the third contact plug includes a conductive plug and a barrier metal, and the barrier metal covers a side surface and a lower surface of the conductive plug.
However, Choi teaches the third contact plug ( Fig. 6A: through contact plug TCP ) includes a conductive plug ( Col. 10 lines 19-21 the through contact plug TCP may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM ) and a barrier metal ( Fig. 6A: barrier pattern BM ), and the barrier metal covers a side surface and a lower surface of the conductive plug ( as discussed above ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Choi with Tamon and Kim to implement the third contact plug includes a conductive plug and a barrier metal, and the barrier metal covers a side surface and a lower surface of the conductive plug because this ensures electrical stability, reliability, and device performance.
Claim 8 is rejected under U.S.C. 103 as being unpatentable over Tamon; US 7983083 B2; 05/2009 in view of Kim; US 8350307 B2; 08/2009 and Choi et al.; US 12,575,106 B2; 03/2023 as it relates to claim 7 and further in view of Harada et al.; US 6,040,627; 04/1998
Claim 8: Tamon, Kim, and Choi disclose the semiconductor device as claimed in claim 7 ( as discussed above ).
Neither Tamon nor Kim nor Choi appear to disclose the barrier metal extends from the side surface of the conductive plug and is on a lower surface of the second pad.
However, Harada teaches the barrier metal ( Fig. 1(a) barrier metal 4 ) extends from the side surface of the conductive plug ( Fig. 1(a) conductive plug 52 ) and is on a lower surface of the second pad ( Fig. 1(a) conductive film 5 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Harada with Tamon, Kim, and Choi to implement the barrier metal extends from the side surface of the conductive plug and is on a lower surface of the second pad because this addresses diffusion prevention and addresses corrosion resistance.
Claim 9 is rejected under U.S.C. 103 as being unpatentable over Tamon; US 7983083 B2; 05/2009 in view of Kim; US 8350307 B2; 08/2009, Choi et al.; US 12,575,106 B2; 03/2023, and Harada et al.; US 6,040,627; 04/1998 as it relates to claim 8 and further in view of Huang et al.; US 12,575,356 B2; 06/2022
Claim 9: Tamon, Kim, Choi, and Harada disclose the semiconductor device as claimed in claim 8 ( as discussed above ).
Neither Tamon nor Kim nor Choi nor Harada appear to disclose the conductive plug includes a material different from a material of the second pad.
However, Huang teaches the conductive plug ( Fig. 1C contact plug 134 ) includes a material ( Col. 8 lines 6 – 14 contact plugs 134 can include conductive materials with low resistivity (e.g., resistivity of about 50 μΩ-cm, about 40 μΩ-cm, about 30 μΩ-cm, about 20 μΩ-cm, or about 10 μΩ-cm), such as cobalt (Co), tungsten (W), ruthenium (Ru), iridium (Ir), nickel (Ni), Osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), other suitable conductive materials with low resistivity, and a combination thereof ) different from a material ( Col. 8 lines via structures 136 can be disposed on contact structures 130 and can include conductive materials, such as Ru, Co, Ni, Al, Mo, W, Ir, Os, Cu, and Pt; since there are multiple options the conductive plug could be different from the second pad ) of the second pad ( Fig. 1C via structures 136 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Huang with Tamon, Kim, Choi, and Harada to implement the conductive plug includes a material different from a material of the second pad because this improves the diffusion barrier and addresses adhesion needs.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817