DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application KR 10-2023-0006510 filed in Korean Intellectual Property Office (KIPO) on January 17, 2023 and receipt of a certified copy thereof.
Information Disclosure Statement
The information disclosure statement (IDS) filed on November 9, 2023, IDS filed on June 26, 2024, IDS filed on September 25, 2024 and IDS filed on November 26, 2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDSs are considered by the examiner.
Specification
The disclosure is objected to because of the following informality:
In the paragraph [0057], line 4, “the fence pattern 475” should be corrected to be --the fence pattern 485--.
Appropriate correction is required.
Drawings
The drawings are objected to for the following informalities:
In Fig. 4, the reference character “105” should be corrected to be --150--. Support can be found at least in Fig. 2B.
In Fig. 18, the reference character “105” should be corrected to be --150--. Support can be found at least in Fig. 17B.
No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d) . If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-9, 12-14, 17-19, 21-24, 27, 30 and 31 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Kim et al. US 2022/0085026 (Kim ‘026).
Regarding claim 1, Kim ‘026 teaches a semiconductor device (e.g., Figs. 1-2, the description thereof) comprising:
an active pattern (e.g., 105, Fig. 2) on a substrate (e.g., 100, Fig. 2);
a gate structure (e.g., 160, Fig. 2) in an upper portion of the active pattern;
a bit line structure (e.g., 325, Fig. 2) on the active pattern;
a spacer structure (e.g., 385, 395(397), 405, Fig. 2; [108]) on a sidewall of the bit line structure, the spacer structure comprising an insulating material (e.g., [35]); and
a lower contact plug (e.g., 425, Fig. 2) on a portion of the active pattern adjacent to the bit line structure, the lower contact plug contacting the spacer structure (e.g., Fig. 2),
wherein the spacer structure comprises a layer having at least two curves and a vertex disposed between and contacting the two curves (e.g., 405, Fig. 2).
Regarding claim 2, Kim ‘026 teaches the semiconductor device according to claim 1, wherein the spacer structure comprises a first spacer (e.g., 385, Fig. 2), a second spacer (e.g., 395(397), Fig. 2) and a third spacer (e.g., 405, Fig. 2) sequentially stacked on the sidewall of the bit line structure, and wherein the layer having the two curves and the vertex comprises the third spacer (e.g., Fig. 2).
Regarding claim 3, Kim ‘026 teaches the semiconductor device according to claim 2, wherein an end portion in a vertical direction of the third spacer comprises the two curves and the vertex (e.g., Fig. 2), the vertical direction being substantially perpendicular to an upper surface of the substrate (e.g., Fig. 2).
Regarding claim 6, Kim ‘026 teaches the semiconductor device according to claim 1, further comprising a protective spacer (e.g., 460, Fig. 2) which contacts an outer sidewall of the spacer structure and comprises a material resistant to a dry etching process (e.g., [43]).
Regarding claim 7, Kim ‘026 teaches the semiconductor device according to claim 6, the protective spacer comprises at least one of titanium nitride (TiN), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN) (e.g., [43]).
Regarding claim 8, Kim ‘026 teaches the semiconductor device according to claim 1, wherein the bit line structure (e.g., 325, Figs. 1-2) is one of a plurality of bit line structures spaced apart from each other in a first direction (e.g., 1st direction, Figs. 1-2), and the lower contact plug (e.g., 425, Figs. 1-2) is one of a plurality of lower contact plugs spaced apart from each other in a second direction (e.g., 2nd direction, Figs. 1-2) substantially parallel to the upper surface of the substrate and intersecting the first direction, and wherein the semiconductor device further comprises a fence pattern (e.g., 430, Figs. 1-2) that is disposed between and separates ones of the plurality of lower contact plugs neighboring in the second direction (e.g., Figs. 1-2).
Regarding claim 9, Kim ‘026 teaches the semiconductor device according to claim 8, wherein the fence pattern contacts the spacer structure (e.g., Fig. 2).
Regarding claim 12, Kim ‘026 teaches the semiconductor device according to claim 1, further comprising: an upper contact plug (e.g., 475, Fig. 2) on the lower contact plug; and a capacitor (e.g., 550, Fig. 2) on the upper contact plug.
Regarding claim 13, Kim ‘026 teaches the semiconductor device according to claim 1, wherein a slope of the layer of the spacer structure changes from a negative value to a positive value at the vertex (e.g., 405, Fig. 2).
Regarding claim 14, Kim ‘026 teaches the semiconductor device according to claim 1, wherein a slope of the layer of the spacer structure non-linearly changes at the vertex (e.g., 405, Fig. 2).
Regarding claim 17, Kim ‘026 teaches a semiconductor device (e.g., Figs. 1-2, the description thereof) comprising:
an active pattern (e.g., 105, Fig. 2) on a substrate (e.g., 100, Fig. 2);
a gate structure (e.g., 160, Fig. 2) in an upper portion of the active pattern;
a bit line structure (e.g., 325, Fig. 2) on the active pattern;
a spacer structure (e.g., 385, 395(397), 405, Fig. 2; [108]) on a sidewall of the bit line structure, the spacer structure comprising an insulating material (e.g., [35]); and
a lower contact plug (e.g., 425, Fig. 2) on a portion of the active pattern adjacent to the bit line structure, the lower contact plug contacting the spacer structure (e.g., Fig. 2),
wherein the spacer structure comprises a layer having a vertex at which a slope non- linearly changes (e.g., 405, Fig. 2).
Regarding claim 18, Kim ‘026 teaches the semiconductor device according to claim 17, wherein the spacer structure comprises a first spacer (e.g., 385, Fig. 2), a second spacer (e.g., 395(397), Fig. 2) and a third spacer (e.g., 405, Fig. 2) sequentially stacked on the sidewall of the bit line structure, and wherein the layer having the vertex comprises the third spacer (e.g., Fig. 2).
Regarding claim 19, Kim ‘026 teaches the semiconductor device according to claim 18, wherein an end portion in a vertical direction of the third spacer comprises the vertex (e.g., Fig. 2).
Regarding claim 21, Kim ‘026 teaches the semiconductor device according to claim 18, further comprising a protective spacer (e.g., 460, Fig. 2) which contacts an outer sidewall of the spacer structure and comprises a material resistant to a dry etching process (e.g., [43]).
Regarding claim 22, Kim ‘026 teaches the semiconductor device according to claim 21, wherein the protective spacer comprises at least one of titanium nitride (TiN), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN) (e.g., [43]).
Regarding claim 23, Kim ‘026 teaches the semiconductor device according to claim 17, wherein the bit line structure (e.g., 325, Figs. 1-2) is one of a plurality of bit line structures spaced apart from each other in a first direction (e.g., 1st direction, Figs. 1-2), and the lower contact plug (e.g., 425, Figs. 1-2) is one of a plurality of lower contact plugs spaced apart from each other in a second direction (e.g., 2nd direction, Figs. 1-2) substantially parallel to the upper surface of the substrate and intersecting the first direction, and wherein the semiconductor device further comprises a fence pattern (e.g., 430, Figs. 1-2) that is disposed between and separates ones of the plurality of lower contact plugs neighboring in the second direction (e.g., Figs. 1-2).
Regarding claim 24, Kim ‘026 teaches the semiconductor device according to claim 23, wherein the fence pattern contacts the spacer structure (e.g., Fig. 2).
Regarding claim 27, Kim ‘026 teaches the semiconductor device according to claim 17, wherein a slope of the layer of the spacer structure changes from a negative value to a positive value at the vertex (e.g., 405, Fig. 2).
Regarding claim 30, Kim ‘026 teaches a semiconductor device (e.g., Figs. 1-2, the description thereof) comprising:
active patterns (e.g., 105, Figs. 1-2) on a substrate (e.g., 100, Fig. 2),
the active patterns (e.g., 105, Figs. 1-2) disposed in first and second directions (e.g., 1st direction, 2nd direction, Figs. 1-2) substantially parallel to an upper surface of the substrate and substantially perpendicular to each other;
an isolation pattern (e.g., 110, Figs. 1-2) covering sidewalls of the active patterns;
gate structures (e.g., 160, Figs. 1-2) spaced apart from each other in the second direction, each of the gate structures formed in upper portions of the active patterns and the isolation pattern and extending in the first direction;
bit line structures (e.g., 325, Figs. 1-2) spaced apart from each other in the first direction, each of the bit line structures being on central portions of ones of the active patterns arranged in the second direction and extending in the second direction (e.g., Figs. 1-2);
a spacer structure (e.g., 385, 395(397), 405, Fig. 2; [108]) on a sidewall in the first direction of each of the bit line structures, the spacer structure comprising first, second and third spacers (e.g., 385, 395(397), 405, Fig. 2) sequentially stacked in the first direction; and
a contact plug structure (e.g., 425, 475, Fig. 2) on each of end portions of each of the active patterns, the contact plug comprising a lower contact plug (e.g., 425, Fig. 2) and an upper contact plug (e.g., 475, Fig. 2) sequentially stacked in a vertical direction substantially perpendicular to an upper surface of the substrate,
wherein the third spacer (e.g., 405, Fig. 2) comprises two curves and a vertex disposed between and contacting the two curves (e.g., Fig. 2).
Regarding claim 31, Kim ‘026 teaches the semiconductor device according to claim 30, wherein an end portion in the vertical direction of the third spacer comprises the two curves and the vertex (e.g., 405, Fig. 2).
Claims 1-3, 6, 8, 9, 12-14, 17-19, 21, 23, 24, 27, 30 and 31 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Kim et al. US 2019/0206873 (Kim ‘873).
Regarding claim 1, Kim ‘873 teaches a semiconductor device (e.g., Figs. 26-27, the description thereof; also see Figs. 1-25 and the description thereof) comprising:
an active pattern (e.g., 105, Fig. 27) on a substrate (e.g., 100, Fig. 27);
a gate structure (e.g., 160, Fig. 27) in an upper portion of the active pattern;
a bit line structure (e.g., 305, Fig. 27) on the active pattern;
a spacer structure (e.g., 315, 340(520) and/or 375, Fig. 27; [67]) on a sidewall of the bit line structure, the spacer structure comprising an insulating material (e.g., [35], [37], [42]); and
a lower contact plug (e.g., 440 (not labeled) that are disposed in 430, Fig. 27; Fig. 21) on a portion of the active pattern adjacent to the bit line structure, the lower contact plug contacting the spacer structure (e.g., Fig. 27; Fig. 21),
wherein the spacer structure comprises a layer having at least two curves and a vertex disposed between and contacting the two curves (e.g., 375, Fig. 27).
Regarding claim 2, Kim ‘873 teaches the semiconductor device according to claim 1, wherein the spacer structure comprises a first spacer (e.g., 315, Fig. 27), a second spacer (e.g., 340(520), Fig. 27) and a third spacer (e.g., 375, Fig. 27) sequentially stacked on the sidewall of the bit line structure, and wherein the layer having the two curves and the vertex comprises the third spacer (e.g., Fig. 27).
Regarding claim 3, Kim ‘873 teaches the semiconductor device according to claim 2, wherein an end portion in a vertical direction of the third spacer comprises the two curves and the vertex (e.g., Fig. 27), the vertical direction being substantially perpendicular to an upper surface of the substrate (e.g., Fig. 27).
Regarding claim 6, Kim ‘873 teaches the semiconductor device according to claim 1, further comprising a protective spacer (e.g., 340, Fig. 27) which contacts an outer sidewall of the spacer structure and comprises a material resistant to a dry etching process (e.g., silicon oxide of 340 (e.g., [37]) may be resistant to a dry etching process to some extent depending on various/different operation conditions of a dry etching process; Applicant did not specifically claim what material the protective spacer is composed of, in what conditions the dry etching process is performed, and the like).
Regarding claim 8, Kim ‘873 teaches the semiconductor device according to claim 1, wherein the bit line structure (e.g., 305, Fig. 26-27) is one of a plurality of bit line structures spaced apart from each other in a first direction (e.g., 1st direction, Figs. 26-27), and the lower contact plug (e.g., 440 (not labeled) that are disposed in 430, Fig. 27; Fig. 21) is one of a plurality of lower contact plugs spaced apart from each other in a second direction (e.g., 2nd direction, Figs. 26-27) substantially parallel to the upper surface of the substrate and intersecting the first direction, and wherein the semiconductor device further comprises a fence pattern (e.g., 410, Figs. 26-27; Fig. 23) that is disposed between and separates ones of the plurality of lower contact plugs neighboring in the second direction (e.g., Figs. 26-27; Fig. 23).
Regarding claim 9, Kim ‘873 teaches the semiconductor device according to claim 8, wherein the fence pattern contacts the spacer structure (e.g., Fig. 27).
Regarding claim 12, Kim ‘873 teaches the semiconductor device according to claim 1, further comprising: an upper contact plug (e.g., 465 (not labeled) that are disposed on 450, Fig. 27; Fig. 24) on the lower contact plug; and a capacitor (e.g., 570, Fig. 27) on the upper contact plug.
Regarding claim 13, Kim ‘873 teaches the semiconductor device according to claim 1, wherein a slope of the layer of the spacer structure changes from a negative value to a positive value at the vertex (e.g., 375, Fig. 27).
Regarding claim 14, Kim ‘873 teaches the semiconductor device according to claim 1, wherein a slope of the layer of the spacer structure non-linearly changes at the vertex (e.g., 375, Fig. 27).
Regarding claim 17, Kim ‘873 teaches a semiconductor device (e.g., Figs. 26-27, the description thereof; also see Figs. 1-25 and the description thereof) comprising:
an active pattern (e.g., 105, Fig. 27) on a substrate (e.g., 100, Fig. 27);
a gate structure (e.g., 160, Fig. 27) in an upper portion of the active pattern;
a bit line structure (e.g., 305, Fig. 27) on the active pattern;
a spacer structure (e.g., 315, 340(520) and/or 375, Fig. 27; [67]) on a sidewall of the bit line structure, the spacer structure comprising an insulating material (e.g., [35], [37], [42]); and
a lower contact plug (e.g., 440 (not labeled) that are disposed in 430, Fig. 27; Fig. 21) on a portion of the active pattern adjacent to the bit line structure, the lower contact plug contacting the spacer structure (e.g., Fig. 27; Fig. 21),
wherein the spacer structure comprises a layer having a vertex at which a slope non- linearly changes (e.g., 375, Fig. 27).
Regarding claim 18, Kim ‘873 teaches the semiconductor device according to claim 17, wherein the spacer structure comprises a first spacer (e.g., 315, Fig. 27), a second spacer (e.g., 340(520), Fig. 27) and a third spacer (e.g., 375, Fig. 27) sequentially stacked on the sidewall of the bit line structure, and wherein the layer having the vertex comprises the third spacer (e.g., Fig. 27).
Regarding claim 19, Kim ‘873 teaches the semiconductor device according to claim 18, wherein an end portion in a vertical direction of the third spacer comprises the vertex (e.g., Fig. 27).
Regarding claim 21, Kim ‘873 teaches the semiconductor device according to claim 18, further comprising a protective spacer (e.g., 340, Fig. 27) which contacts an outer sidewall of the spacer structure and comprises a material resistant to a dry etching process (e.g., silicon oxide of 340 (e.g., [37]) may be resistant to a dry etching process to some extent depending on various/different operation conditions of a dry etching process; Applicant did not specifically claim what material the protective spacer is composed of, in what conditions the dry etching process is performed, and the like).
Regarding claim 23, Kim ‘873 teaches the semiconductor device according to claim 17, wherein the bit line structure (e.g., 305, Fig. 26-27) is one of a plurality of bit line structures spaced apart from each other in a first direction (e.g., 1st direction, Figs. 26-27), and the lower contact plug (e.g., 440, (not labeled) that are disposed in 430, Fig. 27; Fig. 21) is one of a plurality of lower contact plugs spaced apart from each other in a second direction (e.g., 2nd direction, Figs. 26-27) substantially parallel to an upper surface of the substrate and intersecting the first direction, and wherein the semiconductor device further comprises a fence pattern (e.g., 410, Figs. 26-27; Fig. 23) that is disposed between and separates ones of the plurality of lower contact plugs neighboring in the second direction (e.g., Figs. 26-27; Fig. 23).
Regarding claim 24, Kim ‘873 teaches the semiconductor device according to claim 23, wherein the fence pattern contacts the spacer structure (e.g., Fig. 27).
Regarding claim 27, Kim ‘873 teaches the semiconductor device according to claim 17, wherein a slope of the layer of the spacer structure changes from a negative value to a positive value at the vertex (e.g., 375, Fig. 27).
Regarding claim 30, Kim ‘873 teaches a semiconductor device (e.g., Figs. 26-27, the description thereof; also see Figs. 1-25 and the description thereof) comprising:
active patterns (e.g., 105, Figs. 26-27) on a substrate (e.g., 100, Fig. 27), the active patterns disposed in first and second directions (e.g., 1st direction, 2nd direction, Figs. 26-27) substantially parallel to an upper surface of the substrate and substantially perpendicular to each other;
an isolation pattern (e.g., 110, Figs. 26-27) covering sidewalls of the active patterns;
gate structures (e.g., 160, Figs. 26-27) spaced apart from each other in the second direction, each of the gate structures formed in upper portions of the active patterns and the isolation pattern and extending in the first direction;
bit line structures (e.g., 305, Figs. 26-27) spaced apart from each other in the first direction, each of the bit line structures being on central portions of ones of the active patterns arranged in the second direction and extending in the second direction (e.g., Figs. 26-27);
a spacer structure (e.g., 315, 340(520), 375, Fig. 27; [67]) on a sidewall in the first direction of each of the bit line structures, the spacer structure comprising first, second and third spacers (e.g., 315, 340(520), 375, Fig. 27) sequentially stacked in the first direction; and
a contact plug structure (e.g., 440 (not labeled) that are disposed in 430, Fig. 27; Fig. 21; 465 (not labeled) that are disposed on 450, Fig. 27; Fig. 24) on each of end portions of each of the active patterns, the contact plug comprising a lower contact plug (e.g., 440 (not labeled) that are disposed in 430, Fig. 27; Fig. 21) and an upper contact plug (e.g., 465 (not labeled) that are disposed on 450, Fig. 27; Fig. 24) sequentially stacked in a vertical direction substantially perpendicular to an upper surface of the substrate,
wherein the third spacer (e.g., 375, Fig. 27) comprises two curves and a vertex disposed between and contacting the two curves (e.g., Fig. 27).
Regarding claim 31, Kim ‘873 teaches the semiconductor device according to claim 30, wherein an end portion in the vertical direction of the third spacer comprises the two curves and the vertex (e.g., 375, Fig. 27).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 22 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 2019/0206873 (Kim ‘873) in view of Kim et al. US 2022/0085026 (Kim ‘026).
Regarding claim 7, Kim ‘873 teaches the semiconductor device according to claim 6 as discussed above.
Kim ‘873 does not explicitly teach the protective spacer comprises at least one of titanium nitride (TiN), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN).
Kim ‘026 teaches the protective spacer comprises at least one of titanium nitride (TiN), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN) (e.g., 460, [43]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim ‘873 to include the protective spacer comprises at least one of titanium nitride (TiN), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN) as suggested by Kim ‘026 for the purpose of reducing the material diffusion between the contact plugs (e.g., Kim ‘026, [39]), thereby enhancing the device performance for example.
Regarding claim 22, Kim ‘873 teaches the semiconductor device according to claim 21 as discussed above.
Kim ‘873 does not explicitly teach wherein the protective spacer comprises at least one of titanium nitride (TiN), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN).
Kim ‘026 teaches the protective spacer comprises at least one of titanium nitride (TiN), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN) (e.g., 460, [43]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim ‘873 to include wherein the protective spacer comprises at least one of titanium nitride (TiN), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN) as suggested by Kim ‘026 for the purpose of reducing the material diffusion between the contact plugs (e.g., Kim ‘026, [39]), thereby enhancing the device performance for example.
Conclusion
The art made of record and not applied to the rejection is considered pertinent to applicant's disclosure. It is cited primarily to show inventions relevant to the examination of the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BO B JANG/Primary Examiner, Art Unit 2818 January 10, 2026