DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings filed on April 27, 2026 are acceptable.
Claim Objections
The listing of claims is objected to because of the following informality:
After claim 31, “32 – 72. (canceled).” is missing.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-9, 12, 14, 17-19, 21-24, 30 and 31 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Lee et al. US 2021/0408004.
Regarding claim 1, Lee teaches a semiconductor device (e.g., Fig. 12, [109]-[112]; also see Figs. 1-6 that are closely related to Fig. 12 and the descriptions thereof for additional details, [105]; Fig. 12 in association with Figs. 1-6 is thus used in rejection) comprising:
an active pattern (e.g., ACT including 103, Fig. 12; Fig. 1) on a substrate (e.g., 100, Fig. 12);
a gate structure (e.g., 110 including 112 (WL), Fig. 5, [44]; Fig. 1) in an upper portion of the active pattern;
a bit line structure (e.g., 140, Fig. 12) on the active pattern;
a spacer structure (e.g., 151, Fig. 12) on a sidewall of the bit line structure, the spacer structure comprising an insulating material (e.g., [111]); and
a lower contact plug (e.g., 120, Fig. 12) on a portion of the active pattern adjacent to the bit line structure, the lower contact plug contacting the spacer structure (e.g., Fig. 12),
wherein the spacer structure comprises a layer of which an outer surface (e.g., outer surface of 151a; see the annotated Fig. 12 below) has at least two curves and a vertex (e.g., vertex; see the annotated Fig. 12 below) disposed between and contacting the two curves, and
wherein the layer has an inner surface (e.g., inner surface of 151a; see the annotated Fig. 12 below) facing the bit line structure and the outer surface opposite to the inner surface.
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Annotated Fig. 12 of Lee
Regarding claim 2, Lee teaches the semiconductor device according to claim 1, wherein the spacer structure comprises a first spacer (e.g., 151c, Fig. 12), a second spacer (e.g., 151b, Fig. 12) and a third spacer (e.g., 151a, Fig. 12) sequentially stacked on the sidewall of the bit line structure, and wherein the layer having the two curves and the vertex forms the third spacer (e.g., Fig. 12).
Regarding claim 3, Lee teaches the semiconductor device according to claim 2, wherein the vertex is at a lower end portion of the layer below a middle level of the bit line structure along a vertical direction which is substantially perpendicular to an upper surface of the substrate (e.g., see the annotated Fig. 12 above).
Regarding claim 6, Lee teaches the semiconductor device according to claim 1, further comprising a protective spacer (e.g., 152a, Fig. 12) which contacts the outer surface of the layer of the spacer structure and comprises a material resistant to a dry etching process (e.g., silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), [63]).
Regarding claim 7, Lee teaches he semiconductor device according to claim 6, the protective spacer comprises at least one of titanium nitride (TiN), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN) (e.g., [63]).
Regarding claim 8, Lee teaches the semiconductor device according to claim 1, wherein the bit line structure is one of a plurality of bit line structures (e.g., 140, Fig. 12; Fig. 1) spaced apart from each other in a first direction (e.g., D1, Fig. 1), and the lower contact plug is one of a plurality of lower contact plugs (e.g., 120, Fig. 12; Fig. 1, Fig. 5) spaced apart from each other in a second direction (e.g., D2, Fig. 1) substantially parallel to the upper surface of the substrate and intersecting the first direction, and wherein the semiconductor device further comprises a fence pattern (e.g., 170, Fig. 5; Fig. 1) that is disposed between and separates ones of the plurality of lower contact plugs neighboring in the second direction.
Regarding claim 9, Lee teaches the semiconductor device according to claim 8, wherein the fence pattern contacts the spacer structure (e.g., 170 contacts 151 via intervening layer(s) such as 120, Fig. 5, Fig. 12).
Regarding claim 12, Lee teaches the semiconductor device according to claim 1, further comprising: an upper contact plug (e.g., 160, Fig. 12) on the lower contact plug; and a capacitor (e.g., 190, Fig. 12) on the upper contact plug.
Regarding claim 14, Lee teaches the semiconductor device according to claim 1, wherein a slope of the outer surface of the layer of the spacer structure non-linearly changes at the vertex (e.g., see the annotated Fig. 12 above).
Regarding claim 17, Lee teaches a semiconductor device (e.g., Fig. 12, [109]-[112]; also see Figs. 1-6 that are closely related to Fig. 12 and the descriptions thereof for additional details, [105]; Fig. 12 in association with Figs. 1-6 is thus used in rejection) comprising:
an active pattern (e.g., ACT including 103, Fig. 12; Fig. 1) on a substrate (e.g., 100, Fig. 12);
a gate structure (e.g., 110 including 112 (WL), Fig. 5, [44]; Fig. 1) in an upper portion of the active pattern;
a bit line structure (e.g., 140, Fig. 12) on the active pattern;
a spacer structure (e.g., 151, Fig. 12) on a sidewall of the bit line structure, the spacer structure comprising an insulating material (e.g., [111]); and
a lower contact plug (e.g., 120, Fig. 12) on a portion of the active pattern adjacent to the bit line structure, the lower contact plug contacting the spacer structure (e.g., Fig. 12),
wherein the spacer structure comprises a layer of which an outer surface (e.g., outer surface of 151a; see the annotated Fig. 12 above) has a vertex (e.g., vertex; see the annotated Fig. 12 above) at which a slope non-linearly changes,
wherein the layer has an inner surface (e.g., inner surface of 151a; see the annotated Fig. 12 above) facing the bit line structure and the outer surface opposite to the inner surface, and
wherein the vertex is at a level lower than an upper surface of the lower contact plug (e.g., see the annotated Fig. 12 above).
Regarding claim 18, Lee teaches the semiconductor device according to claim 17, wherein the spacer structure comprises (e.g., 151c, Fig. 12), a second spacer (e.g., 151b, Fig. 12) and a third spacer (e.g., 151a, Fig. 12) sequentially stacked on the sidewall of the bit line structure, and wherein the layer having the vertex forms the third spacer (e.g., Fig. 12).
Regarding claim 19, Lee teaches the semiconductor device according to claim 18, wherein the vertex is at a lower end portion of the layer below a middle level of the bit line structure along a vertical direction which is substantially perpendicular to an upper surface of the substrate (e.g., see the annotated Fig. 12 above).
Regarding claim 21, Lee teaches the semiconductor device according to claim 18, further comprising a protective spacer (e.g., 152a, Fig. 12) which contacts the outer surface of the layer of the spacer structure and comprises a material resistant to a dry etching process process (e.g., silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), [63]).
Regarding claim 22, Lee teaches the semiconductor device according to claim 21, wherein the protective spacer comprises at least one of titanium nitride (TiN), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN) (e.g., [63]).
Regarding claim 23, Lee teaches the semiconductor device according to claim 17, wherein the bit line structure is one of a plurality of bit line structures (e.g., 140, Fig. 12; Fig. 1) spaced apart from each other in a first direction (e.g., D1, Fig. 1), and the lower contact plug is one of a plurality of lower contact plugs (e.g., 120, Fig. 12; Fig. 1, Fig. 5) spaced apart from each other in a second direction (e.g., D2, Fig. 1) substantially parallel to an upper surface of the substrate and intersecting the first direction, and wherein the semiconductor device further comprises a fence pattern (e.g., 170, Fig. 5; Fig. 1) that is disposed between and separates ones of the plurality of lower contact plugs neighboring in the second direction.
Regarding claim 24, Lee teaches the semiconductor device according to claim 23, wherein the fence pattern contacts the spacer structure (e.g., 170 contacts 151 via intervening layer(s) such as 120, Fig. 5, Fig. 12).
Regarding claim 30, Lee teaches a semiconductor device (e.g., Fig. 12, [109]-[112]; also see Figs. 1-6 that are closely related to Fig. 12 and the descriptions thereof for additional details, [105]; Fig. 12 in association with Figs. 1-6 is thus used in rejection) comprising:
active patterns (e.g., ACT including 103, Fig. 12; Fig. 1) on a substrate (e.g., 100, Fig. 12), the active patterns disposed in first and second directions (e.g., D1, D2, Fig. 12; Fig. 1) substantially parallel to an upper surface of the substrate and substantially perpendicular to each other;
an isolation pattern (e.g., 105, Fig. 12) covering sidewalls of the active patterns;
gate structures (e.g., 110 including 112 (WL), Fig. 5, [44]; Fig. 1) spaced apart from each other in the second direction, each of the gate structures formed in upper portions of the active patterns and the isolation pattern and extending in the first direction;
bit line structures (e.g., 140, Fig. 12) spaced apart from each other in the first direction, each of the bit line structures being on central portions of ones of the active patterns arranged in the second direction and extending in the second direction (e.g., Fig. 12; Fig. 1);
a spacer structure (e.g., 151, Fig. 12) on a sidewall in the first direction of each of the bit line structures, the spacer structure comprising first, second and third spacers (e.g., 151a, 151b, 151c, Fig. 12) sequentially stacked in the first direction; and
a contact plug structure (e.g., 120, 160, Fig. 12) on each of end portions of each of the active patterns, the contact plug comprising a lower contact plug (e.g., 120, Fig. 12) and an upper contact plug (e.g., 160, Fig. 12) sequentially stacked in a vertical direction substantially perpendicular to the upper surface of the substrate,
wherein an outer surface of the third spacer (e.g., outer surface of 151a; see the annotated Fig. 12 above) comprises two curves and a vertex (e.g., vertex; see the annotated Fig. 12 above) disposed between and contacting the two curves, and
wherein the third spacer has an inner surface (e.g., inner surface of 151a; see the annotated Fig. 12 above) facing the bit line structure and the outer surface opposite to the inner surface.
Regarding claim 31, Lee teaches the semiconductor device according to claim 30, wherein the vertex is at a lower end portion of the third spacer below a middle level of the bit line structure along a vertical direction which is substantially perpendicular to the upper surface of the substrate (e.g., see the annotated Fig. 12 above).
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 27 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed on April 27, 2026 have been fully considered but are moot in view of the new ground(s) of rejection as stated above.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a) . Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a) .
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
If applicant should desire to file an amendment, entry of a proposed amendment after final rejection cannot be made as a matter of right unless it merely cancels claims or complies with a formal requirement made earlier. Amendments touching the merits of the application which otherwise might not be proper may be admitted upon a showing a good and sufficient reasons why they are necessary and why they were not presented earlier.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BO B JANG/Primary Examiner, Art Unit 2818 May 12, 2026
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