Prosecution Insights
Last updated: July 05, 2026
Application No. 18/388,433

SEMICONDUCTOR DEVICES, THREE-DIMENSIONAL MEMORY DEVICES, AND METHODS FOR FORMING THE SAME

Non-Final OA §102
Filed
Nov 09, 2023
Priority
Nov 02, 2023 — CN 202311456332.6
Examiner
DIAZ, JOSE R
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Yangtze Memory Technologies Co., Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
815 granted / 940 resolved
+18.7% vs TC avg
Moderate +8% lift
Without
With
+7.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
18 currently pending
Career history
967
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
56.1%
+16.1% vs TC avg
§102
18.8%
-21.2% vs TC avg
§112
3.2%
-36.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 940 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 11-12, and 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 11315935). Regarding claim 1, Park discloses a semiconductor device, comprising: a semiconductor layer (10) [Figs. 2-3 and 9-10]; a stack structure over the semiconductor layer (10) and comprising alternating first layers (24/26) and first dielectric layers (22), wherein the stack structure comprises a first portion (CNR/DCH) and a second portion (CAR1/CAR2/SR) adjacent to the first portion, the first layers (24) of the first portion comprise second dielectric layers (24), and the first layers (26) of the second portion (CAR1/CAR2/SR) comprise conductive layers (26) [Figs. 3 and 9-10, and col. 6, lines 1-32]; a first contact structure (CNT) extending through the first portion and the semiconductor layer (10) [Fig. 9-10]; and a second contact structure (DCH) extending through a part of the first portion and connecting (.e.g. joining together) with one of the conductive layers (26) [Figs. 3 and 9-10]. Regarding claim 11, Park discloses channel structures (CH) extending through the second portion into the semiconductor layer (10) [Figs. 3 and 10]. Regarding claim 12, Park discloses wherein, in a vertical direction, a length of the first contact structure (CNT) is greater than a length of the channel structures (CH) [Fig. 10]. Regarding claim 14, Park discloses a peripheral circuit (P) connected with the first contact structure (CNT) [Figs. 1 and 10]. Regarding claim 15, Park discloses a first connection layer (PAD1) and a second connection layer (PAD2), the first connection layer (PAD1) connected with the first contact structure (CNT), the second connection layer (PAD2) connected with the peripheral circuit (P) [Fig. 10], wherein the first connection layer (PAD1) is bonded with the second connection layer (PAD2) [Fig. 10 and col. 10, lines 27-31]. Regarding claim 16, Park discloses wherein the peripheral circuit (P) is disposed under the stack structure (C), and the first contact structure (CNT) extends through the semiconductor layer (10) to connect with the peripheral circuit (P) [Fig. 9]. Allowable Subject Matter Claims 17-20 are allowed. Claims 2-10 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lu et al. (US 2019/0067314) discloses a stack structure comprising alternating first layers and first dielectric layers (232/234) [Fig. 2]. Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Jose R Diaz/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Nov 09, 2023
Application Filed
Apr 20, 2026
Non-Final Rejection mailed — §102
Jun 18, 2026
Interview Requested
Jul 01, 2026
Applicant Interview (Telephonic)
Jul 01, 2026
Examiner Interview Summary

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
94%
With Interview (+7.7%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 940 resolved cases by this examiner. Grant probability derived from career allowance rate.

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