Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the patterned layer as taught in claims 10, 11, 16, and 17 and the hybrid bonding with the new substrate wafer as taught in claims 9 and 19 must be shown or the features canceled from the claims. No new matter should be entered.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “106” has been used to designate both the second semiconductor layer and the overlying patterned layer. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are also objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign mentioned in the description: 118.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-19 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 11 describes applying a planarizing layer on top of a patterned layer, which is not described in the specifications.
Claims 12-19 are dependent on claim 11 and thus rejected.
Claims 10-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 10, the phrase “patterned layer” renders the claim because the claim includes elements not actually disclosed (those encompassed by “patterned layer”), thereby rendering the scope of the claim unascertainable. It should be noted that “patterned layer” is a generic term for any kind of layer with any kind of pattern, for example a doping pattern or a marking pattern. The scope of the claim is unclear, and therefore the term is indefinite. For examination purpose, the phrase “patterned layer” has been construed to cover any kind of pattern marking on a portion of the structure.
Claims 11-19 are dependent on claim 11 and thus rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 10, and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 10510668 B1).
Regarding claim 1, FIG. 1C of Chen et al. teaches a method for manufacturing semiconductor packages, comprising:
providing a silicon on insulator (SOI) substrate (210; FIG. 1C; column 2, lines 52-54) having:
a first semiconductor region (210; FIG. 1C; lines 52-54),
a buried oxide layer (230; FIG. 1C; column 3, lines 14-15) over the first semiconductor region, and
a second semiconductor region (300, 304; FIC. 1C; column 6, lines 10-17) over the buried oxide layer, the second semiconductor region having a plurality of recesses (R; FIG. 1C; lines 10-17) exposing the underlying buried oxide layer, each recess having a shape and size configured to accommodate a semiconductor die (100; FIG. 1C; column 6, lines 38-40); and
bonding a plurality of semiconductor dies to the buried oxide through the plurality of recesses (column 2, lines 44-47).
Regarding claim 2, FIG. 1C of Chen et al. teaches the method of claim 1, further comprising forming a planarizing layer (302; FIG. 1C; column 6, lines 38-41) over the second semiconductor region (300, 304; FIC. 1C; column 6, lines 10-17) and the semiconductor dies (100; FIG. 1C; column 6, lines 38-40).
Regarding claim 10, as best understood under the 112(b) issue identified above, FIG. 1C and FIG. 1F of Chen et al. teaches a method for manufacturing semiconductor packages, comprising:
providing a silicon on insulator (SOI) substrate (210; FIG. 1C; column 2, lines 52-54) having:
a first semiconductor region (210; FIG. 1C; lines 52-54),
a buried oxide layer (230; FIG. 1C; column 3, lines 14-15) over the first semiconductor region, and
a patterned layer (410; FIC. 1F; column 6, lines 10-17) over the buried oxide layer, the second semiconductor region having a plurality of recesses (R; FIG. 1C; lines 10-17) exposing the underlying buried oxide layer, each recess having a shape and size configured to accommodate a semiconductor die (100; FIG. 1C; column 6, lines 38-40); and
bonding a plurality of semiconductor dies to the buried oxide through the plurality of recesses (column 2, lines 44-47).
Regarding claim 11, as best understood under the 112(b) issue identified above, FIG. 1C of Chen et al. teaches the method of claim 10, further comprising forming a planarizing layer (302; FIG. 1C; column 6, lines 38-41) over the patterned layer (230; FIC. 1C; column 3, lines 17-21) (this dielectric layer is also a patterned layer) and the semiconductor dies (100; FIG. 1C; column 6, lines 38-40).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3, 4 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Blanchard et al. (US 9355853 B2).
Regarding claim 3, Chen et al. teaches the method of claim 2, further comprising performing a chemical mechanical polish (CMP) process (column 6, lines 49-51) to the planarizing layer (302; FIG. 1C; column 6, lines 38-41). Chen et al. does not teach doing so to reduce surface variation of the planarizing layer (instead removing it outright).
Blanchard et al. teaches the top surface is preferably planarized, e.g. by chemical-mechanical polishing (CMP), before being bonded to the high-temperature handle wafer (column 9, lines 49-53).
Chen et al. and Blanchard et al. are considered analogous to the claimed invention in that they involve semiconductor structures with oxide layers. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to reduce surface variation of the planarizing layer. This allows to planarized layer to be prepared for bonding (column 9, lines 49-53).
Regarding claim 4, the combination of Chen et al. in view of Blanchard et al. teaches the method of claim 3. Chen et al. does not teach the method further comprising bonding a handle wafer to the planarizing layer after performing the CMP process.
Blanchard et al. teaches the top surface of the protective layer is preferably planarized, e.g. by chemical-mechanical polishing (CMP), before being bonded to the high-temperature handle wafer (column 9, lines 49-53).
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have a handle wafer bonded to a planarized layer after a CMP process. This placement allows for the wafer to be removed later (column 6, line 33).
Regarding claim 12, as best understood under the 112(b) issue identified above, Chen et al. teaches the method of claim 11, further comprising performing a planarizing process (column 6, lines 49-51) to the planarizing layer (302; FIG. 1C; column 6, lines 38-41). Chen et al. does not teach doing so to reduce surface variation of the planarizing layer (instead removing it outright).
Blanchard et al. teaches the top surface is preferably planarized, e.g. by chemical-mechanical polishing (CMP), before being bonded to the high-temperature handle wafer (column 9, lines 49-53).
Chen et al. and Blanchard et al. are considered analogous to the claimed invention in that they involve semiconductor structures with oxide layers. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to reduce surface variation of the planarizing layer. This allows to planarized layer to be prepared for bonding (column 9, lines 49-53).
Regarding claim 13, as best understood under the 112(b) issue identified above, the combination of Chen et al. in view of Blanchard et al. teaches the method of claim 11. Chen et al. further teaches the method wherein the planarizing process is implemented using a chemical mechanical polish (CMP) process (column 6, lines 49-51).
Regarding claim 14, as best understood under the 112(b) issue identified above, Chen et al. teaches the method of claim 13. Chen et al. does not teach the method further comprising bonding a handle wafer to the planarizing layer after performing the CMP process.
Blanchard et al. teaches the top surface of the protective layer is preferably planarized, e.g. by chemical-mechanical polishing (CMP), before being bonded to the high-temperature handle wafer (column 9, lines 49-53).
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have a handle wafer bonded to a planarized layer after a CMP process. This placement allows for the wafer to be removed later (column 6, line 33).
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. and Blanchard et al. as applied to claims 4 and 14 above, and further in view of Daneman et al. (US 20140239353 A1).
Regarding claim 5, the combination of Chen et al. and Blanchard et al. teaches the method of claim 4. Neither Chen et al. nor Blanchard et al. teach the method further comprising separating the first semiconductor region from the buried oxide layer after bonding the handle wafer to the planarizing layer.
FIG. 6B and FIG. 6C of Daneman et al. teaches a handle wafer (600; FIG. 6B; paragraph 0049) is bonded with the MEMS substrate and the silicon substrate (606; FIG. 6B; paragraph 0049) is shown to be removed from a silicon oxide layer (604; FIG. 6C; paragraph 0049).
Chen et al., Blanchard et al, and Daneman et al. are all analogous to the claimed invention in that they involve semiconductor structures with oxide layers. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to separate the first semiconductor region from the buried oxide layer after bonding the handle wafer to the planarizing layer. This allows for the oxide layer etched, modified, and/or removed as well (paragraph 0049).
Regarding claim 15, as best understood under the 112(b) issue identified above, the combination of Chen et al. and Blanchard et al. teaches the method of claim 14. Neither Chen et al. nor Blanchard et al. teach the method further comprising separating the first semiconductor region from the buried oxide layer after bonding the handle wafer to the planarizing layer.
FIG. 6B, and FIG. 6C of Daneman et al. teach a handle wafer (600; FIG. 6B; paragraph 0049) is bonded with the MEMS substrate and the silicon substrate (606; FIG. 6B; paragraph 0049) is shown to be removed from a silicon oxide layer (604; FIG. 6C; paragraph 0049).
Chen et al., Blanchard et al, and Daneman et al. are all analogous to the claimed invention in that they involve semiconductor structures with oxide layers. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to separate the first semiconductor region from the buried oxide layer after bonding the handle wafer to the planarizing layer. This allows for the oxide layer etched, modified, and/or removed as well (paragraph 0049).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Blanchard et al. as applied to claims 4 and 14above, and further in view of Bourdelle et al. (US 20110287571 A1).
Regarding claim 6, the combination of Chen et al. in view of Blanchard et al. teaches the method of claim 4. Neither Chen et al. nor Blanchard et al. teach the method further comprising separating the first semiconductor region after bonding the handle wafer to the planarizing layer by removing the buried oxide from the second semiconductor region and the semiconductor dies.
FIG. 1 of Bourdelle et al. teaches a base substrate (5; FIG. 1; paragraph 0038) of the first substrate and a dielectric oxide layer (7; FIG. 1; paragraph 0038) are completely removed so that a semiconductor layer (3; FIG. 1; paragraph 0038), electronic device structures (9a, 9b, 9c; FIG. 1; paragraph 0034), and a bonded standard silicon wafer (13; FIG. 1; paragraph 0036) remain.
Chen et al., Blanchard et al, and Bourdelle et al. are all analogous to the claimed invention in that they involve semiconductor structures with oxide layers. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to separate the first semiconductor region after bonding the handle wafer to the planarizing layer by removing the buried oxide from the second semiconductor region and the semiconductor dies. This allows for a new layer to be placed below the second semiconductor layer (paragraph 0042).
Claims 7-9 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Blanchard et al. and further in view of Daneman et al. as applied to claims 5 and 15 above, and further in view of Bourdelle et al. and Yeh et al. (US-10475762-B1).
Regarding claim 7, the combination of Chen et al. in view of Blanchard et al. and in further view of Daneman et al teaches the method of claim 5. Neither Chen et al., Blanchard et al., nor Daneman et al. teach the method wherein after separating the first semiconductor region from the buried oxide layer, the method further comprises removing the buried oxide region to expose the semiconductor dies and the second semiconductor region.
FIG. 1 of Bourdelle et al. teaches a base substrate (5; FIG. 1; paragraph 0038) of the first substrate and a dielectric oxide layer (7; FIG. 1; paragraph 0038) are completely removed so that a semiconductor layer (3; FIG. 1; paragraph 0038), electronic device structures (9a, 9b, 9c; FIG. 1; paragraph 0034), and a bonded standard silicon wafer (13; FIG. 1; paragraph 0036) remain. Bourdelle et al. does not teach the semiconductor dies or any equivalent being exposed.
FIG. 1C of Yeh et al. teaches the removal process of an oxide dielectric layer (33; FIG. 1C; column 5, lines 36-41) is stopped until the top surface of the die (28; FIG. 1C; column 6, lines 29-32) is exposed while also exposing upper semiconductor substrate (19, FIG. 1C; column 4, lines 6-8).
Chen et al., Blanchard et al., Daneman et al., Bourdelle et al., and Yeh et al. are all analogous to the claimed invention in that they involve semiconductor structures with oxide layers. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to expose the semiconductor dies and the second semiconductor region. This allows structures connected to the dies to be formed (column 7, line 62-63).
Regarding claim 8 the combination of Chen et al. in view of Blanchard et al., Daneman et al., Bourdelle et al., and Yeh et al. teaches the method of claim 7. Chen et al., Blanchard et al., Daneman et al., and Bourdelle et al. do not teach the method wherein exposing the semiconductor dies exposes hybrid bonding surfaces of the dies.
FIG. 2 of Yeh et al. teaches upper dies (128; FIG. 2; column 9, lines 12-14) are bonded to the exposed part of the prior dies (28; FIG. 2; column 9, lines 12-14) through a hybrid bonding process.
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to expose hybrid bonding surfaces of the dies. This allows objects to be bonded to the die surface (column 9, lines 12-14).
Regarding claim 9 the combination of Chen et al. in view of Blanchard et al., Daneman et al., Bourdelle et al., and Yeh et al. teaches the method of claim 8. Chen et al., Blanchard et al., Daneman et al., and Bourdelle et al. do not teach the method further comprising performing a hybrid bonding process to physically bond and electrically connect the semiconductor dies to one or more functional substrates.
FIG. 1A of Yeh et al. teaches the dies (28; FIG. 1A; column 5, lines 4-5) are bonded to the wafer (18; FIG. 1A; column 5, lines 4-5) through a hybrid bonding process, with the wafer’s conductive features (14; FIG. 1A; column 5, lines 8-10) and the die’s conductive features (25; FIG. 1A; column 5, lines 8-10) are bonded by metal-to-metal bonding, and the wafer’s dielectric layer (13; FIG. 1A; column 5, lines 10-12) and the die’s dielectric layer (24; FIG. 1A; column 5, lines 10-12) are bonded by dielectric-to-dielectric bonding.
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to perform a hybrid bonding process to physically bond and electrically connect the semiconductor dies to one or more functional substrates. This is a known bonding method (column 5, lines 8-10).
Regarding claim 16, as best understood under the 112(b) issue identified above, the combination of Chen et al. in view of Blanchard et al. teaches the method of claim 14. Neither Chen et al. nor Blanchard et al. teach the method further comprising separating the first semiconductor region after bonding the handle wafer to the planarizing layer by removing the buried oxide from the patterned layer and the semiconductor dies.
FIG. 1 of Bourdelle et al. teaches a base substrate (5; FIG. 1; paragraph 0038) of the first substrate and a dielectric oxide layer (7; FIG. 1; paragraph 0038) are completely removed so that a semiconductor layer (3; FIG. 1; paragraph 0038), electronic device structures (9a, 9b, 9c; FIG. 1; paragraph 0034), and a bonded standard silicon wafer (13; FIG. 1; paragraph 0036) remain. Bourdelle does not teach the oxide layer being separated from a patterned layer.
FIG. 1C of Yeh et al. teaches the removal process of an oxide dielectric layer (33; FIG. 1C; column 5, lines 36-41) is stopped until the top surface of the die (28; FIG. 1C; column 6, lines 29-32) is exposed while also exposing upper semiconductor substrate (19, FIG. 1C; column 4, lines 6-8), and patterned photo resist mask layer (PR; FIG. 1C; column 6, lines 4-10).
Chen et al., Blanchard et al, Bourdelle et al., and Yeh et al. are all analogous to the claimed invention in that they involve semiconductor structures with oxide layers. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to separate the first semiconductor region after bonding the handle wafer to the planarizing layer by removing the buried oxide from the patterned layer and the semiconductor dies. This allows for a new layer to be placed below the patterned layer (Bourdelle et al., paragraph 0042) (Yeh et al., column 7, line 62-63)..
Regarding claim 17, as best understood under the 112(b) issue identified above, the combination of Chen et al. in view of Blanchard et al. and in further view of Daneman et al teaches the method of claim 15. Neither Chen et al., Blanchard et al., nor Daneman et al. teach the method wherein after separating the first semiconductor region from the buried oxide layer, the method further comprises removing the buried oxide region to expose the semiconductor dies and the patterned layer.
FIG. 1 of Bourdelle et al. teaches a base substrate (5; FIG. 1; paragraph 0038) of the first substrate and a dielectric oxide layer (7; FIG. 1; paragraph 0038) are completely removed so that a semiconductor layer (3; FIG. 1; paragraph 0038), electronic device structures (9a, 9b, 9c; FIG. 1; paragraph 0034), and a bonded standard silicon wafer (13; FIG. 1; paragraph 0036) remain. Bourdelle et al. does not teach the semiconductor dies, or any equivalent being exposed.
FIG. 1C of Yeh et al. teaches the removal process of an oxide dielectric layer (33; FIG. 1C; column 5, lines 36-41) is stopped until the top surface of the die (28; FIG. 1C; column 6, lines 29-32) is exposed while also exposing upper semiconductor substrate (19, FIG. 1C; column 4, lines 6-8).
Chen et al., Blanchard et al., Daneman et al., Bourdelle et al., and Yeh et al. are all analogous to the claimed invention in that they involve semiconductor structures with oxide layers. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to expose the semiconductor dies and the second semiconductor region. This allows structures connected to the dies to be formed (column 7, line 62-63).
Regarding claim 18, as best understood under the 112(b) issue identified above, the combination of Chen et al. in view of Blanchard et al., Daneman et al., Bourdelle et al., and Yeh et al. teaches the method of claim 17. Chen et al., Blanchard et al., Daneman et al., and Bourdelle et al. do not teach the method wherein exposing the semiconductor dies exposes hybrid bonding surfaces of the dies.
FIG. 2 of Yeh et al. teaches upper dies (128; FIG. 2; column 9, lines 12-14) are bonded to the exposed part of the prior dies (28; FIG. 2; column 9, lines 12-14) through a hybrid bonding process.
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to expose hybrid bonding surfaces of the dies. This allows objects to be bonded to the die surface (column 9, lines 12-14).
Regarding claim 19, as best understood under the 112(b) issue identified above, the combination of Chen et al. in view of Blanchard et al., Daneman et al., Bourdelle et al., and Yeh et al. teaches the method of claim 18. Chen et al., Blanchard et al., Daneman et al., and Bourdelle et al. do not teach the method further comprising performing a hybrid bonding process to physically bond and electrically connect the semiconductor dies to one or more functional substrates.
FIG. 1A of Yeh et al. teaches the dies (28; FIG. 1A; column 5, lines 4-5) are bonded to the wafer (18; FIG. 1A; column 5, lines 4-5) through a hybrid bonding process, with the wafer’s conductive features (14; FIG. 1A; column 5, lines 8-10) and the die’s conductive features (25; FIG. 1A; column 5, lines 8-10) are bonded by metal-to-metal bonding, and the wafer’s dielectric layer (13; FIG. 1A; column 5, lines 10-12) and the die’s dielectric layer (24; FIG. 1A; column 5, lines 10-12) are bonded by dielectric-to-dielectric bonding.
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to perform a hybrid bonding process to physically bond and electrically connect the semiconductor dies to one or more functional substrates. This is a known bonding method (column 5, lines 8-10).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kanakasabapathy et al. (US 20110248326 A1) concerns a transistor with a substrate with a semiconductor layer and trench regions filled with fin structures. Pinto et al. (US 20100304547 A1) concerns a device and method of reducing residual STI corner defects in a hybrid orientation transistor, including silicon layers and an oxide layer. Cheng et al. (US 9881998 B1) concerns nanosheet FET devices with substrate isolation layers including a semiconductor device including a rare earth oxide layer..
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A VLCEK whose telephone number is (571)272-9665. The examiner can normally be reached Mon-Fri, 9:00 AM -5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.A.V./Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817
Prosecution Insights