DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, and Claims 1-12 in
the reply filed on 02/09/2026 is acknowledged. Claims 13 - 20 are withdrawn from
further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected
invention, there being no allowable generic or linking claim. Election was made without
traverse in the reply filed on 02/09/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/10/2023, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract of the disclosure is objected to because: the phrase “locally curing selectively portions” is unclear and should be replaced with “locally curing selected portions.” A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities:
The paragraph numbering in the specification is written as [001], [002], [003], [004], [005], [006], [007], [008], [009], [0010]; this should be revised to [0001], [0002], [0003], [0004], [0005], [0006], [0007], [0008], [0009], [0010]
Paragraph [0061] on page 15, recites “encapsulant 100” which should be “encapsulant 106”.
Paragraph [0064] on page 15, recites “encapsulant 108” which should be “encapsulant 106”.
Paragraphs [0005], [0013], [0068], and [0087] on pages 1, 2, 16, and 19 respectively, recites “locally curing selectively”; this should be written as “locally curing selected”.
Appropriate correction is required.
Claim Objections
Claims 1, 2, 5, 6, and 11 are objected to because of the following informalities:
Claim 1 recites “by locally curing selectively portions of the encapsulant”; this should be written as “by locally curing selected portions of the encapsulant.”
Claims 2, 6, and 11 use the phrase “in particular” multiple times, which lacks clarity and should be removed.
Claim 5 recites “chips of a common wafer”, which should be revised to “chips of a wafer” to provide proper antecedent basis for “the wafer” as recited in claims 6 and 7.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 8 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Farnworth (US20030090006A1; hereinafter Farnworth) in view of Sato et al. (JP2016146413A; hereinafter Sato).
Regarding Claim 1, Farnworth discloses a method of processing chips (method of processing one or more semiconductor dice 20 on substrate 10, [0045]), the method comprising:
encapsulating mutually spaced chips (semiconductor dice 20) by an encapsulant comprising a locally curable material (encapsulant 60). FIGS. 12, 18, [0066], [0078], [0085].
Farnworth discloses semiconductor dice 20 disposed on substrate 10, spaced from each other and encapsulated by dam structure 56 and/or envelope 48 formed from encapsulant 60 which is a liquid photo-curable polymer.
by locally curing selectively portions of the encapsulant (60) covering at least a portion of the chips (20), without curing other portions of the encapsulant (60) apart from the encapsulated chip sections. FIG. 16 reproduced below, [0077], [0085], [0086]
Farnworth [0077], [0085], [0086] discloses the laser beam 112 cures encapsulant 60 to form layers 90A, 90B, and 90C covering the chips 20.
Farnworth [0077] discloses the laser beam 112 selectively scans and at least partially cures selected locations of the encapsulant 60, indicating only selected portions are irradiated, while other portions of the encapsulant apart from the encapsulated chip sections may not be cured.
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Farnworth: FIG. 16
Farnworth does not disclose “separating the encapsulated chips with the encapsulant into a plurality of encapsulated chip sections.”
In a similar art, Sato discloses a method of manufacturing a semiconductor device [0006].
encapsulating mutually spaced chips (chips CP spaced by distance D1) by an encapsulant (sealing member 30 made of epoxy resin to form a sealing body 3), FIG. 4, [0035], [0036].
Sato [0026], [0032] discloses semiconductor chips CP attached to an adhesive layer 22 comprising a locally curable material such as energy ray-curable resin is mixed with an acrylic pressure-sensitive adhesive and selectively curing portions using localized irradiation (energy beam E), thereby discloses selective localized curing of a curable material.
separating the encapsulated chips with the encapsulant into a plurality of encapsulated chip sections, FIG. 6C reproduced below, [0046].
Sato [0046] discloses sealing body 3 which includes semiconductor chips CP and sealing member 30 is singulated in units of semiconductor chips CP.
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Sato: FIG. 6C
Sato discloses that a method as taught may improve the uniformity and accuracy of the chip spacing thereby enabling reliable singulation and improving manufacturability [0050]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Farnworth’s method to improve enable reliable singulation and improved manufacturability as disclosed by Sato [0050].
Regarding Claim 2, The combination of Farnworth and Sato discloses the method according to claim 1.
Farnworth discloses: wherein the locally curing comprises selectively irradiating, said portions of the encapsulant by irradiation with curing electromagnetic radiation, in particular ultraviolet electromagnetic radiation (encapsulant 60 responsive to UV wavelength range, [0066]), without irradiating said other portions of the encapsulant with said curing electromagnetic radiation. FIG. 16, [0077], [0085], [0086].
Farnworth [0077], [0085], [0086] discloses the laser beam 112 cures encapsulant 60 to form layers 90A, 90B, and 90C covering the chips 20.
Farnworth [0077] discloses the laser beam 112 selectively scans and at least partially cures selected locations of the encapsulant 60, indicating only selected portions are irradiated, while other portions of the encapsulant apart from the encapsulated chip sections may not be cured.
Farnworth does not disclose “wherein the locally curing comprises selectively irradiating, in particular using a mask”.
Sato discloses: wherein the locally curing comprises selectively irradiating, in particular using a mask (irradiating of energy-beam E through first mask 51 having the opening 51A and a blocking portion 51B), FIG. 9A, [0058].
Sato discloses that a method as taught using a mask may improve the precision of selective curing of the encapsulant, thereby improving manufacturability [0050], [0058]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Farnworth’s method to improve the precision of selective curing of the encapsulant, thereby improving manufacturability as disclosed by Sato [0050], [0058].
Regarding Claim 3, The combination of Farnworth and Sato discloses the method according to claim 1.
Farnworth discloses: wherein the method comprises applying said encapsulant by attaching a solid encapsulant layer to the mutually spaced chips, or
by coating the mutually spaced chips (20) by an encapsulant liquid (60), FIG. 15, [0085].
Farnworth [0085] discloses the mutually spaced semiconductor dice 20 are coated with an encapsulant liquid resin 60.
Regarding Claim 4, The combination of Farnworth and Sato discloses the method according to claim 1.
Farnworth discloses locally curing selectively portions of the encapsulant covering at least a portion of the chips, without curing other portions of the encapsulant apart from the encapsulated chip sections. FIG. 16, [0077], [0085], [0086]
Farnworth [0077], [0085], [0086] discloses the laser beam 112 cures encapsulant 60 to form layers 90A, 90B, and 90C covering the chips 20.
Farnworth [0077] discloses the laser beam 112 selectively scans and at least partially cures selected locations of the encapsulant 60, indicating only selected portions are irradiated, while other portions of the encapsulant apart from the encapsulated chip sections may not be cured.
Farnworth does not disclose “wherein the method comprises separating the encapsulated chip sections.”
Sato discloses: wherein the method comprises separating the encapsulated chip sections, FIG. 6C, [0046].
Sato [0046] discloses sealing body 3 which includes semiconductor chips CP and sealing member 30 is singulated in units of semiconductor chips CP.
The combination of Farnworth and Sato discloses: wherein the method comprises separating the encapsulated chip sections (Sato: FIG. 6C, [0046]) at the uncured other portions of the encapsulant (Farnworth: [0077]).
Sato discloses that a method as taught may improve the uniformity and accuracy of the chip spacing thereby enabling reliable singulation and improving manufacturability [0050]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Farnworth’s method to improve enable reliable singulation and improved manufacturability as disclosed by Sato [0050].
Regarding Claim 5, The combination of Farnworth and Sato discloses the method according to claim 1.
Farnworth does not disclose “wherein the method comprises expanding an expansion tape on which the chips of a common wafer are arranged to thereby mutually space the chips.”
Sato discloses: wherein the method comprises expanding an expansion tape (adhesive sheet 20) on which the chips (CP) of a common wafer (W) are arranged to thereby mutually space the chips (space 224 between chips CP), FIGS. 10A, 10B, [0062].
Sato [0062] discloses stretching the second adhesive sheet 20 holding the plurality of semiconductor chips CP to extend the space between the chips, indicating the second adhesive sheet 20 functions as an expansion tape.
Sato discloses that a method as taught may improve the uniformity and accuracy of the chip spacing thereby improving manufacturability [0050]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Farnworth’s method to improve the uniformity and accuracy of the chip spacing thereby improving manufacturability as disclosed by Sato [0050].
Regarding 6, The combination of Farnworth and Sato discloses the method according to claim 5.
Farnworth does not disclose “comprising at least one of the following features:
wherein the method comprises encapsulating the chips on the expanded expansion tape by the encapsulant; and wherein the method comprises expanding the expansion tape so that the chips of the wafer are mutually spaced in two perpendicular spatial directions of a plane of the expansion tape, wherein in particular the method comprises expanding the expansion tape so that the chips of the wafer are mutually spaced by a distance in a range from 20 μm to 150 μm.”
Sato discloses: comprising at least one of the following features:
wherein the method comprises encapsulating the chips (CP) on the expanded expansion tape by the encapsulant (sealing member 30), [0036], [0062]; and
Sato [0062] discloses stretching the second adhesive sheet 20 holding the plurality of semiconductor chips CP to extend the space between the chips, indicating the second adhesive sheet 20 functions as an expansion tape. Sato [0036] discloses the step of sealing the plurality of semiconductor chips CP using the sealing member 30 after the expanding step.
wherein the method comprises expanding the expansion tape so that the chips of the wafer are mutually spaced in two perpendicular spatial directions of a plane of the expansion tape, wherein in particular the method comprises expanding the expansion tape so that the chips of the wafer are mutually spaced by a distance in a range from 20 μm to 150 μm.
Sato discloses that a method as taught may improve the uniformity and accuracy of the chip spacing thereby improving manufacturability [0050]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Farnworth’s method to improve the uniformity and accuracy of the chip spacing thereby improving manufacturability as disclosed by Sato [0050].
Regarding Claim 7, The combination of Farnworth and Sato discloses the method according to claim 5.
Farnworth does not disclose “wherein the method comprises mounting the wafer, when still being integral, on a separation tape, and thereafter separating the chips from the previously integral wafer.”
Sato discloses: wherein the method comprises mounting the wafer (W), when still being integral, on a separation tape (first adhesive sheet 10), and thereafter separating the chips (CP) from the previously integral wafer, [0022], FIG. 1A, 1B.
Sato [0022] discloses mounting an integral semiconductor wafer W on a separation tape (first adhesive sheet 10), and thereafter separating the wafer into a plurality of semiconductor chips CP by dicing.
Sato discloses that a method as taught may improve the uniformity and accuracy of the chip spacing thereby enabling reliable singulation and improving manufacturability [0050]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Farnworth’s method to improve enable reliable singulation and improved manufacturability as disclosed by Sato [0050].
Regarding Claim 8, The combination of Farnworth and Sato discloses the method according to claim 7.
Farnworth does not disclose “wherein the method comprises connecting the separated chips with said expansion tape, and thereafter removing said separation tape.”
Sato discloses: wherein the method comprises connecting the separated chips (CP) with said expansion tape (second adhesive tape 20), and thereafter removing said separation tape (first adhesive tape 10), FIG. 2A, 2B, [0023], [0024], [0031]. Sato discloses transferring and attaching the separated semiconductor chips CP to an expansion tape adhesive sheet 20 and thereafter peeling off the separation tape first adhesive sheet 10.
Sato discloses that a method as taught may improve the uniformity and accuracy of the chip spacing thereby improving manufacturability [0050]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Farnworth’s method to improve the uniformity and accuracy of the chip spacing thereby improving manufacturability as disclosed by Sato [0050].
Regarding Claim 12, The combination of Farnworth and Sato discloses the method according to claim 1.
Farnworth discloses: comprising at least one of the following features:
wherein the encapsulant (60) comprises a photo imaging polymer (photopolymer, [0059]);
wherein the method comprises washing away the uncured other portions of the encapsulant apart from the encapsulated chip sections.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Farnworth in view of Sato, further in view of Fan (US7776649B1; hereinafter Fan).
Regarding Claim 9, The combination of Farnworth and Sato discloses the method according to claim 1.
The combination of Farnworth and Sato does not disclose “wherein the method comprises attaching a release layer to the encapsulant.”
In a similar art, Fan discloses a manufacturing method of wafer level chip scale package, [col. 4, line 62].
Fan discloses: wherein the method comprises attaching a release layer (protection film 30) to the encapsulant (230), FIG. 3E, [col. 5, line 63].
Fan discloses the encapsulant 230 is formed on and adheres to the protection film 30 which functions as a release layer [col. 5, line 63]. The protection film 30 can be subsequently released by reducing its adhesion [col. 5, line 30].
Fan discloses that a method comprising attaching a release layer to the encapsulant to enhance the peeling and removal of the encapsulant without damaging the chips [col. 6, line 17]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Farnworth and Sato’s method to enhance the peeling and removal of the encapsulant without damaging the chips as disclosed by Fan [col. 6, line 17].
Regarding Claim 10, The combination of Farnworth, Sato, and Fan discloses the method according to claim 9.
The combination of Farnworth and Sato does not disclose “wherein the method comprises releasing the encapsulated chip sections from the release layer.”
Fan discloses: wherein the method comprises releasing the encapsulated chip sections (chips 210 with the encapsulation 230) from the release layer (30), FIG. 3F, [col.5, line 30].
Fan discloses that a method comprising attaching a release layer to the encapsulant to enhance the peeling and removal of the encapsulant without damaging the chips [col. 6, line 17]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method to enhance the peeling and removal of the encapsulant without damaging the chips as disclosed by Fan [col. 6, line 17].
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Farnworth in view of Sato, further in view of Fan, still further in view of Emi et al. (JP2020088264A; hereinafter Emi).
Regarding Claim 11, The combination of Farnworth, Sato, and Fan discloses the method according to claim 10.
The combination of Farnworth, Sato, and Fan does not disclose “comprising at least one of the following features: wherein the method comprises treating the release layer and/or the encapsulant, in particular by supplying heat, for promoting release of the encapsulated chip sections from the release layer; wherein the method comprises collecting the encapsulated chip sections released automatically, in particular falling down by the force of gravity, from the release layer; wherein the method comprises releasing all encapsulated chip sections in a common process under the force of gravity and by reducing an attaching force of the release layer, in particular by supplying heat.”
In a similar art, Emi discloses a method of manufacturing a semiconductor device [0001].
Emi discloses: comprising at least one of the following features:
wherein the method comprises treating the release layer (temporary fixing layer 30c) and/or the encapsulant (sealing layer 50), in particular by supplying heat, for promoting release of the encapsulated chip sections (processed semiconductor member 42) from the release layer (30c), [0022], [0101];
Emi [0022], [0101] discloses the temporary fixing layer 30c (release layer) absorbs light and generates heat when irradiated with light and promotes separation of the semiconductor member 42 from the support member 10, thereby promoting release from the temporary fixing layer 30c.
wherein the method comprises collecting the encapsulated chip sections released automatically, in particular falling down by the force of gravity, from the release layer;
wherein the method comprises releasing all encapsulated chip sections in a common process under the force of gravity and by reducing an attaching force of the release layer, in particular by supplying heat.
Emi discloses that a method as taught enables easy separation of the temporarily fixed semiconductor component from the support member [0124]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Farnworth, Sato, and Fan’s method to enable easy separation of the temporarily fixed semiconductor component from the support member as disclosed by Emi [0124].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Krishna J Palaniswamy whose telephone number is (571)272-6239. The examiner can normally be reached Monday - Friday 8:30AM - 5PM EST.
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/Krishna J. Palaniswamy/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899