Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the Response to Election/Requirement filed on 12/08/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/11/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Claims 1-6, and 15-20 in the reply filed on 12/08/2025 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required.
Claim Objections
Claims 6, and 20 are objected to because of the following informalities: Regarding claim 6, in line 2, “a first flip-flop to a fourth flip-flop” appears that it should read as “a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop”. Regarding claim 20, in line 2, “a first flip-flop to a fourth flip-flop” appears that it should read as “a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 4, 6, 15, 17, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US Patent Application Publication US 2018/0004241 A1, hereinafter “Wang”) in view of Diewald et al. (US Patent Application Publication US 2014/0327467 A1, hereinafter “Diewald”).
Regarding claim 1, Wang discloses (see Fig. 1) a direct current to direct current converter (converter comprising 128, 124, 126, 130) comprising: a switcher (comprising 124, 126) which generates an output voltage (Vout) based on an external input voltage (Vin); and a controller (controller portion of 110) which controls the switcher based on a pulse width modulation signal (PWM), wherein the controller controls the converter in a pulse skip mode (PWM) of a low-power mode (see [0026] “while the pulsed skipping mode is used for passive operation of the electronic device (here, in the case where the electronic device is a cellular phone, the passive mode might include an idle state with the display off).”). Wang does not wherein the controller counts a number of switching of the pulse width modulation signal, generates a count value, and determines a short circuit defect when the count value is equal to or greater than a reference count value. However, Diewald teaches (see Fig. 3) wherein the controller (102) counts a number of switching of the pulse width modulation signal (see [0036] “The pulse timing logic 302 may also count the number of pulses 410 occurring with a measurement interval.”), generates a count value, and determines a short circuit defect when the count value is equal to or greater than a reference count value (see [0040] “The error detection logic 306 can also identify an overcurrent condition by determining whether the number of detected pulses in the signal 112 in a predetermined interval exceeds a predetermined maximum number of pulses.”). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the direct current to direct current converter of Wang wherein the controller counts a number of switching of the pulse width modulation signal, generates a count value, and determines a short circuit defect when the count value is equal to or greater than a reference count value, as taught by Diewald, because it can help prevent over current events, i.e. short circuit defect, while operating in Pulse Skipping Mode.
Regarding claim 3, Wang discloses (see Fig. 1) wherein the switcher comprises: a voltage divider (resistor divider connected to Vout) which divides the output voltage and generates a feedback voltage (Vfb); an error amplifier (112) which amplifies a voltage difference between the feedback voltage and a feedback reference voltage (Vref) and outputs a control voltage (Verr); and a comparator (116) which compares the control voltage with a skip reference voltage (Vskip_mode) and outputs a skip control signal (PSM).
Regarding claim 4, Wang discloses (see Fig. 1) wherein the controller skips active pulses of the pulse width modulation signal when the skip control signal is at a relatively high level, and does not skip the active pulses of the pulse width modulation signal when the skip control signal is at a relatively low level (When PSM is high, pulses are skipped in the pulse skipping mode, and when PSM is low, pulses are not skipped. See [0021] “A control signal indicating that pulse skipping mode is to be entered may be generated based upon an error signal and the skipping mode reference signal, using a comparator.”).
Regarding claim 15, Wang discloses (see Fig. 1) a display device (see [0026] “The electronic device 100 may be a cellular phone, a tablet, or any other portable battery powered device.”) comprising: a display panel (i.e. 132, see [0026] “passive operation of the electronic device (here, in the case where the electronic device is a cellular phone, the passive mode might include an idle state with the display off).”); and a direct current to direct current converter (converter comprising 128, 124, 126, 130) which applies an output voltage (Vout) to the display panel, wherein the direct current to direct current converter includes a switcher (comprising 124, 126) which generates the output voltage based on an external input voltage (Vin), and a controller (controller portion of 110) which controls the switcher based on a pulse width modulation signal (PWM), wherein the controller controls the converter in a pulse skip mode (PWM) of a low-power mode (see [0026] “while the pulsed skipping mode is used for passive operation of the electronic device (here, in the case where the electronic device is a cellular phone, the passive mode might include an idle state with the display off).”). Wang does not wherein the controller counts a number of switching of the pulse width modulation signal, generates a count value, and determines a short circuit defect when the count value is equal to or greater than a reference count value. However, Diewald teaches (see Fig. 3) wherein the controller (102) counts a number of switching of the pulse width modulation signal (see [0036] “The pulse timing logic 302 may also count the number of pulses 410 occurring with a measurement interval.”), generates a count value, and determines a short circuit defect when the count value is equal to or greater than a reference count value (see [0040] “The error detection logic 306 can also identify an overcurrent condition by determining whether the number of detected pulses in the signal 112 in a predetermined interval exceeds a predetermined maximum number of pulses.”). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the display device of Wang wherein the controller counts a number of switching of the pulse width modulation signal, generates a count value, and determines a short circuit defect when the count value is equal to or greater than a reference count value, as taught by Diewald, because it can help prevent over current events, i.e. short circuit defect, while operating in Pulse Skipping Mode.
Regarding claim 17, Wang discloses (see Fig. 1) wherein the switcher comprises: a voltage divider (resistor divider connected to Vout) which divides the output voltage and generates a feedback voltage (Vfb); an error amplifier (112) which amplifies a voltage difference between the feedback voltage and a feedback reference voltage (Vref) and outputs a control voltage (Verr); and a comparator (116) which compares the control voltage with a skip reference voltage (Vskip_mode) and outputs a skip control signal (PSM).
Regarding claim 18, Wang discloses (see Fig. 1) wherein the controller skips active pulses of the pulse width modulation signal when the skip control signal is at a relatively high level, and does not skip the active pulses of the pulse width modulation signal when the skip control signal is at a relatively low level (When PSM is high, pulses are skipped in the pulse skipping mode, and when PSM is low, pulses are not skipped. See [0021] “A control signal indicating that pulse skipping mode is to be entered may be generated based upon an error signal and the skipping mode reference signal, using a comparator.”).
Claims 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Diewald, and further in view of Lai et al. (Chinese Patent Application Publication CN 103401406 A, hereinafter “Lai”). Regarding claim 6, Wang does not disclose wherein the controller comprises a first flip-flop to a fourth flip-flop, in which the first flip-flop outputs a first inverted output signal, which is an inverted output signal of the first flip-flop, using a pulse width modulation clock signal, and simultaneously feeds back the first inverted output signal to a first input signal, which is an input signal of the first flip-flop, the second flip-flop outputs a second inverted output signal, which is an inverted output signal of the second flip-flop, using the first inverted output signal, and simultaneously feeds back the second inverted output signal to a second input signal, which is an input signal of the second flip-flop, the third flip-flop outputs a third inverted output signal, which is an inverted output signal of the third flip-flop, using the second inverted output signal, and simultaneously feeds back the third inverted output signal to a third input signal, which is an input signal of the third flip-flop, and the fourth flip-flop outputs a fourth inverted output signal, which is an inverted output signal of the fourth flip-flop, using the third inverted output signal, and simultaneously feeds back the fourth inverted output signal to a fourth input signal, which is an input signal of the fourth flip-flop. However, Lai teaches (see Fig. 3) wherein the controller (31) comprises a first flip-flop to a fourth flip-flop (D3 – D6), in which the first flip-flop (D3) outputs a first inverted output signal (xq of D3), which is an inverted output signal of the first flip-flop, using a pulse width modulation clock signal (LG to clk), and simultaneously feeds back the first inverted output signal to a first input signal (feedback to d of D3), which is an input signal of the first flip-flop (d of D3), the second flip-flop outputs a second inverted output signal (xq of D4), which is an inverted output signal of the second flip-flop, using the first inverted output signal (using xq of D3 input to clk of D4), and simultaneously feeds back the second inverted output signal to a second input signal (d of D4), which is an input signal of the second flip-flop (d of D4), the third flip-flop outputs a third inverted output signal (xq of D5), which is an inverted output signal of the third flip-flop, using the second inverted output signal (using xq of D4 input to clk of D5), and simultaneously feeds back the third inverted output signal to a third input signal (feedback to d of D5), which is an input signal of the third flip-flop (d of D5), and the fourth flip-flop outputs a fourth inverted output signal (xq of D6), which is an inverted output signal of the fourth flip-flop, using the third inverted output signal (using xq of D5 input to clk of D6), and simultaneously feeds back the fourth inverted output signal to a fourth input signal (feedback to d of D6), which is an input signal of the fourth flip-flop (d of D6). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the direct current to direct current converter of Wang wherein the controller comprises a first flip-flop to a fourth flip-flop, in which the first flip-flop outputs a first inverted output signal, which is an inverted output signal of the first flip-flop, using a pulse width modulation clock signal, and simultaneously feeds back the first inverted output signal to a first input signal, which is an input signal of the first flip-flop, the second flip-flop outputs a second inverted output signal, which is an inverted output signal of the second flip-flop, using the first inverted output signal, and simultaneously feeds back the second inverted output signal to a second input signal, which is an input signal of the second flip-flop, the third flip-flop outputs a third inverted output signal, which is an inverted output signal of the third flip-flop, using the second inverted output signal, and simultaneously feeds back the third inverted output signal to a third input signal, which is an input signal of the third flip-flop, and the fourth flip-flop outputs a fourth inverted output signal, which is an inverted output signal of the fourth flip-flop, using the third inverted output signal, and simultaneously feeds back the fourth inverted output signal to a fourth input signal, which is an input signal of the fourth flip-flop, as taught by Lai, because it can help implement a frequency divider in the pulse skip mode controller. Regarding claim 20, Wang does not disclose wherein the controller comprises a first flip-flop to a fourth flip-flop, in which the first flip-flop outputs a first inverted output signal, which is an inverted output signal of the first flip-flop, using a pulse width modulation clock signal, and simultaneously feeds back the first inverted output signal to a first input signal, which is an input signal of the first flip-flop, the second flip-flop outputs a second inverted output signal, which is an inverted output signal of the second flip-flop, using the first inverted output signal, and simultaneously feeds back the second inverted output signal to a second input signal, which is an input signal of the second flip-flop, the third flip-flop outputs a third inverted output signal, which is an inverted output signal of the third flip-flop, using the second inverted output signal, and simultaneously feeds back the third inverted output signal to a third input signal, which is an input signal of the third flip-flop, and the fourth flip-flop outputs a fourth inverted output signal, which is an inverted output signal of the fourth flip-flop, using the third inverted output signal, and simultaneously feeds back the fourth inverted output signal to a fourth input signal, which is an input signal of the fourth flip-flop. However, Lai teaches (see Fig. 3) wherein the controller (31) comprises a first flip-flop to a fourth flip-flop (D3 – D6), in which the first flip-flop (D3) outputs a first inverted output signal (xq of D3), which is an inverted output signal of the first flip-flop, using a pulse width modulation clock signal (LG to clk), and simultaneously feeds back the first inverted output signal to a first input signal (feedback to d of D3), which is an input signal of the first flip-flop (d of D3), the second flip-flop outputs a second inverted output signal (xq of D4), which is an inverted output signal of the second flip-flop, using the first inverted output signal (using xq of D3 input to clk of D4), and simultaneously feeds back the second inverted output signal to a second input signal (d of D4), which is an input signal of the second flip-flop (d of D4), the third flip-flop outputs a third inverted output signal (xq of D5), which is an inverted output signal of the third flip-flop, using the second inverted output signal (using xq of D4 input to clk of D5), and simultaneously feeds back the third inverted output signal to a third input signal (feedback to d of D5), which is an input signal of the third flip-flop (d of D5), and the fourth flip-flop outputs a fourth inverted output signal (xq of D6), which is an inverted output signal of the fourth flip-flop, using the third inverted output signal (using xq of D5 input to clk of D6), and simultaneously feeds back the fourth inverted output signal to a fourth input signal (feedback to d of D6), which is an input signal of the fourth flip-flop (d of D6). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the display device of Wang wherein the controller comprises a first flip-flop to a fourth flip-flop, in which the first flip-flop outputs a first inverted output signal, which is an inverted output signal of the first flip-flop, using a pulse width modulation clock signal, and simultaneously feeds back the first inverted output signal to a first input signal, which is an input signal of the first flip-flop, the second flip-flop outputs a second inverted output signal, which is an inverted output signal of the second flip-flop, using the first inverted output signal, and simultaneously feeds back the second inverted output signal to a second input signal, which is an input signal of the second flip-flop, the third flip-flop outputs a third inverted output signal, which is an inverted output signal of the third flip-flop, using the second inverted output signal, and simultaneously feeds back the third inverted output signal to a third input signal, which is an input signal of the third flip-flop, and the fourth flip-flop outputs a fourth inverted output signal, which is an inverted output signal of the fourth flip-flop, using the third inverted output signal, and simultaneously feeds back the fourth inverted output signal to a fourth input signal, which is an input signal of the fourth flip-flop, as taught by Lai, because it can help implement a frequency divider in the pulse skip mode controller.
Allowable Subject Matter
Claims 2, 5, 16, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 2, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the controller converts the pulse skip mode of the low-power mode into a pulse width modulation mode when the count value is equal to or greater than the reference count value.”. Regarding Claim 5, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the controller resets the count value when the skip control signal is at a relatively high level, counts the number of switching of the pulse width modulation signal and generates the count value when the skip control signal is at a relatively low level.”. Regarding Claim 16, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the controller converts the pulse skip mode of the low-power mode into a pulse width modulation mode when the count value is equal to or greater than the reference count value.”. Regarding Claim 19, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the controller resets the count value when the skip control signal is at a relatively high level, counts the number of switching of the pulse width modulation signal and generates the count value when the skip control signal is at a relatively low level.”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US Patent Application Publication US 2023/0198403 A1 discloses a short circuit detection function in a power conversion circuit. US Patent Application Publication US 2012/0212205 A1 discloses a pulse skipping overvoltage protection circuit in a power conversion circuit.
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/JYE-JUNE LEE/Examiner, Art Unit 2838
/JUE ZHANG/Primary Examiner, Art Unit 2838