DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15 is/are rejected under 35 U.S.C. 102(A)(1) as being anticipated by Ryou et al. (US 20180308638 A1; Ryou).
Regarding claim 15, Ryou discloses a capacitor component, comprising: a first capacitor structure (Fig. 4, 110/140; ¶36) including a substrate (Fig. 4, 110; ¶36) having a plurality of first trenches (Fig. 4, 130; ¶36) disposed on one surface of the substrate, and a first capacitor layer (Fig. 4, 140; ¶36) disposed on the one surface of the substrate and inner walls of the plurality of first trenches, the first capacitor layer including a first dielectric layer (Fig. 4, 145; ¶39) and first and second electrodes (Fig. 4, 141/142; ¶39) disposed to face each other with the first dielectric layer interposed therebetween; and a second capacitor structure (Fig. 4, 121/160; ¶82/84) disposed on the first capacitor structure, and including an insulating layer (Fig. 4, 122; ¶82/84) having a plurality of second trenches (Fig. 4, 150; ¶82/84) disposed on one surface of the insulating layer, and a second capacitor layer (Fig. 4, 160; ¶82/84) disposed on the one surface of the insulating layer and inner walls of the plurality of second trenches, the second capacitor layer including a second dielectric layer (Fig. 4, 165; ¶82/84) and third and fourth electrodes (Fig. 4, 122/160; ¶82/84) disposed to face each other with the second dielectric layer interposed therebetween, wherein the insulating layer includes silicon oxide (amorphous silicon is made by oxidizing to form a silicon oxide; ¶70), and when an interval between adjacent trenches among the plurality of first trenches is D1, an interval between adjacent trenches among the plurality of second trenches is D2, a depth of a trench among the plurality of first trenches is T1, and a depth of a trench among the plurality of second trenches is T2, D1> D2 and/or T1> T2 are satisfied. (Fig. 4; clear from drawings)
The inequality is claiming a high density capacitor structure over a lower density capacitor structure.
Allowable Subject Matter
Claims 1-20 allowed.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
US-20200294908-A1, US-20200035683-A1,US-20200135844-A1, US-20200294889-A1, US-20220359645-A1 discloses the claimed first and second capacitor structures, having via contacts on a bottom side of the substrate; but is silent on first and second external electrodes disposed on the insulating layer, and respectively connected to the first and second electrodes through the first and second wiring structures; and third and fourth external electrodes disposed on the insulating layer, and respectively connected to the third and fourth electrodes. US-20240047513-A1 discloses a substrate comprising a trench capacitor, a second substrate over the first substrate comprising a second capacitor. An interconnect structure above the second capacitor having vias connected to external contacts. (Fig. 6B)
CN-115497936 , US-20230361224-A1 discloses a first trench capacitor layer and a second trench capacitor layer stacked thereon, external contacts couple to the second capacitor electrodes, a single wiring structure penetrating the second capacitor layer and connected to the first capacitor by a wiring layer in the first capacitor structure. US-20200294908-A1, US-20200135844-A1, US-20210118618-A1 discloses a bottom capacitor structure and top capacitor structure on the bottom capacitor structure. The art is silent on the limitations cited below in combination with the rest of the claimed limitations.
Regarding claim 1, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " and third and fourth external electrodes disposed on the insulating layer, and respectively connected to the third and fourth electrodes.”, as recited in Claim 1, with the remaining features.
Claims 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 16, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " and third and fourth external electrodes disposed on the insulating layer, and respectively connected to the third and fourth electrodes..”, as recited in Claim 16, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899