Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 4, 6, 7, 9, 10, 12, 13, 15, 16, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Crump (US 5,875,463 A), hereinafter “Crump”, in view of Ogasawara (US 20080082779 A1), hereinafter “Ogasawara”.
With regards to claim 1, Crump teaches receiving within a processor a memory access request indicating a multi-bit physical memory address; (Col. 2 Lines 43-47 The PVP is interpreted as the processor.;
Col. 11 Lines 11-14 “The PVP instruction set is built on accessing memory and registers.”)
and fulfilling the memory access request in accordance with an addressing mode based on a bit pattern indicated by a first subset of bits of the multi-bit physical memory address, … (Col. 11 Line 59 – 63 “The upper eight bits of any memory address contain control bits that are used in conjunction with the lower twenty four bits of physical address space.”;
Col. 11 Lines 11-14 “No I/O space is architected into the PVP model except for the special addressing modes provided by the upper eight bits.”)
Crump does not teach:
the addressing mode comprising a type of interleaving to use for fulfilling the memory access request
However, Ogasawara does teach:
the addressing mode comprising a type of interleaving to use for fulfilling the memory access request (¶0110 In a full interleave mode 3300, the memory controller 1020 allocates a memory address alternately between the memories 1030a to 1030b connected to the memory controller 1020 via the channel 1070a, and the memories 1030m to 1030n connected to the memory controller 1020 via the channel 1070n, to all the channels 1070a to 1070n for each predetermined interleave size.
¶0112 In an m channel interleave mode 3400, the memory controller 1020, taking m channels as one unit, allocates a memory address for each predetermined interleave size alternately between the memories 1030a to 1030b connected to the memory controller 1020 via the channel 1070a, …
The interleave modes are seen as an addressing mode compromising a type of interleaving to use for fulfilling the memory access request.)
Crump and Ogasawara are analogous art because they are from the same field of endeavor, that being addressing modes. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method disclosed by Crump to have the addressing mode comprised of a type of interleaving to use for fulfilling memory access requests using the teaching of Ogasawara. The motivation would have been to accelerate access to the continuous memory addresses. (Ogasawara: ¶0115 Here, interleave means that when a memory address is allocated alternately to the memory 1030 connected to the channel 1070, memory addresses are allocated continuously spanning plural channels 1070. Hence, the CPU 1010 can accelerate access to the continuous memory addresses.)
With regards to claim 3, Crump does teach … the addressing mode to use for fulfilling the memory access request. (Crump: Col. 11 Line 59 - Col. 13 Line 15 Shows the different addressing modes and their bit patterns.(e.g. Stream Address Space, Broadcast Address Space, Look Ahead Address Space))
Crump does not teach:
determining a type of non-uniform memory access (NUMA) addressing associated with
However, Ogasawara does teach:
determining a type of non-uniform memory access (NUMA) addressing associated with (¶0222 In case of which computing computers 1001 comprise a Numa system, the construction of the memory zone 6000 may be a memory zone divided among each of the computing computer 1001.;
The computing computers 1001 includes the memory controller which comprises a NUMA system.)
Crump and Ogasawara are analogous art because they are from the same field of endeavor, that being addressing modes. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method disclosed by Crump determine a type of non-uniform memory access (NUMA) addressing associated with the addressing mode to use for fulfilling the memory access request using the teaching of Ogasawara. The motivation would have been to execute remote processes at high speed. (Ogasawara: ¶0069 For example, when a user wishes the computing computer 1001 to execute a remote process at high speed, it is better to increase the number of computing computers 1001 with which the parallel computing system is provided, than the number of the control computers 1000 with which the computing system is provided.)
With regards to claim 4, Crump teaches … fulfilling the memory access request. (Col. 11 Lines 11-12 “The PVP instruction set is built on accessing memory and registers.”)
Crump does not teach:
identifying a memory channel to use for
However, Ogasawara does teach:
identifying a memory channel to use for(¶ 0112 In an m channel interleave mode 3400, the memory controller 1020, taking m channels as one unit, allocates a memory address for each predetermined interleave size alternately between the memories 1030a to 1030b connected to the memory controller 1020 via the channel 1070a, and the memory 1030 connected to the memory controller 1020 via a channel m-1, and this is repeated up to the memories 1030m to 1030n connected to the memory controller 1020 via the channel 1070n.)
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the method disclosed by Crump to include memory channels to use for fulfilling the memory access request using the teaching of Ogasawara. The modification would be obvious because one of ordinary skill in the art would be motivated to reduce the power consumption of a main memory. (Ogasawara: ¶ 0002 This invention relates to a method of memory control and process control of a computing system, and particularly to a method of reducing the power consumption of a main memory taking account of program execution and process control.)
With regards to claim 6, Crump teaches determining the addressing mode based on an entry associated with the indicated bit pattern ... (Col. 11 Line 59 - Col. 13 Line 15 Shows the different addressing modes and their bit patterns.(e.g. Stream Address Space, Broadcast Address Space, Look Ahead Address Space)
Crump does not teach:
In an addressing mode table (AMT).
However, Ogasawara does teach:
In an addressing mode table (AMT). (FIG. 3 Element 2113; ¶ 0106 The memory addressing mode table 2113 includes an addressing mode 3000 and an addressing method 3100.)
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the method disclosed by Crump to add the addressing mode based on an entry associated with the indicated bit pattern to an addressing mode table (AMT) using the teaching of Ogasawara. The modification would be obvious because one of ordinary skill in the art would be motivated to increase the efficiency of the addressing mode selection by grouping the addressing modes and their bit patterns into a table.
With regards to claim 7, Crump teaches wherein the indicated bit pattern comprises N bits, and ... (Col. 11 Line 59 – 63 “The upper eight bits of any memory address contain control bits that are used in conjunction with the lower twenty four bits of physical address space.”)
Crump does not teach:
wherein the AMT comprises up to 2N distinct addressing modes.
However, Ogasawara does teach:
wherein the AMT comprises up to 2N distinct addressing modes. (FIG. 3 Element 2113 and 3000;
¶ 0106 The memory addressing mode table 2113 includes an addressing mode 3000 and an addressing method 3100.;
The addressing mode table shows at least 2 different addressing modes which is considered to be up to 2N distinct addressing modes.)
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the method disclosed by Crump to indicate the bit pattern to comprise of N bits, and to have the AMT comprise up to 2N distinct addressing modes using the teaching of Ogasawara. The modification would be obvious because one of ordinary skill in the art would be motivated to increase the efficiency of the addressing mode selection by grouping the addressing modes and their bit patterns into a table.
With regards to claim 9, Crump teaches wherein receiving the memory access request includes receiving a … multi-bit physical memory address. (Crump: Col. 11 Lines 16-19 “Each processor in the PVP can access any location in the sixteen MB address space or any address in the Host memory space up to thirty one bits of physical memory.”)
Crump does not teach:
a virtual memory address corresponding to the multi-bit physical memory address, and wherein the method further comprises translating the virtual memory address to generate the multi-bit physical memory address.
However, Ogasawara does teach:
a virtual memory address corresponding to the multi-bit physical memory address, and wherein the method further comprises translating the virtual memory address to generate the multi-bit physical memory address. (¶0016 In order to reduce the power consumed by the computing system, the memory controller has a logical/physical address translation table, and the memory controller operates the translation table so that the used memory area can be concentrated in any desired memory device.;
The logical/physical address translation table is interpreted to have logical addresses, interpreted as the claimed virtual memory addresses, and physical addresses, interpreted as the claimed multi-bit physical memory addresses. The logical/physical address translation table is interpreted to translate logical addresses (virtual memory addresses) to physical addresses (multibit-physical memory addresses).)
Crump and Ogasawara are analogous art because they are from the same field of endeavor, that being addressing modes. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method disclosed by Crump to receive a virtual memory address corresponding to the multi-bit physical memory address and further translate the virtual memory address to generate the multi-bit physical memory address, when receiving the memory access request using the teaching of Ogasawara. The motivation would have been to further reduce the power consumed by the computing system. (Ogasawara: (¶0016 In order to reduce the power consumed by the computing system, the memory controller has a logical/physical address translation table, and the memory controller operates the translation table so that the used memory area can be concentrated in any desired memory device.)
With regards to claim 10, Crump teaches A processing system … (Crump: Col. 2 Lines 43-47 The PVP is interpreted as the processor.;
Crump: Col. 11 Lines 11-14 “The PVP instruction set is built on accessing memory and registers.”):
receive a memory access request indicating a multi-bit physical memory address (Crump: Col. 11 Line 59 – 63 “The upper eight bits of any memory address contain control bits that are used in conjunction with the lower twenty four bits of physical address space.”);
and fulfill the memory access request in accordance with an addressing mode based on a bit pattern indicated by a first subset of bits of the multi-bit physical memory address … (Crump: Col. 11 Line 59 – 63 “The upper eight bits of any memory address contain control bits that are used in conjunction with the lower twenty four bits of physical address space.”;
Crump: Col. 11 Lines 11-14 “No I/O space is architected into the PVP model except for the special addressing modes provided by the upper eight bits.”)
Crump does not teach:
… comprising memory controller circuitry, the memory controller circuitry to …
wherein the addressing mode comprises one or more of a type of interleaving or an interleave size to use for fulfilling the memory access request.
However, Ogasawara does teach:
… comprising memory controller circuitry, the memory controller circuitry to … (¶0059 The memory controller 1020 has at least an addressing function which defines a memory address in the memory 1030, and a memory accessing function accessed by the CPU 1010.;
The memory controller is interpreted to be the claimed memory controller circuitry.)
wherein the addressing mode comprises one or more of a type of interleaving or an interleave size to use for fulfilling the memory access request. (¶0110 In a full interleave mode 3300, the memory controller 1020 allocates a memory address alternately between the memories 1030a to 1030b connected to the memory controller 1020 via the channel 1070a, and the memories 1030m to 1030n connected to the memory controller 1020 via the channel 1070n, to all the channels 1070a to 1070n for each predetermined interleave size.
¶0112 In an m channel interleave mode 3400, the memory controller 1020, taking m channels as one unit, allocates a memory address for each predetermined interleave size alternately between the memories 1030a to 1030b connected to the memory controller 1020 via the channel 1070a, …
The interleave modes are seen as an addressing mode compromising a type of interleaving to use for fulfilling the memory access request.)
Crump and Ogasawara are analogous art because they are from the same field of endeavor, that being addressing modes. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Crump to have the memory controller circuitry and the addressing mode to be comprised of one or more of a type of interleaving or an interleave size to use for fulfilling memory access requests using the teaching of Ogasawara. The motivation would have been to accelerate access to the continuous memory addresses. (Ogasawara: ¶0115 Here, interleave means that when a memory address is allocated alternately to the memory 1030 connected to the channel 1070, memory addresses are allocated continuously spanning plural channels 1070. Hence, the CPU 1010 can accelerate access to the continuous memory addresses.)
With regards to claim 12, Crump teaches … the addressing mode to use to fulfill the memory access request. (Col. 11 Lines 11-14 “No I/O space is architected into the PVP model except for the special addressing modes provided by the upper eight bits.”)
Crump does not teach:
wherein the memory controller circuitry is to determine a type of non-uniform memory access (NUMA) addressing associated with
However, Ogasawara does teach:
wherein the memory controller circuitry is to determine a type of non-uniform memory access (NUMA) addressing associated with (¶0222 In case of which computing computers 1001 comprise a Numa system, the construction of the memory zone 6000 may be a memory zone divided among each of the computing computer 1001.;
The computing computers 1001 includes the memory controller which comprises a NUMA system.)
Crump and Ogasawara are analogous art because they are from the same field of endeavor, that being addressing modes. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Crump to add the memory controller and the NUMA addressing to determine a type of non-uniform memory access (NUMA) addressing associated with the addressing mode to use to fulfill the memory access request using the teaching of Ogasawara. The motivation would have been to execute remote processes at high speed. (Ogasawara: ¶0069 For example, when a user wishes the computing computer 1001 to execute a remote process at high speed, it is better to increase the number of computing computers 1001 with which the parallel computing system is provided, than the number of the control computers 1000 with which the computing system is provided.)
With regards to claim 13, Crump teaches to use to fulfill the memory access request. (Crump: Col. 3 Lines 35-44 “The fact that all processors are on a common, single substrate allows for higher bandwidth communication between the processors and memory. A single bus 34, here called a line bus, has been chosen as the interconnect mechanism. The bus is very wide, i.e. it can transfer an entire cache line between caches 31, 32 or between a cache 31, 32 and memory interface 39 during each bus cycle. All processors 30 have a unified memory address space.”)
Crump does not teach:
wherein the addressing mode comprises a memory channel …
However, Ogasawara does teach:
wherein the addressing mode comprises a memory channel (Ogasawara: ¶ 0112 In an m channel interleave mode 3400, the memory controller 1020, taking m channels as one unit, allocates a memory address for each predetermined interleave size alternately between the memories 1030a to 1030b connected to the memory controller 1020 via the channel 1070a, and the memory 1030 connected to the memory controller 1020 via a channel m-1, and this is repeated up to the memories 1030m to 1030n connected to the memory controller 1020 via the channel 1070n.)
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the system disclosed by Crump to include memory channels to use for fulfilling the memory access request using the teaching of Ogasawara. The modification would be obvious because one of ordinary skill in the art would be motivated to reduce the power consumption of a main memory. (Ogasawara: ¶ 0002 This invention relates to a method of memory control and process control of a computing system, and particularly to a method of reducing the power consumption of a main memory taking account of program execution and process control.)
With regards to claim 15, Crump teaches wherein … is to determine the addressing mode based on an entry associated with the indicated bit pattern in an addressing mode table (AMT).
(Crump: Col. 11 Line 59 - Col. 13 Line 15 Shows the different addressing modes and their bit patterns.(e.g. Stream Address Space, Broadcast Address Space, Look Ahead Address Space);
FIG. 3 Element 2113; ¶ 0106 The memory addressing mode table 2113 includes an addressing mode 3000 and an addressing method 3100.)
Crump does not teach:
the memory controller circuitry
However, Ogasawara does teach:
the memory controller circuitry (¶0059 The memory controller 1020 has at least an addressing function which defines a memory address in the memory 1030, and a memory accessing function accessed by the CPU 1010.;
The memory controller is interpreted to be the claimed memory controller circuitry.)
Crump and Ogasawara are analogous art because they are from the same field of endeavor, that being addressing modes. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Crump to use the memory controller circuitry to determine the addressing mode based on an entry associated with the indicated bit pattern in an addressing mode table (AMT) using the teaching of Ogasawara. The motivation would have been to accelerate access to the continuous memory addresses. (Ogasawara: ¶0115 Here, interleave means that when a memory address is allocated alternately to the memory 1030 connected to the channel 1070, memory addresses are allocated continuously spanning plural channels 1070. Hence, the CPU 1010 can accelerate access to the continuous memory addresses.)
With regards to claim 16, Crump teaches wherein the indicated bit pattern comprises N bits, … (Crump: Col. 11 Line 59 – 63 “The upper eight bits of any memory address contain control bits that are used in conjunction with the lower twenty four bits of physical address space.”)
Crump does not teach:
… and wherein the AMT comprises up to 2N distinct addressing modes.
However, Ogasawara does teach:
… and wherein the AMT comprises up to 2N distinct addressing modes. (FIG. 3 Element 2113 and 3000;
¶ 0106 The memory addressing mode table 2113 includes an addressing mode 3000 and an addressing method 3100.;
The addressing mode table shows at least 2 different addressing modes which is considered to be up to 2N distinct addressing modes.)
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the system disclosed by Crump to indicate the bit pattern to comprise of N bits, and to have the AMT comprise up to 2N distinct addressing modes using the teaching of Ogasawara. The modification would be obvious because one of ordinary skill in the art would be motivated to increase the efficiency of the addressing mode selection by grouping the addressing modes and their bit patterns into a table.
With regards to claim 18, Crump teaches … the multi-bit physical memory address. (Crump: Col. 11 Line 59 – 63 “The upper eight bits of any memory address contain control bits that are used in conjunction with the lower twenty four bits of physical address space.”)
Crump does not teach:
comprising a memory management unit to translate a virtual memory address in order to generate the multi-bit physical memory address.
However, Ogasawara does teach:
comprising a memory management unit to translate a virtual memory address in order to generate the multi-bit physical memory address. (¶0016 In order to reduce the power consumed by the computing system, the memory controller has a logical/physical address translation table, and the memory controller operates the translation table so that the used memory area can be concentrated in any desired memory device.;
The logical/physical address translation table is interpreted to be the claimed memory management unit. The address translation table is interpreted to translate logical addresses (virtual memory addresses) to physical addresses (multibit-physical memory addresses).)
Crump and Ogasawara are analogous art because they are from the same field of endeavor, that being addressing modes. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Crump to comprise of a memory management unit to translate a virtual memory address in order to generate the multi-bit physical memory address using the teaching of Ogasawara. The motivation would have been to further reduce the power consumed by the computing system. (Ogasawara: (¶0016 In order to reduce the power consumed by the computing system, the memory controller has a logical/physical address translation table, and the memory controller operates the translation table so that the used memory area can be concentrated in any desired memory device.)
With regards to claim 19, Crump teaches … receive a memory access request indicating a multi-bit physical memory address; (Col. 11 Lines 11-14 “The PVP instruction set is built on accessing memory and registers.”
Crump: Col. 11 Lines 16-19 “Each processor in the PVP can access any location in the sixteen MB address space or any address in the Host memory space up to thirty one bits of physical memory.”;
The PVP instruction set being able to access memory and register is interpreted to mean that the system is able to receive/send memory access requests. The up to thirty one bits of physical memory is interpreted to be the claimed multi-bit physical memory address.)
and fulfill the memory access request in accordance with an addressing mode based on a bit pattern indicated by a first subset of bits of the multi-bit physical memory address, … (Col. 11 Line 59 – 63 “The upper eight bits of any memory address contain control bits that are used in conjunction with the lower twenty four bits of physical address space.”;
Col. 11 Lines 11-14 “No I/O space is architected into the PVP model except for the special addressing modes provided by the upper eight bits.”)
Crump does not teach:
A memory controller, the memory controller comprising circuitry to:
… wherein the addressing mode comprises one or more of a type of interleaving or an interleave size to use for fulfilling the memory access request.
However, Ogasawara does teach:
A memory controller, the memory controller comprising circuitry to: (¶0059 The memory controller 1020 has at least an addressing function which defines a memory address in the memory 1030, and a memory accessing function accessed by the CPU 1010.;
The memory controller is interpreted to be the claimed memory controller circuitry.)
… wherein the addressing mode comprises one or more of a type of interleaving or an interleave size to use for fulfilling the memory access request. (¶0110 In a full interleave mode 3300, the memory controller 1020 allocates a memory address alternately between the memories 1030a to 1030b connected to the memory controller 1020 via the channel 1070a, and the memories 1030m to 1030n connected to the memory controller 1020 via the channel 1070n, to all the channels 1070a to 1070n for each predetermined interleave size.
¶0112 In an m channel interleave mode 3400, the memory controller 1020, taking m channels as one unit, allocates a memory address for each predetermined interleave size alternately between the memories 1030a to 1030b connected to the memory controller 1020 via the channel 1070a, …;
The interleave modes are seen as an addressing mode compromising a type of interleaving to use for fulfilling the memory access request.)
Crump and Ogasawara are analogous art because they are from the same field of endeavor, that being addressing modes. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Crump to have the memory controller comprising circuitry and the addressing mode to be comprised of one or more of a type of interleaving or an interleave size to use for fulfilling memory access requests using the teaching of Ogasawara. The motivation would have been to accelerate access to the continuous memory addresses. (Ogasawara: ¶0115 Here, interleave means that when a memory address is allocated alternately to the memory 1030 connected to the channel 1070, memory addresses are allocated continuously spanning plural channels 1070. Hence, the CPU 1010 can accelerate access to the continuous memory addresses.)
Claim(s) 5, 8, 14, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Crump (US 5875463 A) in view of Ogasawara (US 20080082779 A1) as applied to claim 1, 7, 10, and 16 above, further in view of Zhang (US 20200272573 A1), hereinafter “Zhang”.
With regards to claim 5, Crump in view of Ogasawara teaches … the memory access request. (Crump: Col. 11 Lines 11-12 “The PVP instruction set is built on accessing memory and registers.”)
Crump in view of Ogasawara does not teach:
determining a memory encryption scheme to use for decoding
However, Zhang does teach:
determining a memory encryption scheme to use for decoding (¶ 0032 In order to ensure security of the memory space, a Total Memory Encryption (TME) scheme has been proposed, which is used to achieve the function of encrypting the overall physical memory of the system.)
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the system disclosed by Crump in view of Ogasawara to add a memory encryption scheme to use for decoding the memory access request using the teaching of Zhang. The modification would be obvious because one of ordinary skill in the art would be motivated to enhance the security of the computer system. (Zhang: ¶ 0029 As computer … Usually a software security management mechanism is added to prevent unauthorized visitors from entering the computer system with a falsified authorized identity, for example, users who are authorized (i.e., considered to be secure) can be allocated an identity, an access password is added, or access right is allocated to the user to allow access to only part of the data, thereby enhancing security of the computer system by managing the users.)
With regards to claim 8, Crump in view of Ogasawara teaches wherein the multi-bit physical memory address has a bit length of M bits (Crump: Col. 11 Lines 16-19 ”Each processor in the PVP can access any location in the sixteen MB address space or any address in the Host memory space up to thirty one bits of physical memory.”),
wherein the N bits are the most significant bits of the multi-bit physical memory address (Crump: Col.11 Line 59 – 63 “The upper eight bits of any memory address contain control bits that are used in conjunction with the lower twenty four bits of physical address space.”),
and wherein a physical memory space of the processor comprises a quantity of address locations ... (Crump: Col. 11 Lines 16 - 19)
Crump in view of Ogasawara do not teach:
wherein a physical memory space of the processor comprises a quantity of address locations that is addressable by no more than M - N bits.
However, Zhang does teach:
wherein a physical memory space of the processor comprises a quantity of address locations that is addressable by no more than M - N bits. (¶ 0034 Specifically, the ... In other words, the key identifier KeyID is carried by redefining certain bits on the physical address bus, that is, the physical address bus carries not only the address corresponding to the storage space but also encryption key information of the storage space.;
FIG.1 It would be obvious to say that the quantity of address locations that is addressable is no more than M (Physical address bus) - N (KeyID) when looking at FIG.1 in Zhang's application.)
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It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the method disclosed by Crump in view of Ogasawara to include the multi-bit physical memory address to have a bit length of M bits, wherein the N bits are the most significant bits of the multi-bit physical memory address, and wherein a physical memory space of the processor comprises a quantity of address locations that is addressable by no more than M - N bits using the teaching of Zhang. The modification would be obvious because one of ordinary skill in the art would be motivated to improve the management of address space. (Zhang: ¶0063 For example, once the hardware tag Tag 1 is allocated to the virtual machine 1, only the virtual machine 1 can learn the hardware tag Tag 1, and the remaining virtual machines may not learn the hardware tag Tag 1, and the software system in an addressing operation cannot read the identity information of the virtual machine in the address space to be addressed, thereby security of the address space management is improved.)
With regards to claim 14, Crump in view of Ogasawara teaches … the memory access request. (Crump: Col. 11 Lines 11-12 “The PVP instruction set is built on accessing memory and registers.”)
Crump in view of Ogasawara does not teach:
wherein the addressing mode comprises a memory encryption scheme to use to fulfill However, Zhang does teach:
wherein the addressing mode comprises a memory encryption scheme to use to fulfill (¶ 0032 In order to ensure security of the memory space, a Total Memory Encryption (TME) scheme has been proposed, which is used to achieve the function of encrypting the overall physical memory of the system.)
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the processing system disclosed by Crump in view of Ogasawara to add a memory encryption scheme to the addressing mode to use to fulfill the memory access request using the teaching of Zhang. The modification would be obvious because one of ordinary skill in the art would be motivated to enhance the security of the computer system. (Zhang: ¶ 0029 As computer … Usually a software security management mechanism is added to prevent unauthorized visitors from entering the computer system with a falsified authorized identity, for example, users who are authorized (i.e., considered to be secure) can be allocated an identity, an access password is added, or access right is allocated to the user to allow access to only part of the data, thereby enhancing security of the computer system by managing the users.)
With regards to claim 17, Crump in view of Ogasawara teaches wherein the multi-bit physical memory address has a bit length of M bits (Crump: Col. 11 Lines 16-19” Each processor in the PVP can access any location in the sixteen MB address space or any address in the Host memory space up to thirty one bits of physical memory.”),
wherein the N bits are the most significant bits of the multi-bit physical memory address (Crump: Col.11 Line 59 – 63 “The upper eight bits of any memory address contain control bits that are used in conjunction with the lower twenty four bits of physical address space.”),
and wherein a physical memory space of the processing system comprises a quantity of address locations ... (Crump: Col. 11 Lines 16-19)
Crump in view of Ogasawara does not teach:
wherein a physical memory space of the processing system comprises a quantity of address locations that is addressable by no more than M – N bits.
However, Zhang does teach:
wherein a physical memory space of the processing system comprises a quantity of address locations that is addressable by no more than M – N bits. (¶ 0034 Specifically, the … In other words, the key identifier KeyID is carried by redefining certain bits on the physical address bus, that is, the physical address bus carries not only the address corresponding to the storage space but also encryption key information of the storage space.;
FIG.1 It would be obvious to say that the quantity of address locations that is addressable is no more than M (Physical address bus) - N (KeyID) when looking at FIG.1 in Zhang's application.)
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It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the processing system disclosed by Crump in view of Ogasawara to include the multi-bit physical memory address to have a bit length of M bits, wherein the N bits are the most significant bits of the multi-bit physical memory address, and wherein a physical memory space of the processor comprises a quantity of address locations that is addressable by no more than M - N bits using the teaching of Zhang. The modification would be obvious because one of ordinary skill in the art would be motivated to improve the management of address space. (Zhang: ¶0063 For example, once the hardware tag Tag 1 is allocated to the virtual machine 1, only the virtual machine 1 can learn the hardware tag Tag 1, and the remaining virtual machines may not learn the hardware tag Tag 1, and the software system in an addressing operation cannot read the identity information of the virtual machine in the address space to be addressed, thereby security of the address space management is improved.”)
Response to Arguments
Applicant's arguments filed 09/19/2025 have been fully considered but they are not persuasive.
In response to Applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which Applicant relies (i.e., “selecting a type of memory interleaving”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
In response to Applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which Applicant relies (i.e., “encoding a memory interleave type in a subset of physical address bits for each memory request”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
In response to Applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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