DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 8/19/2026 have been fully considered but they are not persuasive.
Applicant argues that the Examiner equates the claim language with a deterministic test engine that induces errors to check the operation of components as taught in Mozak, and because the Examiner offers no explicit reasoning as to how the claim language is being construed before being compared to the cited art, Applicant is contending that the Examiner is making the assertion that a person of ordinary skill in the art would understand "a finite state machine configured to, during operation, check the data in the SRAM used by the first set of components of the SOC or the second set of components of the SOC for errors by... in response to sending the request to the memory controller, checking a first bank of the SRAM for one or more memory errors" to mean a deterministic test engine that induces errors to check the operation of components.
The Examiner disagrees with Applicant’s understanding of the Office Action and of the cited prior art (Mozak). In the cited passages of the Office Action, Mozark does not induce errors to check the operation of components, but rather performs testing techniques known in the prior art for determining the correct operation of a memory (see paragraph 41). Regardless of other additional features that Mozak may teach such as a deterministic test engine, the Examiner asserts that Mozark still teaches the plain meaning of the claim language. To be clear, the Examiner is asserting that Mozark teaches: a finite state machine (paragraph 43: “test engine 150 is implemented as a hardware finite state machine”) configured to check data in a RAM for errors (paragraph 42: executing a memory test for purposes such as debugging in paragraph 41 which would check the memory for errors) during operation (paragraph 51: “error recovery in system 100 will occur as in runtime operation”) by denying read and write access to a bank of RAM (paragraph 61; memory access requests are disabled for testing by test engine), and in response checking banks of a RAM for memory errors (paragraphs 43-44; testing is then performed once access requests are disabled). It is noteworthy that the plain meaning of the claim language, consistent with the specification, is met by Mozak as explicitly shown above.
Applicant further argues that Mozak contains no discussion as to the test engine checking or reading the data used by components of the system for errors and instead is limited to inducing errors so as to check the behavior of the memory system for faults.
The Examiner asserts that Mozark is not “limited to inducing errors so as to check the behavior of the memory system for faults” because Mozak teaches a plurality of different tests in paragraphs 45-52. Mozak teaches the test engine checking or reading the data used by components of the system in paragraph 51 (checking data for CRC errors).
Applicant argues that the Examiner has not provided a valid motivation to combine Case, Mozak, and Brewer because modifying Mozak based on Brewer to allow the memory address decoder and other components to still send memory access requests would leave the test engine vulnerable and would render Mozak's teaching unfit for its intended purpose.
The Examiner notes that Brewer is merely relied upon as a teaching reference for showing that a request (such as in Fig. 6, 605 of Brewer) is necessary for denying access (paragraph 74) since the memory controller controls access to the memory. The Office Action is not proposing modifying Mozak based on Brewer to allow the memory address decoder and other components to still send memory access requests.
With respect to claims 17-20, Applicant argues that Lordi is silent as to checking each bit in a bank of a RAM for errors and, in response to there being no errors in the bank, checking a sequentially next bank of the RAM; and that none of the other cited references remedy the deficiencies.
The Examiner notes that the limitations above are not fully taught by a single cited reference because the rejection relies on a combination of references, and it is the combination that teaches each claimed limitation. For Example, Lin2 teaches checking each bit of a bank for one or more memory errors (paragraph 48; Fig. 1, 12). Lin teaches in response to a memory bank not including a memory error, checking a next sequential bank of the plurality of banks for one or more memory errors; and in response to the bank including a memory error, writing corrected data to the bank and checking the next sequential bank of the plurality of banks for one or more memory errors (paragraph 30; when a page is read successfully with no error, a next sequential page is read. When a page includes an error, the error is corrected by ECC and the next sequential page is read). Taken in combination, the references teach each of the claimed limitations.
Applicant finally argues that the motivation for combining Lin2 is improper because the Examiner provides no explanation as to why modifying systems that do not check each bit of a bank for errors to then check each bit would reduce the time testing takes or why there would be any reasonable expectation of success and if anything, a person of ordinary skill in the art would understand that modifying a system to instead check each bit would take more time.
The Examiner acknowledges that a person of ordinary skill in the art would understand that modifying a system to instead check each bit would take more time, but one of ordinary skill in the art would also have considered that applying the teachings of Lin2 would have allowed the obvious benefit of checking each bit while reducing test time beyond what is conventional, as described by Lin2 in paragraph 15.
The Examiner disagrees with the Applicant and maintains all rejections of claims 1-20. All amendments and arguments by the Applicant have been considered. It is the Examiner’s conclusion that claims 1-20 are not patentably distinct or non-obvious over the prior art of record. Therefore, the rejection is maintained.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 6, 9, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Case et al (US Pat. Pub. 2016/0364343; hereinafter referred to as Case) in view of Mozak et al (US Pat. Pub. 2014/0095947; hereinafter referred to as Mozak) in view of Arya et al (US Pat. Pub. 2010/0125444; hereinafter referred to as Arya) in view of Brewer (US Pat. Pub. 2022/0121474).
As per claim 1: Case teaches a processing system comprising:
a random-access memory (RAM) (Fig. 1, 130) shared between a first domain and a second domain (Fig. 8, 802-806) of a system on a chip (SOC) (Fig. 1, 100), the first domain including a first set of components of the SOC configured to access data in the RAM during operation and the second domain including a second set of components of the SOC configured to access the data in the RAM during operation (paragraph 78; all components of the SOC 100 are configured to access the data in the RAM 130 during operation as shown).
Not explicitly disclosed is: a finite state machine configured to, during operation, check the data in the SRAM used by the first set of components of the SOC or the second set of components of the SOC for errors by: sending a request to a memory controller of the SRAM indicating that read and write access to a first bank of the SRAM is to be denied for the first set of components of the first domain and the second set of components of the second domain and in response to sending the request to the memory controller, checking a first bank of the RAM for one or more memory errors.
However, Mozak in an analogous art teaches a finite state machine (paragraph 43) configured to check data in a RAM for errors (paragraph 42) during operation (paragraph 51) by denying read and write access to a bank of RAM (paragraph 61; memory access requests are disabled for testing by test engine), and in response checking banks of a RAM for memory errors (paragraphs 43-44; testing is then performed once access requests are disabled). The Examiner notes that a request to the memory controller is necessary for denying access since the memory controller controls access to the memory. For instance, Brewer in an analogous art teaches a memory controller comprising an internal structure for denying read and write access to a memory prior to executing programmable instructions (paragraph 74; Fig. 6, 610) and in response to a request (Fig. 6, 605).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to check the memory of Case for errors concurrently with memory access being disabled for the first and second set of components. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have been a security feature to prevent access to the test engine by malicious code that could be trying to access protected memory contents through the test engine, as disclosed by Mozak in paragraph 61. It would be further obvious to request a memory controller to deny access since Mozak suggests denying access, and it is the function of the memory controller to deny access as shown by Brewer.
Also not explicitly disclosed is a static random-access memory (SRAM). However, Arya in an analogous art teaches an external directly addressable SRAM (Fig. 1, 16; (paragraph 13). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the SRAM of Arya in the system of Case. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Case suggests alternately using an external directly addressable RAM in paragraph 19, and Arya teaches in paragraph 13 that such a RAM may be SRAM or DRAM.
As per claim 9: Case teaches a method, comprising:
a first bank of a random-access memory (RAM) (Fig. 1, 130) shared between a first domain and a second domain (Fig. 8, 802-806) of a system on a chip (SOC) (Fig. 1, 100), the first domain including a first set of components of the SOC and the second domain including a second set of components of the SOC (paragraph 78).
Not explicitly disclosed is: a finite state machine configured to send a request to a memory controller of the SRAM indicating that read and write access to a first bank of the SRAM is to be denied for the first set of components of a first domain of a SOC and the second set of components of a second domain of the SOC and in response to sending the request to the memory controller, read data from the first bank of RAM and check the first bank of the RAM for one or more memory errors.
However, Mozak in an analogous art teaches denying read and write access to a bank of RAM (paragraph 61; memory access requests are disabled for testing by test engine), and in response checking banks of a RAM for memory errors (paragraphs 43-44; testing is then performed once access requests are disabled). The Examiner notes that a request to the memory controller is necessary for denying access since the memory controller controls access to the memory. For instance, Brewer in an analogous art teaches a memory controller comprising an internal structure for denying read and write access to a memory prior to executing programmable instructions (paragraph 74, Fig. 6, 610) and in response to a request (Fig. 6, 605).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to check the memory of Case for errors concurrently with memory access being disabled for the first and second set of components. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have been a security feature to prevent access to the test engine by malicious code that could be trying to access protected memory contents through the test engine, as disclosed by Mozak in paragraph 61. It would be further obvious to request a memory controller to deny access since Mozak suggests denying access, and it is the function of the memory controller to deny access as shown by Brewer.
Also not explicitly disclosed is a static random-access memory (SRAM). However, Arya in an analogous art teaches an external directly addressable SRAM (Fig. 1, 16; (paragraph 13). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the SRAM of Arya in the system of Case. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Case suggests alternately using an external directly addressable RAM in paragraph 19, and Arya teaches in paragraph 13 that such a RAM may be SRAM or DRAM.
Claim(s) 2 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Case in view of Mozak in view of Arya in view of Brewer in view of Astigarraga et al (US Pat. Pub. 2008/0195902; hereinafter referred to as Astigarraga).
As per claim 2: Case et a teach the processing system of claim 1. Not explicitly disclosed is wherein the finite state machine is configured to check the first bank of the RAM for one or more errors by implementing an error correction code. However, Astigarraga in an analogous art teaches checking a RAM for one or more errors by implementing an error correction code (paragraph 13).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use an ECC for testing the memory of Mozak. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it was a known way to recover from errors, as taught by Astigarraga in paragraph 13.
As per claim 10: Case et al teach the method of claim 9. Not explicitly disclosed is wherein checking the data from the first bank for one or more memory errors includes implementing an error correction code. However, Astigarraga in an analogous art teaches checking a RAM for one or more errors by implementing an error correction code (paragraph 13).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use an ECC for testing the memory of Mozak. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it was a known way to recover from errors, as taught by Astigarraga in paragraph 13.
Claim(s) 3 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Case in view of Mozak in view of Arya in view of Brewer in view of Tuan et al (US Pat. 7,477,073; hereinafter referred to as Tuan).
As per claim 3: Case et a teach the processing system of claim 1. Not explicitly disclosed is wherein the first domain is powered by a first power rail and the second domain is powered by a second power rail that is different from the first power rail. However, Tuan in an analogous art teaches a first domain (Fig. 5, 510a) powered by a first power rail (Fig. 5, 530a) and a second domain (Fig. 5, 510b) powered by a second power rail (Fig. 5, 530b) that is different from the first power rail (col. 7, lines 12-30).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to implement the power rails of Tuan to power the system of Case et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have provided power optimization in the supply voltage to different partitions, as disclosed by Tuan in col. 7, lines 12-30.
As per claim 11: Case et a teach the method of claim 9. Not explicitly disclosed is wherein the first domain is powered by a first power rail and the non-second domain is powered by a second power rail that is different from the first power rail. However, Tuan in an analogous art teaches a first domain (Fig. 5, 510a) powered by a first power rail (Fig. 5, 530a) and a second domain (Fig. 5, 510b) powered by a second power rail (Fig. 5, 530b) that is different from the first power rail (col. 7, lines 12-30).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to implement the power rails of Tuan to power the system of Case et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have provided power optimization in the supply voltage to different partitions, as disclosed by Tuan in col. 7, lines 12-30.
Claim(s) 4, 7, 8, 12, 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Case in view of Mozak in view of Arya in view of Brewer in view of Har et al (US Pat. 6,446,145; hereinafter referred to as Har).
As per claim 4: Case et a teach the processing system of claim 1. Not explicitly disclosed is wherein the finite state machine is configured to: check a second bank of the RAM based on a predetermined time interval elapsing after the finite state machine has checked the first bank of the RAM for one or more memory errors, wherein the second bank is a next sequential memory bank of the RAM as indicated by a memory address associated with the RAM. However, Har in an analogous art teaches checking a second bank of the RAM (Fig. 4A, 406-408) based on a predetermined time interval elapsing after checking a prior bank of the RAM for one or more memory errors (Fig. 4A, 402-404), wherein the second bank is a next sequential memory bank of the RAM as indicated by a memory address associated with the RAM (Fig. 4A, 408).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to incorporate a memory scrub as the test process 270 of Mozak. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have enabled detecting accumulated storage errors and correcting the data, as explained by Har in col. 6, lines 20-26.
As per claim 7: Case et a teach the processing system of claim 1. Not explicitly disclosed is wherein the finite state machine is configured to: concurrently with the memory controller denying read and write access to the first bank of the RAM by the first set of components of the first domain and the second set of components of the second domain and in response to detecting a single-bit memory error in the first bank, write corrected data into the first bank. However, Har in an analogous art teaches writing corrected data into a memory bank in response to detecting a single-bit memory error in the bank (Fig. 4A, 410; col. 6, lines 20-26).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to incorporate a memory scrub as the test process 270 of Mozak. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have enabled detecting accumulated storage errors and correcting the data, as explained by Har in col. 6, lines 20-26.
As per claim 8: Har further teaches the processing system of claim 7, wherein the finite state machine is configured to: send the request to the memory controller based on a predetermined period of time elapsing (Har teaches waiting a predetermined period of time in Fig. 4A, 402-404).
As per claim 12: Case et a teach the method of claim 9. Not explicitly disclosed is further comprising: checking a second bank of the RAM for one or more memory errors based on a predetermined time interval elapsing after the finite state machine has checked the first bank of the RAM for one or more memory errors, wherein the second bank is a next sequential memory bank of the RAM as indicated by a memory address associated with the RAM. However, Har in an analogous art teaches checking a second bank of the RAM (Fig. 4A, 406-408) based on a predetermined time interval elapsing after checking a prior bank of the RAM for one or more memory errors (Fig. 4A, 402-404), wherein the second bank is a next sequential memory bank of the RAM as indicated by a memory address associated with the RAM (Fig. 4A, 408).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to incorporate a memory scrub as the test process 270 of Mozak. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have enabled detecting accumulated storage errors and correcting the data, as explained by Har in col. 6, lines 20-26.
As per claim 15: Case et a teach the method of claim 9. Not explicitly disclosed is further comprising: concurrently with read and write access to a first bank of the RAM being disabled for the one or more components of the first domain and the one or more components of the second domain and in response to detecting a single-bit memory error in the first bank, writing corrected data into the first bank. However, Har in an analogous art teaches writing corrected data into a memory bank in response to detecting a single-bit memory error in the bank (Fig. 4A, 410; col. 6, lines 20-26).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to incorporate a memory scrub as the test process 270 of Mozak. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have enabled detecting accumulated storage errors and correcting the data, as explained by Har in col. 6, lines 20-26.
As per claim 16: Har further teaches the method of claim 15, further comprising: providing, to a memory controller, a request indicating that read and write access to the first bank of the RAM is to be disabled based on a predetermined period of time elapsing (Har teaches waiting a predetermined period of time in Fig. 4A, 402-404).
Claim(s) 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable Case in view of Mozak in view of Arya in view of Brewer in view of Von Bokern et al (US Pat. 5,987,628; hereinafter referred to as Von Bokern).
As per claim 5: Case et a teach the processing system of claim 1. Not explicitly disclosed is wherein the finite state machine is configured to: concurrently with checking the first bank of the RAM for one or more memory errors, receive a redirect request indicating a memory error in a second bank of the RAM; and in response to receiving the redirect request, check the second bank of the RAM for one or more errors. However, Von Bokern in an analogous art teaches a scrub buffer (Fig. 3, 50) that stores a memory scrub pointer for scrubbing memory addresses (col. 6, line 60- col. 7, line 1). An entry in the buffer indicates a memory error at the corresponding location of the RAM, and redirects the scrub control logic to check the location of the RAM (col. 7, lines 42-43).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to incorporate the memory scrub circuitry of Von Bokern in the combined system of Case et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have improved overall system reliability (col. 2, lines 61-65).
As per claim 13: Case et a teach the method of claim 9. Not explicitly disclosed is further comprising: concurrently with checking the first bank of the RAM for one or more memory errors, receiving, at the finite state machine, a redirect request indicating a memory error in a second bank of the RAM; and in response to receiving the redirect request, checking a second bank of the RAM for one or more errors. However, Von Bokern in an analogous art teaches a scrub buffer (Fig. 3, 50) that stores a memory scrub pointer for scrubbing memory addresses (col. 6, line 60- col. 7, line 1). An entry in the buffer indicates a memory error at the corresponding location of the RAM, and redirects the scrub control logic to check the location of the RAM (col. 7, lines 42-43).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to incorporate the memory scrub circuitry of Von Bokern in the combined system of Case et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have improved overall system reliability (col. 2, lines 61-65).
Claim(s) 6 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Case in view of Mozak in view of Arya in view of Brewer in view of Rinerson et al (US Pat. Pub. 2006/0028864; hereinafter referred to as Rinerson).
As per claim 6: Case et al teach the processing system of claim 1. Not explicitly disclosed is wherein the finite state machine is configured to: based on detecting a multi-bit memory error in the first bank, generate an interrupt. However, Rinerson in an analogous art teaches generating an interrupt based on detecting a multi-bit memory error (paragraph 46).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to generate an interrupt based on detecting a multi-bit memory error as taught by Rinerson. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have avoided data corruption (paragraph 46).
As per claim 14: Case et al teach the method of claim 9. Not explicitly disclosed is further comprising: based on detecting a multi-bit memory error in the first bank, generating an interrupt. However, Rinerson in an analogous art teaches generating an interrupt based on detecting a multi-bit memory error (paragraph 46).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to generate an interrupt based on detecting a multi-bit memory error as taught by Rinerson. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have avoided data corruption (paragraph 46).
Claim(s) 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lordi (US Pat. 5,611,042) in view of Tuan in view of Lin (US Pat. Pub. 2008/0320366) in view of Lin (US Pat. Pub. 2016/0372211; hereinafter referred to as Lin2).
As per claim 17: Lordi teaches a system comprising:
a first domain comprising a central processing unit (Fig. 6, 70);
a second domain (Fig. 6, 20);
a static random access memory (SRAM) (Fig. 1) shared between the first domain and the second domain (col. 2, lines 25-27 and col. 4, lines 13-15), the SRAM including a plurality of banks (Fig. 3), the first domain configured to access data in the plurality of banks during operation, and the second domain configured to access the data in the plurality of banks during operation (col. 4, lines 13-15); and
a finite state machine (Fig. 6 items 20 and 70: microcontroller 20 and a second processor 70, *Note: this interpretation is consistent with instant Fig. 2 item 200 that includes 2 boxes 205 and 215), during operation, configured to:
check each bank for one or more memory errors (col. 4, lines 39-41)
Not explicitly disclosed is:
the second domain powered independently from the first domain;
sequentially check corresponding data in each bank of the plurality of banks used by the first domain or the second domain for one or more memory errors by: checking each bit of the bank for one or more memory errors;
in response to the bank not including a memory error, checking a next sequential bank of the plurality of banks for one or more memory errors; and
in response to the bank including a memory error, writing corrected data to the bank and checking the next sequential bank of the plurality of banks for one or more memory errors.
However, Tuan in an analogous art teaches a first domain (Fig. 5, 510a) powered independently (col. 7, lines 12-30) from a second domain (Fig. 5, 510b). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to combine the invention of Lordi, with the feature of a first power rail 530a that provides a low supply voltage to a first partition 510a and a second power rail 530b that provides a high supply voltage to a second partition 510b in which the partitions can include block RAM as disclosed by Tuan (i.e., the primary area in lower memory of SRAM 1 of Lordi can be supplied one voltage by a first power rail and the backup area in upper memory of SRAM 1 of Lordi can be supplied another voltage by a second power rail in view of Tuan), with the motivation to provide power optimization in supply voltage to different partitions, as disclosed by Tuan in Col. 7 lines 12-30.
Also not explicitly disclosed is sequentially checking corresponding data in each bank of the plurality of banks used by the first domain or the second domain for one or more memory errors by: checking each bit of the bank for one or more memory errors. However, Lin2 in an analogous art teaches an error detection method comprising checking each bit of a bank for one or more memory errors (paragraph 48; Fig. 1, 12).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to employ the error detection scheme of Lin2 on the memory of Lordi. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have reduced test time (paragraph 15).
Also not explicitly disclosed is in response to the bank not including a memory error, checking a next sequential bank of the plurality of banks for one or more memory errors; and in response to the bank including a memory error, writing corrected data to the bank and checking the next sequential bank of the plurality of banks for one or more memory errors. However, Lin in an analogous art teaches in response to a memory bank not including a memory error, checking a next sequential bank of the plurality of banks for one or more memory errors; and in response to the bank including a memory error, writing corrected data to the bank and checking the next sequential bank of the plurality of banks for one or more memory errors (paragraph 30; when a page is read successfully with no error, a next sequential page is read. When a page includes an error, the error is corrected by ECC and the next sequential page is read).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the ECC method of Lin in the memory of Lordi et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have provided error correction and detection capability (paragraph 22).
Regarding claim 18, the combination of Lordi and Tuan further discloses wherein the finite state machine is configured to wait a predetermined time interval after checking each bank of the plurality of banks for one or more memory errors (see Lordi, Fig. 6 Col. 4 lines 30-42: In cases where a word read is performed, the second processor 70 has the ability to read an entire 16 bit word which may incorporate the primary area P1 and the primary area P2. In this manner, the communication between the two processors is performed via the shared SRAM. If an error is detected in the data read, the second processor 70 can initiate a second read of the same data from the backup area, i.e., the respective B1 area and B2 area and then perform a byte swap in order for the bytes to be in the proper sequence, and see Col. 3 lines 60-64: selects the backup information to be coupled to the processor if an error is indicated in the primary copy and not the backup copy).
Regarding claim 19, the combination of Lordi and Tuan further discloses wherein a first subset of the plurality of banks is assigned to the critical domain and a second subset of the plurality of banks is assigned to the second domain (see Lordi, Fig. 5 Col. 4 lines 1-7: SRAM 10 is allocated such that the primary area is in the lower memory address space and the backup area is in the upper memory address space).
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lordi in view of Tuan in view of Lin in view of Lin2 in view of Mozak in view of Brewer.
As per claim 20: Lordi et al teach the system of claim 17 above. Not explicitly disclosed is wherein the finite state machine is configured to sequentially check each bank of the plurality of the banks by sending, to a memory controller of the SRAM, a request to a memory controller of the SRAM indicating that read and write access to the bank is to be denied for components of the first domain and components of the second domain.
However, Mozak in an analogous art teaches denying read and write access to a bank of RAM (paragraph 61; memory access requests are disabled for testing by test engine), and in response checking banks of a RAM for memory errors (paragraphs 43-44; testing is then performed once access requests are disabled). The Examiner notes that a request to the memory controller is necessary for denying access since the memory controller controls access to the memory. For instance, Brewer in an analogous art teaches a memory controller comprising an internal structure for denying read and write access to a memory prior to executing programmable instructions (paragraph 74) and in response to a request (Fig. 6, 605).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to check the memory of Case for errors concurrently with memory access being disabled for the first and second set of components. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have been a security feature to prevent access to the test engine by malicious code that could be trying to access protected memory contents through the test engine, as disclosed by Mozak in paragraph 61. It would be further obvious to request a memory controller to deny access since Mozak suggests denying access, and it is the function of the memory controller to deny access as shown by Brewer.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE N NGUYEN whose telephone number is (571)272-7214. The examiner can normally be reached M-F 9-5.
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/STEVE N NGUYEN/Primary Examiner, Art Unit 2111
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